Search results for "multiple-clock-domain"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
58	Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott	Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.	HPCA	2002	DBLP DOI BibTeX RDF	Off-Line Analysis Tool, Dynamic Reconfiguration Algorithm, Low Power, Dynamic Voltage and Frequency Scaling, Multiple Clock Domain
51	Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Integrated CPU Cache Power Management in Multiple Clock Domain Processors.	HiPEAC	2008	DBLP DOI BibTeX RDF
36	Arun Rangasamy, Rahul Nagpal, Y. N. Srikant	Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	dvs, dynamic energy, energy, multiple clock domains
34	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Design of a Low-Power Clock Distribution Microarchitecture.	IEEE NAS	2007	DBLP DOI BibTeX RDF
32	Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho	Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor.	ISCA	2003	DBLP DOI BibTeX RDF
32	Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark	Formal Control Techniques for Power-Performance Management.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Power performance management, dynamic voltage, frequency sealing, chip multiprocessors, multiple-clock-domain
27	Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark	Formal online methods for voltage/frequency control in multiple clock domain microprocessors.	ASPLOS	2004	DBLP DOI BibTeX RDF	MCD processors, formal methods, dynamic voltage/frequency scaling
26	Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid	Clock-frequency assignment for multiple clock domain systems-on-a-chip.	DATE	2007	DBLP DOI BibTeX RDF
26	Hiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka	Frequency-hopping vernier clock generators for multiple clock domain SoCs.	CICC	2004	DBLP DOI BibTeX RDF
25	Alvin R. Albrecht, Alan J. Hu	Register Transformations with Multiple Clock Domains.	CHARME	2001	DBLP DOI BibTeX RDF
24	Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark	Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors.	HPCA	2005	DBLP DOI BibTeX RDF
24	Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott	Dynamic frequency and voltage control for a multiple clock domain microarchitecture.	MICRO	2002	DBLP DOI BibTeX RDF
20	Ji-Hoon Lim, Jong-Chan Ha, Won-Young Jung, Yong-Ju Kim, Jae-Kyung Wee	A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
17	Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa	A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity.	TENCON	2018	DBLP DOI BibTeX RDF
17	Joonho Kong, Kwangho Lee	A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
17	Shuo-Lian Hong, Kuen-Jong Lee	A run-pause-resume silicon debug technique for multiple clock domain systems.	ITC-Asia	2017	DBLP DOI BibTeX RDF
17	Shuo-Lian Hong, Kuen-Jong Lee	A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems.	ITC	2017	DBLP DOI BibTeX RDF
17	Djordje Maksimovic, Bao Le, Andreas G. Veneris	Multiple clock domain synchronization in a QBF-based verification environment.	ICCAD	2014	DBLP DOI BibTeX RDF
17	Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen	Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system.	APCCAS	2012	DBLP DOI BibTeX RDF
17	Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin 0001	Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA.	FPL	2010	DBLP DOI BibTeX RDF
17	Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu	Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Amirali Shayan Arani	Online thermal-aware scheduling for multiple clock domain CMPs.	SoCC	2007	DBLP DOI BibTeX RDF
17	Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande	Multiple clock domain synchronization for network on chip architectures.	SoCC	2007	DBLP DOI BibTeX RDF
17	Heiner Giefers, Achim Rettberg	Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	high-level synthesis, low power design, voltage scaling, bit-serial architecture
17	Anders Edman, Christer Svensson, Behzad Mesgarzadeh	Synchronous latency-insensitive design for multiple clock domain.	SoCC	2005	DBLP DOI BibTeX RDF
17	John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong	Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.	ISCA	2004	DBLP DOI BibTeX RDF
17	Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas, Michael L. Scott	Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor.	IEEE Micro	2003	DBLP DOI BibTeX RDF
17	Soha Hassoun, Charles J. Alpert	Optimal path routing in single- and multiple-clock domain systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
17	Soha Hassoun, Charles J. Alpert, Meera Thiagarajan	Optimal buffered routing path constructions for single and multiple clock domain systems.	ICCAD	2002	DBLP DOI BibTeX RDF
17	Octavian Petre, Hans G. Kerkhoff	Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers.	IOLTW	2001	DBLP DOI BibTeX RDF
15	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	SiPS	2006	DBLP DOI BibTeX RDF
11	Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi	An Interconnect Channel Design Methodology for High Performance Integrated Circuits.	DATE	2004	DBLP DOI BibTeX RDF
9	Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das	Coordinated power management of voltage islands in CMPs.	SIGMETRICS	2010	DBLP DOI BibTeX RDF	chip multiprocessors (CMP), control theory, GALs, DVFs
9	Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar	System level design and debug of high-performance embedded media systems (tutorial).	ICCAD	1999	DBLP BibTeX RDF
7	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	FPGA multiprocessor, Multiprocessor, System-on-chip, Network-on-chip, MPEG-4, MPSoC, On-chip interconnection
7	Ravi Surepeddi	System Verilog for Quality of Results (QoR).	ISQED	2008	DBLP DOI BibTeX RDF	System Verilog Design Quality Results
7	Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas	Hiding Synchronization Delays in a GALS Processor Microarchitecture.	ASYNC	2004	DBLP DOI BibTeX RDF
7	Grigorios Magklis, José González 0002, Antonio González 0001	Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2.	ICCD	2004	DBLP DOI BibTeX RDF