Search results for "multiple-gate"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Seung Min Lee, Hyun Jun Jang, Jong Tae Park 0003	Impact of back gate biases on hot carrier effects in multiple gate junctionless transistors.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
18	Mihir R. Choudhury, Kartik Mohanram	Reliability Analysis of Logic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
17	Vaidyanathan Subramanian, Abdelkarim Mercha, Bertrand Parvais, Morin Dehan, Guido Groeseneken, Willy M. C. Sansen, Stefaan Decoutere	Identifying the Bottlenecks to the RF Performance of FinFETs.	VLSI Design	2010	DBLP DOI BibTeX RDF	multiple gate FET, multi-gate FET, RF, FinFET
17	Hari Ananthan, Kaushik Roy 0001	A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.	DAC	2006	DBLP DOI BibTeX RDF	leakage distribution, multiple-gate, tri-gate, process variations, finFET, double-gate
12	Qi-Lin Gu, Peng Zhang, Yi Ru, Hao Song, Wen-Sheng Zhao, Wen-Yan Yin	A comparative study on electrothermal characteristics of nanoscale multiple gate MOSFETs.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
12	Fayçal Djeffal, Z. Ghoggali, Zohir Dibi, N. Lakhdar	Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
12	Jooyoung Song, Bo Yu, Yu Yuan, Yuan Taur	A Review on Compact Modeling of Multiple-Gate MOSFETs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
12	Alessio Griffoni	ESD and ionizing radiation effects on ultrathin body SOI and multiple gate technologies.		2009	RDF
12	Yuan Taur, Jooyoung Song, Bo Yu	Compact modeling of multiple-gate MOSFETs.	CICC	2008	DBLP DOI BibTeX RDF
12	Benjamín Iñíguez, Antonio Lázaro 0001, Hamdy Abd Elhamid, Oana Moldovan, Bogdan Nae, Jaume Roig, David Jiménez	Charge-Based Compact Modeling of Multiple-Gate MOSFET.	CICC	2007	DBLP DOI BibTeX RDF
10	Kelin J. Kuhn	CMOS scaling beyond 32nm: challenges and opportunities.	DAC	2009	DBLP DOI BibTeX RDF	high-k, CMOS, orientation, strain, metal-gate
5	Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir	Maximum circuit activity estimation using pseudo-boolean satisfiability.	DATE	2007	DBLP DOI BibTeX RDF

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