Search results for "multiplexers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
79	Mehran Dowlatshahi, S. K. De	A Numerical Method for Performance Analysis of ATM Multiplexers.	LCN	1997	DBLP DOI BibTeX RDF	numerical analysis method, performance analysis of ATM multiplexers, on-off bursty traffic, periodic traffic
78	Cheng-Shang Chang, Duan-Shin Lee, Chao-Kai Tu	Recursive construction of FIFO optical multiplexers with switched delay lines.	IEEE Trans. Inf. Theory	2004	DBLP DOI BibTeX RDF
70	Paul Metzgen, Dominic Nancekievill	Multiplexer restructuring for FPGA implementation cost reduction.	DAC	2005	DBLP DOI BibTeX RDF	busses, recoding, FPGA, synthesis, multiplexers, restructuring, logic optimization
58	Keshab K. Parhi	Low-energy CSMT carry generators and binary adders.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
55	Jay Cheng	Constructions of Optical 2-to-1 FIFO Multiplexers With a Limited Number of Recirculations.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
55	Emilia Sipos, Lelia Festila, Gabriel Oltean	Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers.	KES (3)	2008	DBLP DOI BibTeX RDF	Analog multiplexer, reconfigurable circuit, transmission gate, CMOS transistors, SUS-LOC
55	Ming-Bo Lin	On the design of fast large fan-in CMOS multiplexers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
46	Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki	SAT-based resource binding for reducing critical path delays.	FPL	2008	DBLP DOI BibTeX RDF
44	Dmitri Botvich, Nick G. Duffield	Large deviations, the shape of the loss curve, and economies of scale in large multiplexers.	Queueing Syst. Theory Appl.	1995	DBLP DOI BibTeX RDF	scaling limits, heterogeneous superpositions, Large deviations, ATM multiplexers
44	Glen G. Langdon Jr.	A Decomposition Chart Technique to Aid in Realizations with Multiplexers.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	Shannon's expansion, decomposition theory, residue functions, Combinational circuits, multiplexers, realization
44	Massimo Alioto, Gaetano Palumbo	Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
44	Cheng-Shang Chang, Duan-Shin Lee, Chao-Kai Tu	Using switched delay lines for exact emulation of FIFO multiplexers with variable length bursts.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
44	Ioanis Nikolaidis, Richard Fujimoto, C. Anthony Cooper	Time-Parallel Simulation of Cascaded Statistical Multiplexers.	SIGMETRICS	1994	DBLP DOI BibTeX RDF
41	Dipak Kumar Kole, Jhuma Dutta, Arpita Kundu, Suravi Chatterjee, Suravi Agarwal, Tanushri Kisku	Generalized construction of quantum multiplexers and de-multiplexers using a proposed novel algorithm based on universal Fredkin gate.	ISED	2016	DBLP DOI BibTeX RDF
35	X. Song, Mustafa K. Mehmet Ali	A Performance Analysis of Tandem Networks with Markovian Sources.	ITC	2007	DBLP DOI BibTeX RDF	Tandem networks, Markovian sources, PGF, multiplexers, variance, mean, queue length, packet delay
35	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
35	Verna J. Friesen, Johnny W. Wong	A case study in local area migration to ATM.	ICCCN	1995	DBLP DOI BibTeX RDF	local area migration, local ATM, ATM switched internetwork, switching hubs, ATM-equipped end devices, ATM backbone, ATM adaptation, campus environment, network components, end-to-end loss, asynchronous transfer mode, local area network, Ethernets, simulation results, routers, servers, simulation model, multiplexers, network performance, ATM switches, end-to-end delay, network configurations, clients
35	D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar	Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
35	Raffaele Bolla, Franco Davoli, Mario Marchese, Marco Perrando	Call Admission Control and Routing of QoS-Aware and Best-Effort Flows in an IP-over-ATM Networking Environment.	QoS-IP	2001	DBLP DOI BibTeX RDF
35	Parag K. Lala, Anup Singh, Alvernon Walker	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.	DFT	1999	DBLP DOI BibTeX RDF	DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
35	Sridhar Narayanan, Melvin A. Breuer	Reconfiguration techniques for a single scan chain.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
32	Jay Cheng	Constructions of Fault-Tolerant Optical 2-to-1 FIFO Multiplexers.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
32	Chih-Chieh Chou, Cheng-Shang Chang, Duan-Shin Lee, Jay Cheng	A Necessary and Sufficient Condition for the Construction of 2-to-1 Optical FIFO Multiplexers by a Single Crossbar Switch and Fiber Delay Lines.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
32	Masayuki Shirane, Akiko Gomyo, Kenta Miura, Yasuo Ohtera, Hirohito Yamada, Shojiro Kawakami	Optical add-drop multiplexers based on autocloned photonic crystals.	IEEE J. Sel. Areas Commun.	2005	DBLP DOI BibTeX RDF
32	Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen	An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
32	Kyoung-Sun Jhang, Kang Yi, Soo Yun Hwang	A Two-Level On-Chip Bus System Based on Multiplexers.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
32	Tony Stansfield	Using Multiplexers for Control and Data in D-Fabrix.	FPL	2003	DBLP DOI BibTeX RDF
32	Rosa Romero, Orlando Frazão, Filip Floreani, Lin Zhang, Paulo V. S. Marques, Henrique M. Salgado	Multiplexers and Demultiplexers Based on Fibre Bragg Gratings and Optical Circulators for DWDM Systems.	HSNMC	2003	DBLP DOI BibTeX RDF
32	Peng Yi, Yuguo Dong, Yuntao Li, Yunfei Guo	Stability Analysis of the PPS with Bufferless in Input De-Multiplexers.	AINA	2003	DBLP DOI BibTeX RDF
32	Martin Reisslein	Measurement-Based Admission Control: A Large Deviations Approach for Bufferless Multiplexers.	ISCC	2000	DBLP DOI BibTeX RDF	Bufferless Multiplexing, Measurement-Based Admission Control, Statistical Quality of Service, Large Deviations
32	Dusan Suvakovic, C. André T. Salama	Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	low power, DSP, energy consumption, switching, multiplexer, low voltage, register, datapath
32	Anwar Elwalid, Daniel P. Heyman, T. V. Lakshman, Debasis Mitra 0001, Alan Weiss	Fundamental Results on the Performance of ATM Multiplexers with Applications to Video Teleconferencing.	SIGMETRICS	1995	DBLP DOI BibTeX RDF
23	Fatemeh Eslami, Mihai Sima	Capacitive Boosting for FPGA Interconnection Networks.	FPL	2011	DBLP DOI BibTeX RDF	capacitive boosting, nMOS pass transistor multiplexers, FPGA interconnection network
23	Michel Mandjes, Ad Ridder	A large deviations analysis of the transient of a queue with many Markov fluid inputs: approximations and fast simulation.	ACM Trans. Model. Comput. Simul.	2002	DBLP DOI BibTeX RDF	importance sampling simulations, large deviations asymptotics, transient probabilities, buffer overflow, queuing theory, IP routers, calculus of variations, ATM multiplexers
23	Michel Mandjes, Ad Ridder	Optimal trajectory to overflow in a queue fed by a large number of sources.	Queueing Syst. Theory Appl.	1999	DBLP DOI BibTeX RDF	large deviations asymptotics, queueing theory, buffer overflow, calculus of variations, ATM multiplexers
23	Nick G. Duffield	Exponential bounds for queues with Markovian arrivals.	Queueing Syst. Theory Appl.	1994	DBLP DOI BibTeX RDF	risk theory, Queueing theory, large deviations, effective bandwidths, martingales, Markov Additive Processes, ATM multiplexers
23	Jehoshua Bruck, Robert Cypher, Ching-Tien Ho	Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	fault-tolerant meshes, d-dimensional mesh, performance evaluation, fault tolerant computing, hypercubes, hypercube networks, multiplexers, tori, fault-tolerant architecture, buses, hexagonal meshes
23	Kwang-Ya Fang, Anthony S. Wojcik	Modular Decomposition of Combinational Multiple-Valued Circuits.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	combinatorial multiple-values circuits, ternary functions, optimization, many-valued logics, multiplexers, combinatorial circuits, logic functions, modular decomposition
23	Raymond P. Voith	ULM Implicants for Minimization of Universal Logic Module Circuits.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	universal functions, optimization, logic design, integrated circuits, logic circuits, multiplexers, Boolean algebra, prime implicants
23	Frank M. Brown	Weighted Realizations of Switching Functions.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	tally-coded representations, multiplexers, combinational logic, symmetric functions, Binary adders
23	Seung Ho Ok, Byung In Moon	A Digit Reversal Circuit for the Variable-Length Radix-4 FFT.	FGCN (2)	2007	DBLP DOI BibTeX RDF
23	Kenji Asano, Junji Kitamichi, Kenichi Kuroda	Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems.	VLSI Design	2007	DBLP DOI BibTeX RDF
23	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.	VLSI Design	2007	DBLP DOI BibTeX RDF
23	Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones	Design space exploration for low-power reconfigurable fabrics.	IPDPS	2006	DBLP DOI BibTeX RDF
23	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen	VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	shape-adaptive, boundary extension, discrete wavelet transform, VLSI architecture
23	Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan	Leakage control in FPGA routing fabric.	ASP-DAC	2005	DBLP DOI BibTeX RDF
23	Jiong Luo, Lin Zhong 0001, Yunsi Fei, Niraj K. Jha	Register binding-based RTL power management for control-flow intensive designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
23	Arifur Rahman, Vijay Polavarapuv	Evaluation of low-leakage design techniques for field programmable gate arrays.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, leakage power, multiplexer
23	József Bíró, Zalán Heszberger, Mátyás Martinecz	A Family of Performance Bounds for QoS Measures in Packet-Based Networks.	NETWORKING	2004	DBLP DOI BibTeX RDF
23	Krishnendu Chakrabarty	A synthesis-for-transparency approach for hierarchical and system-on-a-chip test.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
23	Kayi Lee, Kai-Yeung Siu	On the reconfigurability of single-hub WDM ring networks.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	capacity ratio, hub traffic, approximation algorithm, reconfigurability, dynamic, wavelength division multiplexing (WDM), ring network
23	Michele Favalli, Cecilia Metra	Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths.	DATE	2002	DBLP DOI BibTeX RDF
23	Stefan R. Meier, Mario Steinert, Steffen Buch	Testability of path history memories with register-exchange architecture used in Viterbi-decoders.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
23	W. J. Bainbridge, Stephen B. Furber	Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding.	ASYNC	2001	DBLP DOI BibTeX RDF
23	Krishnendu Chakrabarty, Andrew Exnicios, Rajatish Mukherjee	Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip Test.	VLSI Design	2001	DBLP DOI BibTeX RDF
23	Bassam Shaer, David L. Landis, Sami A. Al-Arian	Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
23	Bassam Shaer, Sami A. Al-Arian, David L. Landis	Partitioning sequential circuits for pseudoexhaustive testing.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
23	Saud Andrew Al-Barrak, Adnan Andrew Nouh, Saad Haj Bakry	Computer simulation for the evaluation of static and dynamic priority schemes in an ATM multiplexer with multimedia traffic.	Int. J. Netw. Manag.	1999	DBLP DOI BibTeX RDF
23	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	A design-for-testability technique for register-transfer level circuits using control/data flow extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
23	A. Pal, R. K. Gorai, V. V. S. S. Raju	Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach
21	Hongji Fang, Zhenguo Ma, Feng Yu 0003, Bei Zhao, Bo Zhang 0097	Optimised Serial Commutator FFT Architecture in Terms of Multiplexers.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
21	Giuseppe E. Biccario, Oleg Vitrenko, Roberto Nonis, Stefano D'Amico	A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
21	Zeynep Kaya, Mario Garrido, Jarmo Takala	Memory-Based FFT Architecture With Optimized Number of Multiplexers and Memory Usage.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
21	Erfan Abbasian, Maedeh Orouji, Sana Taghipour Anvari, Alireza Asadi, Ehsan Mahmoodi	An ultra-low power and energy-efficient ternary Half-Adder based on unary operators and two ternary 3:1 multiplexers in 32-nm GNRFET technology.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
21	Yun Gao, Noah Pestana, Skylar Deckoff-Jones, Jiajiu Zheng, Jordan Goldstein, Andrew M. Netherton, Ren-Jye Shiue, Michael R. Watts, Christopher V. Poulton	Passive Integrated Athermal (De)Multiplexers on 300 mm Silicon Photonics Wafers.	OFC	2023	DBLP DOI BibTeX RDF
21	Jin-Xu Xu, Mo Huang, Su-Li Song, Hui-Yang Li	Compact Multichannel Filters and Multiplexers Based on Dual-Coaxial Resonators.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
21	Mario Garrido, Pedro Paz	Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
21	B. Jeevan, Kosaraju Sivani	Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
21	Angela Amphawan, Sushank Chaudhary, Tse-Kian Neo, Mohsen Kakavand, Mohammad Dabbagh	Radio-over-free space optical space division multiplexing system using 3-core photonic crystal fiber mode group multiplexers.	Wirel. Networks	2021	DBLP DOI BibTeX RDF
21	Adriana N. Borodzhieva, Ivanka D. Tsvetkova, Dimitar Dimitrov	Technology-Enhanced Active Learning Used for Teaching "Multiplexers and Demultiplexers".	MIPRO	2021	DBLP DOI BibTeX RDF
21	Karol Niewiadomski, Dietmar Tutsch	A New Concept for Multiplexers in Interconnect Blocks of FPGAs.	ICCE	2021	DBLP DOI BibTeX RDF
21	Karsten Schuh, Qian Hu, Roman Dischler, Vahid Aref, Fred Buchali, Son Thai Le, Michael Collisi, Michael Möller 0004, Horst Hettrich, Rolf Schmid, Xuan-Quang Du, Markus Grözing, Manfred Berroth	High-speed IM/DD transmission with analog (de-)multiplexers.	ECOC	2021	DBLP DOI BibTeX RDF
21	Kevin Jin, Tahsin Saffat, Justin Morgan, Marek A. Perkowski	A Polarity-based Approach for Optimization of Multivalued Quantum Multiplexers with Arbitrary Single-qubit Target Gates.	FLAP	2020	DBLP BibTeX RDF
21	Ramzi A. Jaber, Ali M. Haidar 0001, Abdallah Kassem	CNTFET-Based Design of Ternary Multiplier using Only Multiplexers.	ICM	2020	DBLP DOI BibTeX RDF
21	Anh Due Ta, Danilo Vasconcellos Vargas	Towards improvement of SUNA in multiplexers with preliminary results of simple logic gate neuron variation.	GECCO Companion	2020	DBLP DOI BibTeX RDF
21	Junya Takano, Takeshi Fujisawa, Yusuke Sawada, Kunimasa Saitoh	Low-Loss Silicon 2 × 4λ Multiplexers Composed of On-Chip Polarization-Splitter-Rotator and 2 × 2 and 2 × 1 Mach-Zehnder Filters for 400GbE.	OFC	2020	DBLP BibTeX RDF
21	Joel Carpenter	Multi-plane light conversion based mode multiplexers.	ECOC	2020	DBLP DOI BibTeX RDF
21	Kevin Jin, Tahsin Saffat, Marek A. Perkowski	A Reed Muller-based approach for optimization of general binary quantum multiplexers.	CoRR	2019	DBLP BibTeX RDF
21	José Eduardo Henriques da Silva, Heder Soares Bernardino	A 3-Step Cartesian Genetic Programming for Designing Combinational Logic Circuits with Multiplexers.	EPIA (1)	2019	DBLP DOI BibTeX RDF
21	Chenlei Li, Hao Wu, Ying Tan, Shipeng Wang, Daoxin Dai	Silicon-based on-chip hybrid (de)multiplexers.	Sci. China Inf. Sci.	2018	DBLP DOI BibTeX RDF
21	Suhas Lohit, Rajhans Singh, Kuldeep Kulkarni, Pavan K. Turaga	Rate-Adaptive Neural Networks for Spatial Multiplexers.	CoRR	2018	DBLP BibTeX RDF
21	Chetan Vudadha, Ajay Surya, Saurabh Agrawal, M. B. Srinivas	Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
21	Yong Chen 0005, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins	A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
21	Tomoyuki Akiyama, Tsuyoshi Aoki, Takasi Simoyama, Akio Sugama, Shigeaki Sekiguchi, Yohei Sobu, Shinsuke Tanaka, Yu Tanaka, Seok-Hwan Jeong, Motoyuki Nishizawa, Nobuaki Hatori, Akinori Hayakawa, Toshihiko Mori	Error-Free Loopback of a Compact 25 Gb/s × 4 ch WDM Transceiver Assembly Incorporating Silicon (De)Multiplexers with Automated Phase-Error Correction.	OFC	2018	DBLP BibTeX RDF
21	G. R. Kavitha, T. S. Indumathi	Quality of Service (QoS) Aware Reconfigurable Optical Add/Drop Multiplexers (ROADM) Model with Minimizing the Blocking Rate.	CSOC (3)	2018	DBLP DOI BibTeX RDF
21	Nicolas K. Fontaine, Roland Ryf, Haoshuo Chen, Steffen Wittek, Jiaxiong Li, Juan Carlos Alvarado, Jose Enrique Antonio-Lopez, Mark Cappuzzo, Rose Kopf, Alaric Tate, Hugo Safar, Cristian A. Bolle, David T. Neilson, Ellsworth Burrows, K. W. Kim, Pierre Sillard, Frank Achten, Marianne Bigot, Adrian Amezcua Correa, Rodrigo Amezcua Correa, Jiangbing Du, Zuyuan He, Joel Carpenter	Packaged 45-Mode Multiplexers for a 50-µm Graded Index Fiber.	ECOC	2018	DBLP DOI BibTeX RDF
21	Bitao Pan, Fulong Yan, Xuwei Xue, Nicola Calabretta	Performance Assessment of Metro Networks Based on Fast Optical Add-Drop Multiplexers Under 5G Traffic Applications.	ECOC	2018	DBLP DOI BibTeX RDF
21	Xifan Tang, Giovanni De Micheli, Pierre-Emmanuel Gaillardon	A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers.	IEEE Trans. Emerg. Top. Comput.	2017	DBLP DOI BibTeX RDF
21	Sanda Lefteriu, Martine Olivi, Fabien Seyfert, Matteo Oldoni	System identification of microwave filters from multiplexers by rational interpolation.	Autom.	2017	DBLP DOI BibTeX RDF
21	Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon	Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
21	Stephan Friedrichs, Attila Kinali	Efficient Metastability-Containing Multiplexers.	ISVLSI	2017	DBLP DOI BibTeX RDF
21	Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon	Physical Design Considerations of One-level RRAM-based Routing Multiplexers.	ISPD	2017	DBLP DOI BibTeX RDF
21	T. A. Birks, Stephanos Yerolatsitis, Kerrianne Harrington	Adiabatic mode multiplexers.	OFC	2017	DBLP BibTeX RDF
21	Nicolas K. Fontaine, Roland Ryf, Haoshuo Chen, David T. Neilson, Joel Carpenter	Design of High Order Mode-Multiplexers using Multiplane Light Conversion.	ECOC	2017	DBLP DOI BibTeX RDF
21	Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri	Design of efficient QCA multiplexers.	Int. J. Circuit Theory Appl.	2016	DBLP DOI BibTeX RDF
21	Kumar H. B. Chethan, Nachiket Kapre	Hoplite-DSP: Harnessing the Xilinx DSP48 multiplexers to efficiently support NoCs on FPGAs.	FPL	2016	DBLP DOI BibTeX RDF
21	Rodrigo Amezcua Correa	All-fiber mode multiplexers.	OFC	2016	DBLP BibTeX RDF
21	Jonathan St-Yves, Sophie LaRochelle, Wei Shi 0007	O-band silicon photonic Bragg-grating multiplexers using UV lithography.	OFC	2016	DBLP BibTeX RDF
21	Daoxin Dai	Multi-channel wavelength/mode-division-multiplexers on silicon.	OFC	2016	DBLP BibTeX RDF
21	Xueyan Wang, Xiaotao Jia, Qiang Zhou 0001, Yici Cai, Jianlei Yang 0001, Mingze Gao, Gang Qu 0001	Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.	ACM Great Lakes Symposium on VLSI	2016	DBLP DOI BibTeX RDF