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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 2778 publication records. Showing 2778 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
97 | K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr. |
Parallel reduced area multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 9(3), pp. 181-191, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
74 | Shreesha Srinath, Katherine Compton |
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 51-58, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asymmetric multipliers, composable multipliers, multiplier design |
74 | Oscal T.-C. Chen, Sandy Wang, Yi-Wen Wu |
Minimization of switching activities of partial products for designing low-power multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 418-433, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
67 | Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang |
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 492-499, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams |
67 | Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
An effective BIST scheme for carry-save and carry-propagate array multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 298-302, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic |
62 | Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume |
A Black Hen Lays White Eggs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CARDIS ![In: Smart Card Research and Advanced Applications, 8th IFIP WG 8.8/11.2 International Conference, CARDIS 2008, London, UK, September 8-11, 2008. Proceedings, pp. 74-88, 2008, Springer, 978-3-540-85892-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
double-size technique, RSA, smartcard, Montgomery multiplication, efficient implementation |
59 | Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Effective Built-In Self-Test for Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(3), pp. 105-111, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Booth multipliers, Built-In Self Test, design for testability, data paths |
59 | Alok A. Katkar, James E. Stine |
Modified booth truncated multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 444-447, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VLSI, arithmetic |
54 | Suthikshn Kumar, Kevin E. Forward, Marimuthu Palaniswami |
A fast-multiplier generator for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 53-56, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fast-multiplier generator, variable word length multipliers, Booth encoded optimized Wallace tree architecture, field programmable gate arrays, FPGAs, parallel architectures, artificial neural networks, multiplying circuits, FPGA architecture, neural chips |
51 | Francisco Rodríguez-Henríquez, Çetin Kaya Koç |
Parallel Multipliers Based on Special Irreducible Pentanomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(12), pp. 1535-1542, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
pentanomials, multipliers for GF(2^m), Finite fields arithmetic, parallel multipliers |
51 | Kiamal Z. Pekmastzi |
Multiplexer-Based Array Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(1), pp. 15-23, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiplication algorithm, two's complement multiplication, pipeline multipliers, Array multipliers |
51 | Issam Alzaher-Noufal, Michael Nicolaidis |
A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 122-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Fault Secure Circuits, Residue Arithmetic Codes, Multipliers, Self-Checking Circuits |
51 | Ravi Kumar Satzoda, Ramya Muralidharan, Chip-Hong Chang |
Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 808-811, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Haining Fan, M. Anwar Hasan |
A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 224-233, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
subquadratic space complexity multiplier, shifted polynomial basis, Finite field, coordinate transformation, Toeplitz matrix |
51 | Michal Bidlo |
Evolutionary Design of Generic Combinational Multipliers Using Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 77-88, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Arash Reyhani-Masoleh, M. Anwar Hasan |
Low Complexity Word-Level Sequential Normal Basis Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(2), pp. 98-110, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Finite field, optimal normal basis, Massey-Omura multiplier |
51 | Arash Reyhani-Masoleh, M. Anwarul Hasan |
Low Complexity Sequential Normal Basis Multipliers over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 188-195, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Finite field, optimal normal basis, Massey-Omura multiplier |
51 | Nan-Ying Shen, Oscal T.-C. Chen |
Low-power multipliers by minimizing switching activities of partial products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 93-96, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte |
Analysis of Column Compression Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 33-39, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
51 | Avinash K. Gautam, V. Visvanathan, S. K. Nandy 0001 |
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 285-288, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela Araújo Cunha |
Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS multipliers, distortion, analog multipliers |
46 | Gopalakrishnan Lakshminarayanan, B. Venkataramani |
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(7), pp. 783-793, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
An Effective Built-In Self-Test Scheme for Parallel Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(9), pp. 936-950, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
tree multipliers, Built-in self-test, array multipliers, cell fault model |
43 | Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos |
Efficient Diminished-1 Modulo 2^n+1 Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(4), pp. 491-496, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Modulo 2^n+1 multipliers, Fermat number transform, computer arithmetic, VLSI design, residue number system |
43 | Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos |
Modified Booth Modulo 2n-1 Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(3), pp. 370-374, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Mersenne arithmetic, one's complement arithmetic, Booth multipliers, VLSI design, Residue Number System |
43 | T. Sansaloni, Javier Valls, Keshab K. Parhi |
Digit-Serial Complex-Number Multipliers on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 105-115, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding |
43 | Roman A. Polyak |
Log-Sigmoid Multipliers Method in Constrained Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 101(1-4), pp. 427-460, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
log-sigmoid, multipliers method, smoothing technique, duality |
43 | Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand |
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(7), pp. 628-637, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
inverse square root, single-/double-precision operations, small multipliers, exponential, square root, Reciprocal, logarithm, Taylor series |
43 | Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos |
Low Power BIST for Wallace Tree-Based Fast Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 433-438, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Testing, Low Power, BIST, Multipliers, Wallace Trees |
43 | Sebastian T. J. Fenn, Michael Gössel, Mohammed Benaissa, David Taylor |
On-Line Error Detection for Bit-Serial Multipliers in GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(1), pp. 29-40, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
finite fields, multipliers, parity checking, on-line error detection |
43 | Michael Nicolaidis, Ricardo de Oliveira Duarte |
Design of Fault-Secure Parity-Prediction Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 7-14, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Booth multipliers, Self-checking circuits |
43 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis |
C-Testable modified-Booth multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 241-260, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model |
43 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
Design tradeoffs in high speed multipliers and FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 29-32, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed |
43 | Hakim Bederr, Michael Nicolaidis, Alain Guyot |
Analytic approach for error masking elimination in on-line multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 30-37, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead |
43 | Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar |
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(10), pp. 1306-1311, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier |
43 | Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu |
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(9), pp. 1061-1070, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
irreducible AOP, finite field, montgomery multiplication, irreducible trinomial, Bit-parallel systolic multiplier |
43 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Built-in sequential fault self-testing of array multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 449-460, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
Low-voltage micropower multipliers with reduced spurious switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4078-4081, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Kenny Johansson, Oscar Gustafsson, Lars Wanhammar |
Low-complexity bit-serial constant-coefficient multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 649-652, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Jean-Luc Beuchat |
Some Modular Adders and Multipliers for Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 190, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
modulo m addition, modulo m multiplication, FPGA, Computer arithmetic |
43 | Tong Zhang 0002, Keshab K. Parhi |
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(7), pp. 734-749, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Finite (or Galois) field, standard basis, complexity, multiplication, VLSI architecture, irreducible polynomials, Toeplitz matrix |
43 | Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian |
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 15-21, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Tim Courtney, Richard H. Turner, Roger F. Woods |
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 341-343, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo |
Fast FPGA-based pipelined digit-serial/parallel multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 482-485, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Richard C. North, Walter H. Ku |
beta-bit serial/parallel multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(4), pp. 219-233, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
39 | Oliver A. Pfänder, Reinhard Nopper, Hans-Jörg Pfleiderer, Shun Zhou, Amine Bermak |
Configurable Blocks for Multi-precision Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 478-481, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reconfigurable multipliers, embedded blocks, multi-precision, FPGA, multiplication |
38 | Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu |
Energy-aware probabilistic multiplier: design and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 281-290, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, multiplier, voltage scaling, probabilistic computation |
38 | R. Mahesh 0001, A. Prasad Vinod 0001 |
A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 217-229, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang |
A self-compensation fixed-width booth multiplier and its 128-point FFT applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Zhijun Huang, Milos D. Ercegovac |
High-Performance Low-Power Left-to-Right Array Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 272-283, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design |
38 | Yirng-An Chen, Randal E. Bryant |
An efficient graph representation for arithmetic circuitverification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12), pp. 1443-1454, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | J. Living, M. Moniri, S. B. Tennakoon |
Efficient Recursive Digital Filters using Combined Look-Ahead Denominator Distribution and Numerator Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 27(3), pp. 269-295, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
IIR digital filters, iteration bound, look ahead pipelining, resource minimisation |
38 | Sandro Wefel, Paul Molitor |
Prove that a faulty multiplier is faulty!? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 43-46, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Gerardo Orlando, Christof Paar |
A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 232-239, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography |
38 | Yirng-An Chen, Randal E. Bryant |
PHDD: an efficient graph representation for floating point circuit verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 2-7, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
KFDD, *BMD, HDD, K*BMD, Verification, Formal Verifications, BDD, Floating Point, FDD, BMD |
36 | Patrizia Daniele |
Lagrange multipliers and infinite-dimensional equilibrium problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Glob. Optim. ![In: J. Glob. Optim. 40(1-3), pp. 65-70, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Separation theory, Quasi relative interior, Lagrange multipliers, Equilibrium problems |
36 | Robert T. Grisamore, Earl E. Swartzlander Jr. |
Negative Save Sign Extension for Multi-term Adders and Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(1), pp. 1-11, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers |
36 | Pasquale Malacaria, Han Chen |
Lagrange multipliers and maximum information leakage in different observational models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLAS ![In: Proceedings of the 2008 Workshop on Programming Languages and Analysis for Security, PLAS 2008, Tucson, AZ, USA, June 8, 2008, pp. 135-146, 2008, ACM, 978-1-59593-936-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
security, information theory, lagrange multipliers |
36 | Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan |
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 422-430, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable |
36 | Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell |
High-level synthesis for large bit-width multipliers on FPGAs: a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 213-218, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA devices, large-scale integer multipliers, high level synthesis, reconfigurable computing, design exploration |
36 | Lisa A. Korf |
Stochastic programming duality: 8 multipliers for unbounded constraints with an application to mathematical finance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 99(2), pp. 241-259, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
arbitrage, fundamental theorem of asset pricing, duality, stochastic programming, Lagrange multipliers |
36 | Kiamal Z. Pekmestzi, Paraskevas Kalivas |
Constant Number Serial Pipeline Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 26(3), pp. 361-368, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
constant number multiplication, serial multipliers, systolic circuits, canonic signed digit representation |
36 | Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou |
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 121-129, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing |
36 | Luca Breveglieri, Luigi Dadda, Vincenzo Piuri |
Column Compression Pipelined Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 93-103, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pipelining, computer arithmetic, multipliers |
35 | Alexey F. Izmailov, Mikhail V. Solodov |
On attraction of Newton-type iterates to multipliers violating second-order sufficiency conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 117(1-2), pp. 271-304, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classification (2000) 90C30 |
35 | Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki |
Power Optimization of Parallel Multipliers in Systems with Variable Word-Length. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 103-115, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi |
A New Family of High.Performance Parallel Decimal Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 195-204, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Michal Bidlo |
Evolutionary Development of Generic Multipliers: Initial Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 405-412, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson |
Transition-activity aware design of reduction-stages for parallel multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 120-125, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power consumption, parallel multiplier, partial product reduction, transition activity |
35 | José Luis Imaña, Juan Manuel Sánchez, Francisco Tirado |
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 520-533, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Finite (or Galois) fields, canonical basis, triangular basis, complexity, permutation, multiplication, cycles, matrix decomposition, transpositions, irreducible trinomials |
35 | Magnus Karlsson, Mark Vesterbacka |
Digit-serial/parallel multipliers with improved throughput and latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Nima Honarmand, Ali Afzali-Kusha |
Low Power Combinational Multipliers using Data-driven Signal Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1430-1433, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi |
FPGA designs of parallel high performance GF(2233) multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 268-271, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Jiunn-Chern Chen, Yirng-An Chen |
Equivalence checking of integer multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 169-174, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Ron Balczewski, Ramesh Harjani |
Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 508-511, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Pierre L'Ecuyer, Richard J. Simard |
Beware of linear congruential generators with multipliers of the form a = ±2q ±2r. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Math. Softw. ![In: ACM Trans. Math. Softw. 25(3), pp. 367-374, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
correlation test, random number generation, linear congruential generators |
35 | Leilei Song, Keshab K. Parhi |
Low-complexity modified Mastrovito multipliers over finite fields GF(2M). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 508-512, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Thomas K. Callaway, Earl E. Swartzlander Jr. |
Power-Delay Characteristics of CMOS Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 26-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
35 | Michael Gössel, Sebastian T. J. Fenn, David Taylor |
On-line error detection for finite field multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 307-312, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
on-line error detection circuit, parity prediction, simulation, fault coverage, multiplying circuits, hardware overhead, finite field multiplier |
35 | Martin Keim, Michael Martin 0002, Bernd Becker 0001, Rolf Drechsler, Paul Molitor |
Polynomial Formal Verification of Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 150-157, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Binary Moment Diagram (BMD), Verification, Multiplier |
31 | Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato |
Integer Multiplication with Overflow Detection or Saturation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(7), pp. 681-691, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
unsigned, tree multipliers, computer arithmetic, array multipliers, Overflow, saturation, integer, two's complement |
31 | Ajay Kumar Verma, Paolo Ienne |
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 601-608, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers |
31 | Cheng-Yu Pai, Asim J. Al-Khalili, William E. Lynch |
Low-Power Constant-Coefficient Multiplier Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 35(2), pp. 187-194, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
constant multipliers, low power, VHDL, DSP, design automation, integer multiplication |
31 | Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume |
Unbridle the Bit-Length of a Crypto-coprocessor with Montgomery Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Selected Areas in Cryptography ![In: Selected Areas in Cryptography, 13th International Workshop, SAC 2006, Montreal, Canada, August 17-18, 2006 Revised Selected Papers, pp. 188-202, 2006, Springer, 978-3-540-74461-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RSA, smartcard, Montgomery multiplication, crypto-coprocessor |
31 | Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi |
A Large Scale Adaptable Multiplier for Cryptographic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 477-484, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis |
Binary Multiplication based on Single Electron Tunneling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 152-166, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Zhijun Huang, Milos D. Ercegovac |
High-Performance Left-to-Right Array Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 4-11, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima |
Efficient construction of binary moment diagrams for verifying arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 78-82, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
word-level verification, binary moment diagram, arithmetic circuit, design verification |
28 | Valeria Garofalo, Nicola Petra, Ettore Napoli |
Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 60(9), pp. 1366-1371, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
truncated multipliers, maximum error, digital arithmetic, error analysis, Multiplication, error compensation |
28 | Igor V. Evstigneev, Sjur Didrik Flåm |
Stochastic Programming: Nonanticipativity and Lagrange Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Optimization ![In: Encyclopedia of Optimization, Second Edition, pp. 3783-3789, 2009, Springer, 978-0-387-74758-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Nonanticipativity, Fritz John conditions, Yosida-Hewitt decomposition, Stochastic programming, Lagrange multipliers |
28 | Marc Teboulle |
Lagrangian Multipliers Methods for Convex Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Encyclopedia of Optimization ![In: Encyclopedia of Optimization, Second Edition, pp. 1813-1818, 2009, Springer, 978-0-387-74758-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Proximal algorithms, Convex optimization, Augmented Lagrangians, Primal-dual methods, Lagrangian multipliers |
28 | Pachara V. Rao, Cyril Prasanna Raj, S. Ravi 0001 |
VLSI Design and Analysis of Multipliers for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IIH-MSP ![In: Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), Kyoto, Japan, 12-14 September, 2009, Proceedings, pp. 1354-1357, 2009, IEEE Computer Society, 978-1-4244-4717-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Low Power, Delay, CMOS, Multipliers, Area, ASIC Implementation |
28 | Lucia Parussini |
Fictitious Domain Approach Via Lagrange Multipliers with Least Squares Spectral Element Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Sci. Comput. ![In: J. Sci. Comput. 37(3), pp. 316-335, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Fictitious Domain, Least Squares Spectral Element Method, Lagrange multipliers |
28 | Katsushi Ohmori, Norikazu Saito |
Flux-free Finite Element Method with Lagrange Multipliers for Two-fluid Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Sci. Comput. ![In: J. Sci. Comput. 32(2), pp. 147-173, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Two-fluid flows, flux-free constraint, mass preserving, finite element method, Lagrange multipliers |
28 | Hesham A. Al-Twaijry, Michael J. Flynn |
Technology Scaling Effects on Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(11), pp. 1201-1215, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Feature size, topology, multipliers, Booth encoding |
28 | Weng-Fai Wong, Eiichi Goto |
Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(3), pp. 278-294, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
hardware-based algorithms, elementary function computations, rectangular multipliers, common elementary functions, reciprocal square root, arc tangent, microscopic parallelism, floating point multiplication, scientific computations, digital arithmetic, error analysis, sine, cosine |
28 | Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao |
Berger Check Prediction for Array Multipliers and Array Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 892-896, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Berger check prediction, array dividers, closed-form check-predicting equations, digital arithmetic, multiplying circuits, array multipliers, dividing circuits |
28 | Alexander Skavantzos, Poornachandra B. Rao |
New Multipliers Modulo 2^N - 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 957-961, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
modulo 2/sup N/-1, ROM bits, digital arithmetic, multiplication, multipliers, multiplying circuits, additions, squaring, look-up tables, cyclic convolution |
28 | Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa |
Pseudorandom Rounding for Truncated Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(9), pp. 1065-1067, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
truncated multipliers, pseudorandom rounding, digital arithmetic, multiplications, rounding, floating-point numbers, multiple-precision |
28 | Stamatis Vassiliadis, Eric M. Schwarz, Baik Moon Sung |
Hard-Wired Multipliers with Encoded Partial Products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(11), pp. 1181-1197, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
hardwired multipliers, encoded partial products, multibit overlapped scanning multiplication algorithm, sign-magnitude, encoding, digital arithmetic, multiplying circuits, two's complement |
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