Search results for "multiported"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Nathan Kalyanasundharam, Nital Patwa	Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor.	ICCD	1999	DBLP DOI BibTeX RDF	multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance
93	Jessica H. Tseng, Krste Asanovic	Banked Multiported Register Files for High-Frequency Superscalar Microprocessors.	ISCA	2003	DBLP DOI BibTeX RDF
50	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee	A High-Bandwidth Memory Pipeline for Wide Issue Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Data bandwidth, runtime stack, data stream partitioning, multiported data cache, instruction level parallelism, data locality
50	Ronald F. DeMara, Dan I. Moldovan	The SNAP-1 Parallel AI Prototype.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	SNAP-1 parallel AI prototype, Semantic Network Array Processor, marker-propagation paradigm, natural languageunderstanding, multiprocessing clusters, dedicated communication units, tiered synchronization scheme, multiported memorynetwork, speech analysis andprocessing, knowledge representation, parallel architecture, parallel architectures, natural languages, reasoning, inference mechanisms, semantic networks, speech processing, digital signal processors, special purpose computers, parallelmachines
41	Jessica H. Tseng, Krste Asanovic	A Speculative Control Scheme for an Energy-Efficient Banked Register Fil.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	speculative control, Low-power, superscalar, register file, simultaneous multithreading
31	Inayat Ullah, Zahid Ullah, Jeong-A Lee	Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA.	IEEE Access	2018	DBLP DOI BibTeX RDF
31	Bo-Cheng Charles Lai, Jiun-Liang Lin	Efficient Designs of Multiported Memory on FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
31	Bo-Cheng Charles Lai, Kun-Hua Huang	An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
31	Ameer M. S. Abdelhadi, Guy G. F. Lemieux	Modular Switched Multiported SRAM-Based Memories.	ACM Trans. Reconfigurable Technol. Syst.	2016	DBLP DOI BibTeX RDF
31	Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han 0003, Xingxing Zhang, Zhang Zhang, Xu Cheng 0002, Zhiyi Yu	Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
31	Paul Sack, William Gropp	Collective Algorithms for Multiported Torus Networks.	ACM Trans. Parallel Comput.	2015	DBLP DOI BibTeX RDF
31	Tahsin Turker Mutlugun, Sheng-De Wang	OpenCL computing on FPGA using multiported shared memory.	FPL	2015	DBLP DOI BibTeX RDF
31	Erfan Azarkhish, Igor Loi, Luca Benini	A high-performance multiported L2 memory IP for scalable three-dimensional integration.	3DIC	2013	DBLP DOI BibTeX RDF
31	Deepa Yagain, Ankit Parakh, Akriti Kedia, Gunjan Kumar Gupta	Design and Implementation of High Speed, Low Area Multiported Loadless 4T Memory Cell.	ICETET	2011	DBLP DOI BibTeX RDF
31	Fakhar Anjam, Stephan Wong, Faisal Nadeem	A multiported register file with register renaming for configurable softcore VLIW processors.	FPT	2010	DBLP DOI BibTeX RDF
31	Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin	Investigating Simple Low Latency Reliable Multiported Register Files.	ISVLSI	2007	DBLP DOI BibTeX RDF
31	Smaïl Niar, Lieven Eeckhout, Koenraad De Bosschere	Comparing Multiported Cache Schemes.	PDPTA	2003	DBLP BibTeX RDF
31	Mike J. G. Lewis, L. E. M. Brackenbury	Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank.	ASYNC	2001	DBLP DOI BibTeX RDF
31	Pascal Sainrat, Abdelaziz Mzoughi, Christine Rochange, Daniel Litaize	The Design of the M3S: A Multiported Shared-Memory Multiprocessor.	SC	1992	DBLP DOI BibTeX RDF
29	Muhamed F. Mudawar	Scalable cache memory design for large-scale SMT architectures.	WMPI	2004	DBLP DOI BibTeX RDF	scalable multiported cache memory, simultaneous multithreaded architectures
20	Tom Van Court, Martin C. Herbordt	Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique.	FPL	2006	DBLP DOI BibTeX RDF
20	Michael B. Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	microprocessors, distributed architectures, Interconnection architectures
20	Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose	Complexity-Effective Reorder Buffer Designs for Superscalar Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
20	Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras	Implementing branch-predictor decay using quasi-static memory cells.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Energy aware computing
20	Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.	HPCA	2003	DBLP DOI BibTeX RDF
20	Preeti Ranjan Panda, Nikil D. Dutt	Behavioral Array Mapping into Multiport Memories Targeting Low Power.	VLSI Design	1997	DBLP DOI BibTeX RDF
20	Murthy V. Devarakonda, Bill Kish, Ajay Mohindra	Recovery in the Calypso File System.	ACM Trans. Comput. Syst.	1996	DBLP DOI BibTeX RDF	Calypso, distributed state, state reconstruction, cluster systems
20	Todd M. Austin, Gurindar S. Sohi	High-Bandwidth Address Translation for Multiple-Issue Processors.	ISCA	1996	DBLP DOI BibTeX RDF
20	Rick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider	Teramac-configurable custom computing.	FCCM	1995	DBLP DOI BibTeX RDF
20	Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé	Using Sacks to Organize Registers in VLIW Machines.	CONPAR	1994	DBLP DOI BibTeX RDF
20	Christine Rochange, Pascal Sainrat, Daniel Litaize	Performance of M3S for the SOR algorithm.	PARLE	1993	DBLP DOI BibTeX RDF
20	M. Chastain, G. Gostin, James E. Mankovich, Steven J. Wallach	The convex C240 architecture.	SC	1988	DBLP DOI BibTeX RDF