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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 20 occurrences of 18 keywords
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Results
Found 23 publication records. Showing 23 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
123 | Zhanglei Wang, Krishnendu Chakrabarty |
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(2-3), pp. 145-161, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nanofabric, CAEN, chemically assembled, reconfiguration, BIST, nanotechnology, defect tolerance, molecular electronics |
113 | Kushal Datta, Arindam Mukherjee 0001, Arun Ravindran |
Automated design flow for diode-based nanofabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 2(3), pp. 219-241, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Automatic synmthesis, optimization |
68 | Mohammad Tehranipoor |
Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 305-313, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
55 | Wenjing Rao, Alex Orailoglu, Ramesh Karri |
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 214-221, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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33 | Jason G. Brown, R. D. (Shawn) Blanton |
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(2-3), pp. 131-144, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fault diagnostic accuracy, nanofabrication, regular architectures, nanoFabric, fault diagnosis, logic testing, reconfigurability, integrated circuit testing, fault coverage, nanoelectronics, high defect densities |
32 | Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor |
3D SRAM Macro Design in 3D Nanofabric Process Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(7), pp. 2858-2867, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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32 | Edouard Giacomin, Francky Catthoor, Pierre-Emmanuel Gaillardon |
Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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32 | Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon |
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers, pp. 279-300, 2020, Springer, 978-3-030-81640-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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32 | Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon |
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 34-39, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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32 | Abdalrahman M. Arafeh, Sadiq M. Sait |
Cells reconfiguration around defects in CMOS/nanofabric circuits using simulated evolution heuristic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 581-588, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
32 | Sadiq M. Sait, Abdalrahman M. Arafeh |
Tabu search based cells placement in nanofabric architectures with restricted connectivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013, pp. 487-493, 2013, IEEE, 978-1-4673-4951-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | J. G. Alzate, Parag Upadhyaya, M. Lewis, J. Nath, Y. T. Lin, Kin Wong, S. Cherepov, P. Khalili Amiri, Kang L. Wang, J. Hockel, A. Bur, G. P. Carman, S. Bender, Y. Tserkovnyak, J. Zhu, Y.-J. Chen, I. N. Krivorotov, J. Katine, J. Langer, Prasad Shabadi, Santosh Khasanvis, Sankara Narayanan Rajapandian, Csaba Andras Moritz, Alexander Khitun |
Spin wave nanofabric update. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012, pp. 196-202, 2012, ACM, 978-1-4503-1671-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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32 | Prasad Shabadi, Alexander Khitun, Kin Wong, P. Khalili Amiri, Kang L. Wang, Csaba Andras Moritz |
Spin wave functions nanofabric update. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, USA, June 8-9, 2011, pp. 107-113, 2011, IEEE Computer Society, 978-1-4577-0993-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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32 | Stefano Frache, Luca Gaetano Amarù, Mariagrazia Graziano, Maurizio Zamboni |
Nanofabric power analysis: Biosequence alignment case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, USA, June 8-9, 2011, pp. 91-98, 2011, IEEE Computer Society, 978-1-4577-0993-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
32 | Mandar V. Joshi, Waleed Al-Assadi |
Nanofabric PLA Architecture with Double Variable Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDES ![In: Proceedings of the 2007 International Conference on Computer Design, CDES 2007, Las Vegas, Nevada, USA, June 25-28, 2007, pp. 17-21, 2007, CSREA Press, 1-60132-036-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
32 | Mandar V. Joshi, Waleed Al-Assadi |
Nanofabric PLA architecture with Redundancy Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 427-435, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Jason G. Brown, R. D. (Shawn) Blanton |
CAEN-BIST: Testing the NanoFabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 462-471, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Mohammad Tehranipoor, Reza M. Rad |
Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 943-958, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Chen He, Margarida F. Jacome |
Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 817-833, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Wenjing Rao, Alex Orailoglu, Ramesh Karri |
Towards Nanoelectronics Processor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(2-3), pp. 235-254, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fault tolerance, reliability, computational model, processor architecture, nanoelectronics, time redundancy, hardware redundancy |
23 | Hossein Asadi 0001, Mehdi Baradaran Tahoori, Chandra Tirumurti |
Estimating Error Propagation Probabilities with Bounded Variances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 41-49, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Mohammad Tehranipoor, Reza M. Rad |
Test and recovery for fine-grained nanoscale architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 226, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Chen He, Margarida F. Jacome |
RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1179-1184, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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