Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
51 | Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Isolating Short-Lived Operands for Energy Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(6), pp. 697-709, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
49 | Sivaram Gopalakrishnan, Priyank Kalla, Florian Enescu |
Optimization of Arithmetic Datapaths with Finite Word-Length Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 511-516, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
arithmetic datapaths, finite word length, operands, polynomial computations, finite integer rings, CAD, area optimization, bit vectors |
47 | Ilhyun Kim, Mikko H. Lipasti |
Half-Price Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 28-38, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Gyula Magó |
Copying operands versus copying results: A solution to the problem of large operands in FFP'S. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPCA ![In: Proceedings of the 1981 conference on Functional programming languages and computer architecture, FPCA 1981, Wentworth, New Hampshire, USA, October 1981, pp. 93-98, 1981, ACM, 0-89791-060-5. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
|
44 | Belle W. Y. Wei, He Du, Honglu Chen |
A complex-number multiplier using radix-4 digits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 84-, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme |
42 | Kaijie Wu 0001, Ramesh Karri |
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3), pp. 413-422, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Anthony S. Fong |
A computer architecture with access control and cache option tags on individual instruction operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 31(3), pp. 1-5, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
operand descriptor, optional encaching, system attributes, access control, data coherency |
42 | Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Reducing Datapath Energy through the Isolation of Short-Lived Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA, pp. 258-268, 2003, IEEE Computer Society, 0-7695-2021-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Masaaki Kondo, Hiroshi Nakamura |
A Small, Fast and Low-Power Register File by Bit-Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 40-49, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Brian R. Mestan, Mikko H. Lipasti |
Exploiting Partial Operand Knowledge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October 2003, Kaohsiung, Taiwan, pp. 369-378, 2003, IEEE Computer Society, 0-7695-2017-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Norman Ramsey |
Relocating Machine Instructions by Currying. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), Philadephia, Pennsylvania, USA, May 21-24, 1996, pp. 226-236, 1996, ACM, 0-89791-795-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
35 | Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup |
An IWS Montgomery Modular Multiplication Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 234-239, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
RNS Montgomery modular multiplication algorithm, very large operands, mixed radix, processor ring, redundant high-radix implementation, residue number systems, residue number system, computation time, table look-up |
35 | Geoff Barrett |
Formal Methods Applied to a Floating-Point Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 15(5), pp. 611-621, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
floating-point number system, binary floating-point arithmetic, ANSI/IEEE Std. 754-1985, set-theoretic specification language, sequential components, unpack, operands, proven rules, mathematically rigorous method, Inmos IMS T800 transputer, formal specification, formal methods, specification languages, digital arithmetic, Z, formalization, round, pack, program development, IEEE standard, floating-point unit, internal representations |
33 | Maziar Goudarzi, Tohru Ishihara |
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 383-386, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
asymmetric sram, leakage, instruction cache, register renaming |
33 | Namrata Shekhar, Priyank Kalla, Florian Enescu |
Equivalence verification of arithmetic datapaths with multiple word-length operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 824-829, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Daehong Kim, Dongwan Shin, Kiyoung Choi |
Pipelining with common operands for power-efficient linear systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(9), pp. 1023-1034, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Tongquan Wei, Kaijie Wu 0001, Ramesh Karri, Alex Orailoglu |
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1192-1195, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Kaushal R. Gandhi, Nihar R. Mahapatra |
A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 426-, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Jean-Michel Muller |
Complex Division with Prescaling of Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 304-314, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou |
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 211-217, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra |
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 155-163, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Brian R. Nickerson |
Graph Coloring Register Allocation for Processors with Multi-Register Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'90 Conference on Programming Language Design and Implementation (PLDI), White Plains, New York, USA, June 20-22, 1990, pp. 40-52, 1990, ACM, 0-89791-364-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Intel 80960 |
28 | Jatan P. Shah, Rama Sangireddy |
Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 4012-4015, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Mallik Kandala, Wei Zhang 0002, Laurence Tianruo Yang |
An Area-Efficient Approach to Improving Register File Reliability against Transient Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA Workshops (1) ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), Workshops Proceedings, Volume 1, May 21-23, 2007, Niagara Falls, Canada, pp. 798-803, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Kaushal R. Gandhi, Nihar R. Mahapatra |
Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1001-1006, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Sanjay Misra |
Modified Cognitive Complexity Measure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCIS ![In: Computer and Information Sciences - ISCIS 2006, 21th International Symposium, Istanbul, Turkey, November 1-3, 2006, Proceedings, pp. 1050-1059, 2006, Springer, 3-540-47242-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cognitive weights, basic control structures, cognitive complexity measure, Software metrics |
28 | Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra |
Exploiting forwarding to improve data bandwidth of instruction-set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 43-48, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction-set extensions, data forwarding |
28 | Sorin Dan Cotofana, Casper Lageweg, Stamatis Vassiliadis |
Addition Related Arithmetic Operations via Controlled Transport of Charge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 243-256, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
single electron technology, electron counting, multiplication, SET, addition |
28 | Robert D. Kenney, Michael J. Schulte |
High-Speed Multioperand Decimal Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(8), pp. 953-963, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic |
28 | Hongkyu Kim, D. Scott Wills, Linda M. Wills |
Empirical Analysis of Operand Usage and Transport in Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 168-171, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Madhubanti Mukherjee, Ranga Vemuri |
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 436-440, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner |
Combined Multiplication and Sum-of-Squares Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 204-214, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Milan Ojstersek, Viljem Zumer, Ljubo Pipan |
Efficient execution of parallel programs using partial strict triggering of program graph nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 11-13 December 1997, Seoul, Korea, Proceedings, pp. 453-459, 1997, IEEE Computer Society, 0-8186-8227-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
partial strict triggering, program graph nodes, coarse grained program graph nodes, VL, DSH scheduling algorithms, parallel programming, parallel programs, CPM |
28 | Sorin Cotofana, Stamatis Vassiliadis |
delta-Bit serial binary addition with linear threshold networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 14(3), pp. 249-264, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Tudor Jebelean |
Design of a systolic coprocessor for rational addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 282-289, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD |
28 | S. E. Richardson |
Exploiting trivial and redundant computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 220-227, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Ben Heggy, Mary Lou Soffa |
Architectural support for register allocation in the presence of aliasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 730-739, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
28 | J. Philip Benkard |
Replicate each, anyone? ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the international conference on APL: APL in transition, APL 1987, Dallas, TX, USA, May 10-14, 1987., pp. 245-252, 1987, ACM, 0-89791-226-8. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
APL |
28 | Edward L. Robertson |
Code Generation and Storage Allocation for Machines with Span-Dependent Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 1(1), pp. 71-83, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
|
28 | Brian Randell, L. J. Russell |
Single-Scan Techniques for the Translation of Arithmetic Expressions into ALGOL 60. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 11(2), pp. 159-167, 1964. The full citation details ...](Pics/full.jpeg) |
1964 |
DBLP DOI BibTeX RDF |
ALGOL |
26 | Toshinori Sato, Itsujiro Arita |
Table size reduction for data value predictors by exploiting narrow width values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000, pp. 196-205, 2000, ACM, 1-58113-270-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
narrow width operands, instruction level parallelism, hardware implementation, value prediction, data speculation |
26 | Jean-Michel Muller |
Some Characterizations of Functions Computable in On-Line Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(6), pp. 752-755, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
piecewise affine functions, operands, arbitrarily long length, computability, digital arithmetic, finite automata, multiplication, division, elementary functions, finite automaton, online computing, rational numbers |
26 | Peter Kornerup, David W. Matula |
An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(8), pp. 1106-1115, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
tree pipeline, Gosper, redundant binary bit-pipelined rational arithmetic, redundant binary representation, rational operands, partial quotient arithmetic algorithm, online arithmetic unit, signed bit level, binary radix, binary rational representation, online delays, simulation, parallel computation, redundancy, interconnection, product, digital arithmetic, number theory, difference, quotient, sum |
26 | Sally G. Smith |
Comments on "A Signed Bit-Sequential Multiplier". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(9), pp. 1328-1330, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
signed bit-sequential multiplier, unsigned operands, digital arithmetic |
26 | James W. Watterson, Jill J. Hallenbeck |
Modulo 3 Residue Checker: New Results on Performance and Cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(5), pp. 608-612, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
modulo-3 residue code checker, pipelined serial multiplier, concurrent self-test, minimum error latency, multiplier input operands, 4- mu m NMOS, standard cell design, performance evaluation, integrated circuit testing, error detection, automatic testing, digital arithmetic, pipeline processing, multiplying circuits, built in test, field effect integrated circuits, error detection coverage |
23 | Xin Qiao, Qingyu Guo, Xiyuan Tang, Jiahao Song, Renjie Wei, Meng Li 0004, Runsheng Wang, Yuan Wang 0001 |
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(4), pp. 1706-1718, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
23 | Constantinos Efstathiou, Ioannis Kouretas, Paris Kitsos |
On the modulo 2n+1 addition and subtraction for weighted operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 101, pp. 104897, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Peter Fritz |
Operands and Instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Rev. Symb. Log. ![In: Rev. Symb. Log. 16(1), pp. 188-209, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Simon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis |
Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, CA, USA, April 5-7, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-3475-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Vishesh Mishra, Urbi Chatterjee |
VMEO: Vector Modeling Errors and Operands for Approximate adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 1120, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
23 | Rui Liu, Xiaoyu Zhang 0009, Xiaoming Chen 0003, Yinhe Han 0001, Minghua Tang |
FeMIC: Multi-Operands in-Memory Computing Based on FeFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 678-683, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | David J. Schlais, Heng Zhuo, Mikko H. Lipasti |
Work-in-Progress: NoRF: A Case Against Register File Operands in Tightly-Coupled Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022, Shanghai, China, October 7-14, 2022, pp. 33-34, 2022, IEEE, 978-1-6654-7296-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang, Wei Zhang |
Reducing GPU Energy Consumption by Packing Narrow-Width Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Eng. ![In: J. Comput. Sci. Eng. 15(4), pp. 135-147, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Jiaqi Gu, Zheng Zhao 0003, Chenghao Feng, Zhoufeng Ying, Ray T. Chen, David Z. Pan |
O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 1062-1067, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Meng Li 0004, Yilei Li, Vikas Chandra |
Improving Efficiency in Neural Network Accelerator using Operands Hamming Distance Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021, pp. 599-604, 2021, ACM, 978-1-4503-7999-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Sanlin Chen, Gang Cai, Zhihong Huang |
An Enhanced DSP Block Architecture for FPGA Supporting Multi-operands Addition Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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23 | Zhiting Lin, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, Junning Chen |
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(5), pp. 1316-1320, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ram Rangan, Mark W. Stephenson, Aditya Ukarande, Shyam Murthy, Virat Agarwal, Marc Blackstein |
Zeroploit: Exploiting Zero Valued Operands in Interactive Gaming Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 17(3), pp. 17:1-17:26, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Meng Li 0004, Yilei Li, Pierce Chuang, Liangzhen Lai, Vikas Chandra |
Improving Efficiency in Neural Network Accelerator Using Operands Hamming Distance optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2002.05293, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
23 | Dibakar Gope, Jesse G. Beu, Matthew Mattina |
High Throughput Matrix-Matrix Multiplication between Asymmetric Bit-Width Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2008.00638, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
23 | Daniel Jancarczyk, Volodymyr Rudnytskyi, Roksolana Breus, Mykhailo Pustovit, Olga Veselska, Ruslana Ziubina |
Two-Operand Operations of Strict Stable Cryptographic Coding with Different Operands' Bits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDAACS-SWS ![In: 2020 IEEE 5th International Symposium on Smart and Wireless Systems within the Conferences on Intelligent Data Acquisition and Advanced Computing Systems (IDAACS-SWS), Dortmund, Germany, September 17-18, 2020, pp. 1-8, 2020, IEEE, 978-1-7281-9960-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang 0056, Wei Zhang 0002 |
Packing Narrow-Width Operands to Improve Energy Efficiency of General-Purpose GPU Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPEC ![In: 2020 IEEE High Performance Extreme Computing Conference, HPEC 2020, Waltham, MA, USA, September 22-24, 2020, pp. 1-7, 2020, IEEE, 978-1-7281-9219-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Poulami Das 0003, Debapriya Basu Roy, Debdeep Mukhopadhyay |
Automatic generation of HCCA-resistant scalar multiplication algorithm by proper sequencing of field multiplier operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Cryptogr. Eng. ![In: J. Cryptogr. Eng. 9(3), pp. 263-275, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Vasileios Leon, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi |
Energy-efficient VLSI implementation of multipliers with double LSB operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(6), pp. 816-821, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Li Jiang |
The identical operands commutative encryption and watermarking based on homomorphism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 77(23), pp. 30575-30594, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang 0056, Wei Zhang 0002 |
Packing Narrow-Width Operands to Improve GPU Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Eng. ![In: J. Comput. Sci. Eng. 12(2), pp. 37-49, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Serhii Mashchenko |
Intersections and unions of fuzzy sets of operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fuzzy Sets Syst. ![In: Fuzzy Sets Syst. 352, pp. 12-25, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Eduardo Chielle, Oleg Mazonka, Nektarios Georgios Tsoutsos, Michail Maniatakos |
E3: A Framework for Compiling C++ Programs with Encrypted Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2018, pp. 1013, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
23 | Chibuike Ugwuoke, Zekeriya Erkin, Reginald L. Lagendijk |
Secure Fixed-point Division for Homomorphically Encrypted Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the 13th International Conference on Availability, Reliability and Security, ARES 2018, Hamburg, Germany, August 27-30, 2018, pp. 33:1-33:10, 2018, ACM, 978-1-4503-6448-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Krishna Bhowal, Debasree Sarkar, Susanta Biswas, Partha Pratim Sarkar |
A steganographic approach to hide secret data in digital audio based on XOR operands triplet property with high embedding rate and good quality audio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 25, pp. 2136-2148, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Xin Wang 0056, Wei Zhang 0002 |
GPU Register Packing: Dynamically Exploiting Narrow-Width Operands to Improve Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TrustCom/BigDataSE/ICESS ![In: 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, pp. 745-752, 2017, IEEE Computer Society, 978-1-5090-4906-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Poulami Das 0003, Debapriya Basu Roy, Debdeep Mukhopadhyay |
Automatic Generation of HCCA Resistant Scalar Multiplication Algorithm by Proper Sequencing of Field Multiplier Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PROOFS ![In: PROOFS 2017, 6th International Workshop on Security Proofs for Embedded Systems, Taipei, Taiwan, September 29th, 2017, pp. 33-49, 2017, EasyChair. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Wafaa S. Sayed, Hossam A. H. Fahmy |
What are the Correct Results for the Special Values of the Operands of the Power Operation? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Math. Softw. ![In: ACM Trans. Math. Softw. 42(2), pp. 14:1-14:17, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Darjn Esposito, Davide De Caro, Antonio Giuseppe Maria Strollo |
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8), pp. 1200-1209, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Mehran Mozaffari Kermani, Rajkumar Ramadoss, Reza Azarderakhsh |
Efficient error detection architectures for CORDIC through recomputing with encoded operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 2154-2157, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Kiamal Z. Pekmestzi, Kostas Tsoumanis, Constantinos Efstathiou |
Fused modulo 2n + 1 add-multiply unit for weighted operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016, Istanbul, Turkey, April 12-14, 2016, pp. 1-6, 2016, IEEE, 978-1-5090-0336-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Poulami Das 0003, Debapriya Basu Roy, Debdeep Mukhopadhyay |
Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2015, pp. 925, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
23 | Takeshi Sugawara 0001, Daisuke Suzuki, Minoru Saeki |
Two Operands of Multipliers in Side-Channel Attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2015, pp. 291, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
23 | Takeshi Sugawara 0001, Daisuke Suzuki, Minoru Saeki |
Two Operands of Multipliers in Side-Channel Attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COSADE ![In: Constructive Side-Channel Analysis and Secure Design - 6th International Workshop, COSADE 2015, Berlin, Germany, April 13-14, 2015. Revised Selected Papers, pp. 64-78, 2015, Springer, 978-3-319-21475-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Xiaoxiao Zhang, Farid Boussaïd, Amine Bermak |
32 Bit ×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(4), pp. 759-770, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Xiaofei Guo, Debdeep Mukhopadhyay, Chenglu Jin, Ramesh Karri |
NREPO: Normal Basis Recomputing with Permuted Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2014, pp. 497, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
23 | Kostas Tsoumanis, Constantinos Efstathiou, Kiamal Z. Pekmestzi |
Modulo 2n+1 addition and multiplication for redundant operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 9th International Design and Test Symposium, IDT 2014, Algeries, Algeria, December 16-18, 2014, pp. 205-210, 2014, IEEE, 978-1-4799-8200-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Mohamed Karroumi, Benjamin Richard, Marc Joye |
Addition with Blinded Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COSADE ![In: Constructive Side-Channel Analysis and Secure Design - 5th International Workshop, COSADE 2014, Paris, France, April 13-15, 2014. Revised Selected Papers, pp. 41-55, 2014, Springer, 978-3-319-10174-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Xiaofei Guo, Debdeep Mukhopadhyay, Chenglu Jin, Ramesh Karri |
NREPO: Normal basis Recomputing with Permuted Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014, Arlington, VA, USA, May 6-7, 2014, pp. 118-123, 2014, IEEE Computer Society, 978-1-4799-4114-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Xiaofei Guo, Ramesh Karri |
Recomputing with Permuted Operands: A Concurrent Error Detection Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10), pp. 1595-1608, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Xiaofei Guo, Ramesh Karri |
Recomputing with Permuted Operands: A Concurrent Error Detection Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2013, pp. 613, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
23 | Jongwon Lee, Jonghee M. Youn, Jihoon Lee, Minwook Ahn, Yunheung Paek |
Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 26th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2012, Shanghai, China, May 21-25, 2012, pp. 119-130, 2012, IEEE Computer Society, 978-1-4673-0975-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Hirotaka Kawashima, Naofumi Takagi |
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 4, pp. 131-139, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | José-Luis Sánchez-Romero, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno-Morenilla |
Function approximation on decimal operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Digit. Signal Process. ![In: Digit. Signal Process. 21(2), pp. 354-366, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Shlomi Dolev, Sergey Frenkel, Dan E. Tamir |
Computer Arithmetic Preserving Hamming Distance of Operands in Operation Result ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1104.3310, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
23 | Bijan Alizadeh, Masahiro Fujita |
Modular equivalence verification of polynomial datapaths with multiple word-length operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011, pp. 9-16, 2011, IEEE Computer Society, 978-1-4577-1744-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Kenshu Seto, Masahiro Fujita |
Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 3, pp. 57-68, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Ilknur Cansu Kaynak, Yusuf Onur Koçberber, Oguz Ergin |
Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 19(8), pp. 1689-1709, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Costas Efstathiou |
Efficient modulo 2N+1 subtractors for weighted operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pp. 1-4, 2010, IEEE, 978-1-4244-8155-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik |
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 252-257, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multiply-accumulate, Fused and continuous MAC, VLSI, Floating-point |
23 | Liang-Kai Wang, Michael J. Schulte |
A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009, pp. 125-134, 2009, IEEE Computer Society, 978-0-7695-3670-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Miklós Erdélyi-Szabó, László Kálmán, Agi Kurucz |
Towards a natural language semantics without functors and operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Log. Lang. Inf. ![In: J. Log. Lang. Inf. 17(1), pp. 1-17, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Finite axiomatisability, Finite entailment problem, Function/argument metaphor, Pieces of evidence, Measurements, Completeness, Compositionality, Decision algorithm, Natural language semantics |
23 | Eduardo A. C. da Costa, José Monteiro 0001, Sergio Bampi |
A new array architecture for signed multiplication using Gray encoded radix-2m operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 40(2), pp. 118-132, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Ajay Kumar Verma, Paolo Ienne |
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 601-608, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers |
23 | Naveed Ali, Shoab A. Khan, Naveed Sarfraz Khattak |
Equivalence Verification of Arithmetic Data Paths With Multiple Word-Length Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCS ![In: Proceedings of the 2007 International Conference on Foundations of Computer Science, FCS 2007, June 25-28, 2007, Las Vegas, Nevada, USA, pp. 171-176, 2007, CSREA Press, 1-60132-049-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|