Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
109 | Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije |
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 94-99, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
TSPC, high speed digital circuit, low power, prescaler |
90 | Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije |
A 4.1 GHz prescaler using double data throughput E-TSPC structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 123-127, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
TSPC, high speed digital circuit, prescaler |
81 | Quan Yuan, Haigang Yang, Fang-yuan Dong, Tao Yin |
"Time borrowing" technique for design of low-power high-speed multi-modulus prescaler in frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1004-1007, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
81 | Hans-Dieter Wohlmuth, Daniel Kehrer |
A 24 GHz dual-modulus prescaler in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3227-3230, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
81 | Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo |
A new 5 GHz CMOS dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5027-5030, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
81 | Hong Jo Ahn, Mohammed Ismail 0001 |
GHz programmable dual-modulus prescaler for multi-standard wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 137-140, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
66 | Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije |
A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 144-148, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high speed digital circuit, low power, prescaler, frequency synthesizer |
62 | Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije |
A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1895-1898, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
62 | Stephen Machan |
A Low-Power Fully Differential 2.4-GHz Prescaler in 0.18µm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 98-100, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
62 | Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez |
A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 791-794, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo |
A New Phase Noise Model for TSPC based divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 348-351, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | No Yong Kwon, Bora Kim, Yong Moon |
A study of META-voltage controlled oscillator and prescaler using 65nm CMOS process: META-VCO and prescaler using 65nm CMOS precess. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016, pp. 27-28, 2016, IEEE, 978-1-5090-3219-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
43 | Keliu Shu, Edgar Sánchez-Sinencio |
A 5-GHz prescaler using improved phase switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 85-88, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Herbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost |
A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 20-23, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Ko-Chi Kuo, Feng-Ji Wu |
A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 214-217, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | João Navarro Jr., Wilhelmus A. M. Van Noije |
Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(3), pp. 301-308, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Suchitav Khadanga |
Synchronous programmable divider design for PLL Using 0.18 um cmos technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 281-286, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
programmable divider, CMOS integrated circuits, phase locked loop, PLL, Prescaler, frequency synthesizers |
28 | Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac |
Long and Fast Up/Down Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(7), pp. 722-735, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Binary counter, constant time counter, serial counter, up/down counter, prescaler, parallel counter |
24 | Ravi Kumar, Pooja Bohara, Krishna Thakur, Santosh Kumar Vishvakarma |
A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(4), pp. 2350068:1-2350068:16, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Devavarshini Arulnambi, Khutiza Afrose Syed, Yue-Fang Kuo, Po-Hsien Wu |
An Efficient Architecture Design of High-Speed Dual-Modulus Prescaler for Frequency Synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-Taiwan ![In: International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023, PingTung, Taiwan, July 17-19, 2023, pp. 633-634, 2023, IEEE, 979-8-3503-2417-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Yu Liu, Alexander C. Frank, Tilman Esslinger, Tobias Donner, Abdulkadir Akin |
Laser Frequency Stabilization Using a Prescaler and a High-Resolution Frequency to Voltage Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QCE ![In: IEEE International Conference on Quantum Computing and Engineering, QCE 2023, Bellevue, WA, USA, September 17-22, 2023, pp. 367-368, 2023, IEEE, 979-8-3503-4323-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Vasileios Chioktour, Athanasios Kakarountas |
Constant delay systolic binary counter with variable size cellular automaton based prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 93, pp. 107291, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Uma Nirmal, V. K. Jain |
Divide-by-16/17 dual modulus prescaler design with enhanced speed in a 180nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Aided Eng. Technol. ![In: Int. J. Comput. Aided Eng. Technol. 14(3), pp. 345-357, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Seokwon Kang, Kyunghwan Choi, Yongjun Park 0001 |
PreScaler: an efficient system-aware precision scaling framework on heterogeneous systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, San Diego, CA, USA, February, 2020, pp. 280-292, 2020, ACM, 978-1-4503-7047-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Lukas Polzin, Marcel van Delden, Nils Pohl, Klaus Aufinger, Thomas Musch |
A 117 GHz Dual-Modulus Prescaler With Inductive Peaking for a Programmable Frequency Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BCICTS ![In: IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2020, Monterey, CA, USA, November 16-19, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9749-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Gautam R. Gangasani, Peter R. Kinget |
A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 66-II(5), pp. 803-807, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Suraj Kumar Saw, Madhusudan Maiti, Preetisudha Meher |
Design and Analysis of Dual Modulus Prescaler Circuit for Frequency Synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2019 (Formerly iNiS), Rourkela, India, December 16-18, 2019, pp. 185-188, 2019, IEEE, 978-1-7281-4655-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Wenjian Jiang, Fengqi Yu, Qinjin Huang |
A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(1), pp. 20160446, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Xincun Ji, Xiaojuan Xia, Zixuan Wang, Leisheng Jin |
A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(8), pp. 20170065, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Vasileios Chioktour, Georgios P. Spathoulas, Athanasios Kakarountas |
Systolic Binary Counter using a Cellular Automaton-based Prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PCI ![In: Proceedings of the 21st Pan-Hellenic Conference on Informatics, Larissa, Greece, September 28-30, 2017, pp. 15:1-15:4, 2017, ACM, 978-1-4503-5355-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Song Jia, Ziyi Wang, Shilin Yan, Yuan Wang 0001 |
A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 44(10), pp. 1895-1900, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Song Jia, Ziyi Wang, Zijin Li, Yuan Wang 0001 |
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 2751-2754, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Wen-rui Zhu, Haigang Yang, Tongqiang Gao, Fei Liu 0011, Tao Yin, Dandan Zhang, Hongfeng Zhang |
A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(1), pp. 194-197, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Meilin Wan, Zhenzhen Zhang, Wang Liao, Kui Dai, Xuecheng Zou |
A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(7), pp. 1550109:1-1550109:23, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Song Jia, Shilin Yan, Yuan Wang 0001, Ganggang Zhang |
A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 890-893, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Cristina Azcona, Belén Calvo, Nicolás Medrano, Santiago Celma, Cecilia Gimeno |
A wide-range dual-modulus prescaler using a novel SCL biasing technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 2225-2228, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Takeshi Mitsunaka, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima |
8-GHz Locking Range and 0.4-pJ Low-Energy Differential Dual-Modulus 10/11 Prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 97-C(6), pp. 486-494, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu |
A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(2), pp. 250-258, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Jianhui Wu 0001, Zixuan Wang, Xincun Ji, Cheng Huang 0005 |
A low-power high-speed true single phase clock divide-by-2/3 prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 10(2), pp. 20120913, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Zheng Sun, Yong Xu, Chen Hu, Guangyan Ma, Yuanliang Wu, Ying Huang |
Design of novel high speed dual-modulus prescaler based on new optimized structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-6415-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Hyunchol Shin |
A 1-V TSPC Dual Modulus Prescaler with Speed Scalability Using Forward Body Biasing in 0.18 µm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 95-C(6), pp. 1121-1124, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Hideyuki Nakamizo, Kenichi Tajima, Ryoji Hayashi, Kenji Kawakami, Toshiya Uozumi |
Parallel Dual Modulus Prescaler with a Step Size of 0.5. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 95-C(7), pp. 1189-1194, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Elkim Roa, Byunghoo Jung |
A 50GHz 130µW inductorless prescaler in 45nm SOI CMOS using ETSPC logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 1071-1074, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Keping Wang, Kaixue Ma, Kiat Seng Yeo |
Low-power high-speed dual-modulus prescaler for Gb/s applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, December 2-5, 2012, pp. 256-259, 2012, IEEE, 978-1-4577-1728-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Xincun Ji, Fuqing Huang, Jianhui Wu 0001, Longxing Shi |
An 11.2-mW 5-GHz CMOS Frequency Synthesizer with Low Power Prescaler for Zigbee Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 94-C(3), pp. 375-378, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Yunfeng Yu, Tianchun Ye 0001, Chengyan Ma |
Optimization and design of a novel prescaler and its application to GPS receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 54(9), pp. 1938-1944, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Qun Jane Gu, Heng-Yu Jian, Zhiwei Xu 0003, Yi-Cheng Wu, Mau-Chung Frank Chang, Yves Baeyens, Young-Kai Chen |
CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 58-II(7), pp. 393-397, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Huimin Liu, Xiaoxing Zhang, Yujie Dai, Yingjie Lv |
Low Power CMOS High Speed Dual-Modulus 15/16 Prescaler for Wireless Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CMC ![In: Third International Conference on Communications and Mobile Computing, CMC 2011, Qingdao, China, 18-20 April 2011, pp. 397-400, 2011, IEEE Computer Society, 978-0-7695-4357-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim |
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1), pp. 72-82, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Seungsoo Kim, Jaewook Shin, Hyunchol Shin |
On-the-fly speed and power scaling of an E-TSPC dual modulus prescaler using forward body bias in 0.25 μm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 1775-1778, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto |
A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 92-C(6), pp. 785-791, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Lei Lu, Zhichao Gong, Youchun Liao, Hao Min, Zhangwen Tang |
A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, pp. 396-397, 2009, IEEE, 978-1-4244-3458-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Yanping Ding, Kenneth K. O |
A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 42(6), pp. 1240-1249, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto |
A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007, pp. 472-475, 2007, IEEE, 978-1-4244-1125-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Yi-Shing Shih, Jenn-Hwan Tarng |
A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 3(12), pp. 276-280, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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24 | Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo |
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 902-905, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Chihun Lee, Lan-chou Cho, Shen-Iuan Liu |
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006, pp. 397-400, 2006, IEEE, 1-4244-0075-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Ram Singh Rana |
Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-μm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(8), pp. 1662-1670, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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24 | Olivier Mazouffre, Hervé Lapuyade, Jean-Baptiste Bégueret, Andreia Cathelin, Didier Belot, Yann Deval |
A 1 V 270 My-W 2 GHz CMOS Synchronized Ring Oscillator Based Prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 1(2), pp. 153-160, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Rasoul Dehghani |
A very low power 3ghz 128/129 CMOS dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 12th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2005, Gammarth, Tunisia, December 11-14, 2005, pp. 1-4, 2005, IEEE, 978-9972-61-100-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Mihai A. T. Sanduleanu, Razvan Ionita, Andrei Vladimirescu |
A 34GHz/1V prescaler in 90nm CMOS SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005, pp. 109-112, 2005, IEEE, 0-7803-9205-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Huayi Zhang, Ezz I. El-Masry |
A novel CMOS power efficient and glitch free d-flip-flop for dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits, Signals, and Systems ![In: Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005, pp. 1-4, 2005, IASTED/ACTA Press, 0-88986-509-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
24 | Chin-Sheng Chen, Robert C. Chang |
A new prescaler for fully integrated 5-GHz CMOS frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 245-248, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
24 | Ahmed Wafa, Ayman Ahmed |
High-speed RF multi-modulus prescaler architecture for ΣΔ fractional-N PLL frequency synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 241-244, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
24 | Mark P. Houlgate, Daniel J. Olszewski, Karim Abdelhalim, Leonard MacEachern |
Adaptable MOS current mode logic for use in a multi-band RF prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 329-332, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
24 | Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez, Sherif H. K. Embabi |
A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(6), pp. 866-874, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Wei-Zen Chen, Chien-Liang Kuo, Chia-Chun Liu |
10 GHz quadrature-phase voltage controlled oscillator and prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, pp. 361-364, 2003, IEEE, 0-7803-7995-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Hans-Dieter Wohlmuth, Daniel Kehrer |
A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, pp. 77-80, 2003, IEEE, 0-7803-7995-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Ki-Hyuk Sung, Lee-Sup Kim |
Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 35(6), pp. 919-920, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Ayman I. Ahmed, Khalid Sharaf, Hisham S. Haddara, Hani F. Ragai |
CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 737-740, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Marc Tiebout |
A 480 μW 2 GHz ultra low power dual-modulus prescaler in 0.25 μm standard CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 741-744, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Hongyan Yan, Manish Biyani, Kenneth K. O |
A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2) latch and its application in a dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(10), pp. 1400-1404, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Joao Navarro Soares, Wilhelmus A. M. Van Noije |
A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(1), pp. 97-102, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | W.-H. Chang, D. R. Pehlke, R. Yu |
A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999, pp. 597-600, 1999, IEEE, 0-7803-5443-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Abdelaziz Benachour, Sherif H. K. Embabi, Akbar Ali |
A 1.5 GHz, sub-2 mW CMOS dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999, pp. 613-616, 1999, IEEE, 0-7803-5443-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Dirk Pfaff, Qiuting Huang |
A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999, pp. 649-652, 1999, IEEE, 0-7803-5443-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu |
New dynamic flip-flops for high-speed dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 33(10), pp. 1568-1571, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Rami Ahola, Kari Halonen |
A 4 GHz CMOS multiple modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998, pp. 323-326, 1998, IEEE, 0-7803-5008-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Byungsoo Chang, Joonbae Park, Wonchan Kim |
A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(5), pp. 749-752, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
24 | Jan Craninckx, Michiel S. J. Steyaert |
A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(7), pp. 890-897, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
24 | Patrik Larsson |
High-speed architecture for a programmable frequency divider and a dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(5), pp. 744-748, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
24 | Jan Craninckx, Michel S. J. Steyaert |
A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(12), pp. 1474-1482, December 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
24 | Tim Seneff, Lynelle McKay, Kurt Sakamoto, Neil Tracht |
A sub-1 mA 1.5-GHz silicon bipolar dual modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 29(10), pp. 1206-1211, October 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | JinKyung Kim, Sung-Kyu Jung, Ji-Hoon Jung, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam, Bong Hyuk Park, Sang-Sung Choi |
A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 441-445, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
single-sideband (SSB) mixer, UWB, phase-locked loop (PLL), Frequency Synthesizer |
19 | Himanshu Arora, Nikolaus Klemmer, Patrick D. Wolf |
A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 381-386, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RMS phase error, delta-sigma, fractional-N, gain mismatch, phase frequency detector, spurs, thermal noise, VCO, phase noise, frequency synthesizer, charge pump |
19 | Taoufik Bourdi, Assaad Borjak, Izzet Kale |
A modeling platform for efficient characterization of phase-locked loop Delta Sigma frequency synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun |
Design of A 2.4-GHz integrated frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 21-22, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Shuenn-Yuh Lee, Chung-Han Cheng, Ming-Feng Huang, Shyh-Chyang Lee |
A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2811-2814, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Young-Mi Lee, Ju-Sang Lee, Sang Jin Lee, Ri-A Ju |
Design of a frequency synthesizer for WCDMA in 0.18µm CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 757-760, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Won Hyo Lee, Jun Dong Cho, Sung Dae Lee |
A High Speed and Low Power Phase-Frequency Detector and Charge - pump. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 269-272, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Amr N. Hafez, Mohamed I. Elmasry |
A low power monolithic subsampled phase-locked loop architecture for wireless transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 549-552, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Rami Ahola, Kari Stadius, Kari Halonen |
Design of a fully integrated 2 GHz CMOS frequency synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 160-163, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Juha Häkkinen, Timo Rahkonen, Juha Kostamovaara |
A frequency hopping synthesizer IC for IF and RF applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 202-205, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|