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Searching for phrase processor-in-memory (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1995-2002 (16) 2003-2005 (17) 2006-2015 (15) 2016-2023 (12)
Publication types (Num. hits)
article(14) inproceedings(45) phdthesis(1)
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The graphs summarize 65 occurrences of 47 keywords

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Found 60 publication records. Showing 60 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
36Slo-Li Chu An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture. Search on Bibsonomy EUC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF EOPRS, SAGE II, SoC, Power Reduction, Processor-in-Memory
36Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. Search on Bibsonomy HPCA The full citation details ... 2000 DBLP  DOI  BibTeX  RDF directory controller, multiprocessor, reconfigurable, PIM, DSM, coherence protocol, NUMA, processor-in-memory, COMA
35Slo-Li Chu POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture. Search on Bibsonomy ICPADS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF POERS, SAGE II, MPSoC, Processor-in-Memory, Energy Reduction
32Krishna Kumar Rangan, Philip A. Wilsey, Nilesh Pisolkar, Nael B. Abu-Ghazaleh PPIM-SIM: An Efficient Simulator for a Parallel Processor in Memory. Search on Bibsonomy Annual Simulation Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Slo-Li Chu PSS: A Novel Statement Scheduling Mechanism for a High-Performance SoC Architecture. Search on Bibsonomy ICPADS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Pair-Selection Scheduling, Statement Analysis, SoC, Processor-in-Memory, SAGE
31Marco Lanuzza, Martin Margala, Pasquale Corsonello Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF reconfigurable computing, datapath, processor-in-memory
30Slo-Li Chu Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture. Search on Bibsonomy LCPC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
27Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Search on Bibsonomy Intelligent Memory Systems The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
26Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh Dynamic Co-operative Intelligent Memory. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
26Thomas L. Sterling Towards Memory Oriented Scalable Computer Architecture and High Efficiency Petaflops Computing. Search on Bibsonomy NPC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinzler PIM lite: a multithreaded processor-in-memory prototype. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multithreading, VLSI design, processing-in-memory
25Jung-Yup Kang, Sandeep Gupta 0001, Jean-Luc Gaudiot Accelerating the Kernels of BLAST with an Efficient PIM (Processor-In-Memory) Architecture. Search on Bibsonomy CSB The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Processor-In-Memory (PIM) Architecture, Sequence Alignment, BLAST
25Thomas L. Sterling, Hans P. Zima Gilgamesh: a multithreaded processor-in-memory architecture for petaflops computing. Search on Bibsonomy SC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Petaflops computing, data parallel processing, parallel architectures, Processor-In-Memory, irregular applications
24Slo-Li Chu Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture. Search on Bibsonomy EUC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
22Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihin Helper thread prefetching for loosely-coupled multiprocessor systems. Search on Bibsonomy IPDPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
21Nagarajan Venkateswaran, Aditya Krishnan 0002, S. Niranjan Kumar, Arrvindh Shriraman, Srinivas Sridharan Memory in processor: a novel design paradigm for supercomputing architectures. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
20Brandon J. Jasionowski, Michelle K. Lay, Martin Margala A Processor-In-Memory Architecture for Multimedia Compression. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
20Hans P. Zima, Thomas L. Sterling Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays. Search on Bibsonomy ISHPC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
20Jaejin Lee, Changhee Jung, Daeseob Lim, Yan Solihin Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
19Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter Combined DRAM and logic chip for massively parallel systems. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
18Jih-Ching Chiu, Yu-Liang Chou, Hua-Yi Tzeng A multi-streaming SIMD architecture for multimedia applications. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF SIMD, streaming processing, streaming computing, processor-in-memory, mmx, multimedia extensions, pim
17Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie Computational RAM: Implementing Processors in Memory. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
16Jae Chul Cha, Sandeep K. Gupta 0001 Matrix Inversion on a PIM (Processor-in-Memory). Search on Bibsonomy CSSE (3) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
16Slo-Li Chu, Wen-Chih Ho, Chien-Fang Chen, Kai-Wei Ceng, Ming-Han Liu Design a Novel Memory Network for Processor-in-Memory Architectures. Search on Bibsonomy SKG The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
16Danijela Efnusheva, Aristotel Tentov Design of Processor in Memory with RISC-modified Memory-Centric Architecture. Search on Bibsonomy CSOC (2) The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
16Christopher J. Hughes, Sarita V. Adve Memory-side prefetching for linked data structures for processor-in-memory systems. Search on Bibsonomy J. Parallel Distributed Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
16Yan Solihin, Jaejin Lee, Josep Torrellas Adaptively Mapping Code in an Intelligent Memory Architecture. Search on Bibsonomy Intelligent Memory Systems The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
16Dennis W. Prather Three Dimensional VLSI-Scale Interconnects. Search on Bibsonomy IPDPS Workshops The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
15Ed T. Upchurch, Thomas L. Sterling, Jay B. Brockman Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs. Search on Bibsonomy SC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
13Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou Design of a novel SIMD architecture by fusing operations and registers. Search on Bibsonomy ICS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF processor-in-memory, mmx, simd, multimedia extensions, pim
13Sourav Chatterji, Manikandan Narayanan, Jason Duell, Leonid Oliker Performance Evaluation of Two Emerging Media Processors: VIRAM and Imagine. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multimedia applications, stream processing, QR decomposition, processor-in-memory, vector architecture
13Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leonid Oliker, Katherine A. Yelick, Rupak Biswas Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines. Search on Bibsonomy IPDPS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF memory intensive benchmarks, data parallelism, vector processor, Processor-in-Memory, embedded DRAM
13G. Jack Lipovski, Clement T. Yu The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval. Search on Bibsonomy MTDT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
12M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001 FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
12M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews 0001 FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ? Search on Bibsonomy FPL The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
12Sung-June Byun, Dong-Gyun Kim, Kyung-Do Park, Yeun-Jin Choi, Pervesh Kumar, Imran Ali, Dong-Gyu Kim, June-Mo Yoo, Hyung-Ki Huh, Yeon-Jae Jung, Seok-Kee Kim, YoungGun Pu, Kang-Yoon Lee A Low-Power Analog Processor-in-Memory-Based Convolutional Neural Network for Biosensor Applications. Search on Bibsonomy Sensors The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
12Kyung Do Park, Dong Gyun Kim, YoungGun Pu, Kang-Yoon Lee 10.76 TOPS/W CNN Algorithm Circuit using Processor-In-Memory with 8T-SRAM. Search on Bibsonomy BigComp The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
12Purab Ranjan Sutradhar, Mark Connolly, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao, Mark A. Indovina, Amlan Ganguly pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning. Search on Bibsonomy IEEE Comput. Archit. Lett. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
12Dominique Lavenier, Remy Cimadomo, Romaric Jodin Variant Calling Parallelization on Processor-in-Memory Architecture. Search on Bibsonomy BIBM The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
12Richard Muri, Paul J. Fortier Embedded Processor-In-Memory Architecture for Accelerating Arithmetic Operations. Search on Bibsonomy HPEC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
12Duckhwan Kim 0001 Neurocube: Energy-Efficient Programmable Digital Deep Learning Accelerator based on Processor in Memory Platform. Search on Bibsonomy 2019   RDF
12Dominique Lavenier, Jean-François Roy, David Furodet DNA mapping using Processor-in-Memory architecture. Search on Bibsonomy BIBM The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
12Joshua Schabel, Lee Baker, Sumon Dey, Weifu Li, Paul D. Franzon Processor-in-memory support for artificial neural networks. Search on Bibsonomy ICRC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
12Erik P. DeBenedictis, Jeanine E. Cook, Mark Hoemmen, Tzevetan S. Metodi Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS). Search on Bibsonomy NANOARCH The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
12Jed Kao-Tung Chang, Chen Liu 0001, Jean-Luc Gaudiot Enhancement for Potential Target in Cryptography Algorithms by Applying Processor-in-Memory Architecture. Search on Bibsonomy IPDPS Workshops The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
12Mohammed Sayed, Wael M. Badawy, Graham A. Jullien Video-Active RAM: A processor-in-memory architecture for video coding applications. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
12Jung-Yup Kang, Sandeep K. Gupta 0001, Jean-Luc Gaudiot An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Real-time and embedded systems, Special-Purpose and Application-Based Systems
12A. I. Eldosuky, H. A. Ali, M. A. Abbas An Energy-Efficient FlexRAM Processor-In-Memory chip. Search on Bibsonomy Egypt. Comput. Sci. J. The full citation details ... 2006 DBLP  BibTeX  RDF
12Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee Improving workload balance and code optimization on processor-in-memory systems. Search on Bibsonomy J. Syst. Softw. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
12Slo-Li Chu, Tsung-Chuan Huang SAGE: an automatic analyzing system for a new high-performance SoC architecture--processor-in-memory. Search on Bibsonomy J. Syst. Archit. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
12Tsung-Chuan Huang, Slo-Li Chu A statement based parallelizing framework for processor-in-memory architectures. Search on Bibsonomy Inf. Process. Lett. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
12Jung-Yup Kang, Sandeep Gupta 0001, Saurabh Shah, Jean-Luc Gaudiot An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation. Search on Bibsonomy ASAP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
12Thomas L. Sterling The Gilgamesh MIND Processor-in-Memory Architecture for Petaflops-Scale Computing. Search on Bibsonomy ISHPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
12Slo-Li Chu, Tsung-Chuan Huang, Lan-Chi Lee Improving Workload Balance and Code Optimization in Processor-in-Memory Systems. Search on Bibsonomy ICPADS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
12Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, Peter M. Kogge Optimizing Data Scheduling on Processor-in-Memory Arrays. Search on Bibsonomy IPPS/SPDP The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
11Arun Rodrigues, Richard C. Murphy, Peter M. Kogge, Keith D. Underwood Poster reception - The structural simulation toolkit: exploring novel architectures. Search on Bibsonomy SC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
11John C. Koob, Daniel A. Leder, Raymond J. Sung, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn, Lisa G. McIlrath Design of a 3-D fully depleted SOI computational RAM. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
4Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels. Search on Bibsonomy ISCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
4Jinwoo Suh, Dong-In Kang, Stephen P. Crago Dynamic Power Management of Multiprocessor Systems. Search on Bibsonomy IPDPS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
4Hans P. Zima, Thomas L. Sterling Support for Irregular Computations in Massively Parallel PIM Arrays, Using an Object-Based Execution Model. Search on Bibsonomy IPDPS Workshops The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
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