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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 296 publication records. Showing 296 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
91 | Tomás Lang, Alberto Nannarelli |
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(6), pp. 727-739, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
decimal division, algorithms and architectures for floating-point arithmetic, Decimal arithmetic, digit-recurrence division |
72 | Shuenn-Yuh Lee, Chia-Chyang Chen |
VLSI implementation of programmable FFT architectures for OFDM communication system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing, IWCMC 2006, Vancouver, British Columbia, Canada, July 3-6, 2006, pp. 893-898, 2006, ACM, 1-59593-306-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FFT processor, low power, VLSI architecture |
72 | Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy |
A split-radix algorithm for 2-D DFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 698-701, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
63 | Pere Martí-Puig, Ramón Reig Bolaño, Vicenç Parisi Baradad |
Radix-R FFT and IFFT Factorizations for Parallel Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCAI ![In: International Symposium on Distributed Computing and Artificial Intelligence, DCAI 2008, University of Salamanca, Spain, 22th-24th October 2008, pp. 152-160, 2008, Springer, 978-3-540-85862-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Parallel algorithms, Fast Fourier Transform, Fast algorithms |
63 | Jin-Hua Hong, Cheng-Wen Wu |
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 474-484, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
63 | Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy |
An efficient split-radix FFT algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 65-68, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
63 | Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera |
Radix-4 Vectoring CORDIC Algorithm and Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 19(2), pp. 127-147, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
61 | Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher |
Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 386-391, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division |
55 | J. Arjun Prabhu, Gregory B. Zyner |
167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 155-162, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
54 | Shuenn-Yuh Lee, Chia-Chyang Chen, Shyh-Chyang Lee, Chih-Jen Cheng |
A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
54 | David L. Harris, Stuart F. Oberman, Mark Horowitz |
SRT Division Architectures and Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 18-25, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
skew-tolerant, Computer arithmetic, floating point units, SRT division, domino circuits |
54 | Miriam Leeser, John W. O'Leary |
Verification of a subtractive radix-2 square root algorithm and implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 526-531, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
subtractive radix-2 square root, floating point square root hardware, Intel Pentium, radix-2 square root, MIPS R4400, RTL level, verification, formal verification, theorem proving, theorem proving, floating point arithmetic, optimizing transformations |
47 | Daisuke Takahashi, Yasumasa Kanada |
High-Performance Radix-2, 3 and 5 Parallel 1-D Complex FFT Algorithms for Distributed-Memory Parallel Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 15(2), pp. 207-228, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
3 and 5, cyclic distribution, fast Fourier transform, all-to-all communication, distributed-memory parallel computer, radix-2 |
47 | Hosahalli R. Srinivas, Keshab K. Parhi |
A floating point radix 2 shared division/square root chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 472-478, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
floating point radix 2 shared division/square root chip, full-custom 1.2 micron CMOS VLSI chip, single precision IEEE 754 std. floating point numbers, square root algorithm, digit-by-digit schemes, quotient/root digit selection, 5.0 V, 66 MHz, VLSI, floating point arithmetic, CMOS integrated circuits, IEEE standards, dividing circuits, 1.2 micron, division algorithm |
46 | Ioannis Kouretas, Vassilis Paliouras |
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 93-102, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy |
A General Class of Split-Radix FFT Algorithms for the Computation of the DFT of Length-2m. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 55(8), pp. 4127-4138, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Bryan Catanzaro, Brent E. Nelson |
Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 279, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata |
Cordic based parallel/pipelined architecture for the Hough transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 12(3), pp. 207-221, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
45 | Luis A. Montalvo, Alain Guyot |
Svoboda-Tung division with no compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 381-385, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Svoboda-Tung division, radix-b division algorithm, iteration overflow, most significant digits, radix-b algorithm, IEEE normalised divisor, pre-scaling technique, stepwise approximation, VLSI, iterative methods, digital arithmetic, VLSI implementation, prescalers, dividing circuits |
43 | T. C. Choinski, T. T. Tylaska |
Generation of Digit Reversed Address Sequences for Fast Fourier Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(6), pp. 780-784, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
digit reversed address sequences generation, radix-4, binary counter, address sequences, fast Fourier transforms, fast Fourier transforms, hardware design, computerised signal processing, radix-2 |
38 | Jae-Hee Won, Kiyoung Choi |
Low power self-timed Radix-2 division (poster session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 210-212, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSD, radix-2 division, low power, self-timed |
37 | Jean-Luc Beuchat, Jean-Michel Muller |
Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 303-308, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Satyendra R. Datla, Mitchell A. Thornton, David W. Matula |
A Low Power High Performance Radix-4 Approximate Squaring Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 91-97, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Shuenn-Shyang Wang, Chien-Sung Li |
An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(3), pp. 245-256, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
variable length FFT, substructure sharing, Fast Fourier Transform, OFDM |
36 | Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy |
Design of a multidimensional split vector-radix decimation-in-frequency FFT algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Peter-Michael Seidel, Lee D. McFearin, David W. Matula |
Secondary Radix Recodings for Higher Radix Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(2), pp. 111-123, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
recoding, high radix, digit set, mixed radix representation, partial product reduction, Booth recoding, Binary multiplication |
36 | Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy |
An efficient split-radix FHT algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 565-568, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Behrooz Parhami |
Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(11), pp. 1509-1514, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
digit-selector PLA, high-radix division, p-d plot, quotient digit selection, SRT division, Digit-recurrence division |
36 | Jaehyun Baek, Byung S. Son, Byung G. Jo, Myung Hoon Sunwoo, Seung Keun Oh |
A continuous flow mixed-radix FFT architecture with an in-place algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 133-136, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Alexandre F. Tenca, Georgi Todorov, Çetin Kaya Koç |
High-Radix Design of a Scalable Modular Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, pp. 185-201, 2001, Springer, 3-540-42521-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
modular multiplier, montgomery multiplier, high-radix, scalable architecture |
36 | Alexandre F. Tenca, Milos D. Ercegovac |
On the Design of High-Radix On-Line Division for Long Precision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 44-51, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
36 | Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata |
High Radix Cordic Rotation Based on Selection by Rounding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 155-164, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Rotation mode, High radix algorithm, CORDIC algorithm |
36 | Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera |
Radix-4 Vectoring Cordic Algorithm And Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 55-64, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
radix-4 vectoring CORDIC algorithm, radix-4 vectoring CORDIC architectures, vectoring mode, microrotations, zero skipping technique, recursive architectures, matrix triangularization, rotation angle, computational complexity, complexity, parallel architectures, singular value decomposition, SVD, signal processing, digital arithmetic, digital arithmetic, matrix algebra, pipelined architectures |
36 | Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata |
Redundant CORDIC Rotator Based on Parallel Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 172-179, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
High speed processor, Parallel prediction, Parallel architecture, CORDIC algorithm, Redundant arithmetic |
33 | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 398-402, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron |
32 | Nan Jiang 0009, David Money Harris |
Parallelized radix-2 scalable Montgomery multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 146-150, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Alexander A. Petrovsky, Sergei L. Shkredov |
Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland, pp. 181-186, 2006, IEEE Computer Society, 0-7695-2554-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Kooroush Manochehri, Saadat Pourmozafari |
Modified Radix-2 Montgomery Modular Multiplication to Make It Faster and Simpler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (1) ![In: International Symposium on Information Technology: Coding and Computing (ITCC 2005), Volume 1, 4-6 April 2005, Las Vegas, Nevada, USA, pp. 598-602, 2005, IEEE Computer Society, 0-7695-2315-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Radix2, Exponentiation, Modular multiplication, Montgomery, CSA |
29 | Gautam Abhaychand Shah, Tejmal Saubhagyamal Rathore |
A New Fast Radix-2 Decimation-in-Frequency Algorithm for Computing the Discrete Hartley Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICSyN ![In: First International Conference on Computational Intelligence, Communication Systems and Networks, CICSYN 2009, Indore, India, 23-25 July, 2009, pp. 363-368, 2009, IEEE Computer Society, 978-0-7695-3743-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
decimation-in-frequency, discrete Hartley transform, matrix approach, algorithm, radix-2 |
29 | Mahn-ling Woo, Rosemary A. Renaut |
Unordered parallel distance-1 and distance-2 FFT algorithms of radix 2 and (4-2). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 1994 ACM Symposium on Applied Computing, SAC'94, Phoenix, AZ, USA, March 6-8, 1994, pp. 504-509, 1994, ACM, 0-89791-647-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
mixed-radix (4-2) FFT, parallel FFT algorithms, radix-2 FFT, complexity analysis |
29 | Shalhav Zohar |
Rounding and Truncation in Radix (-2) Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 25(5), pp. 464-469, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
N-bit rounding algorithms, radix (-2), rounding error bounds, truncation errors |
29 | Paul W. Baker |
More Efficient Radix-2 Algorithms for Some Elementary Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(11), pp. 1049-1054, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
variable left shift, Digital arithmetic, iterative algorithms, elementary functions, radix 2 |
28 | Renato H. Neuenfeld, Mateus Beck Fonseca, Eduardo A. C. da Costa, Jean P. Oses |
Exploiting addition schemes for the improvement of optimized radix-2 and radix-4 fft butterflies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 8th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2017, Bariloche, Argentina, February 20-23, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5859-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Zhuo Qian, Martin Margala |
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(9), pp. 3008-3012, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Renato Neuenfeld, Mateus Fonseca, Eduardo A. C. da Costa |
Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 7th Latin American Symposium on Circuits & Systems, LASCAS 2016, Florianopolis, Brazil, February 28 - March 2, 2016, pp. 171-174, 2016, IEEE, 978-1-4673-7835-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Manzur Rahman, Arindam Sanyal, Nan Sun 0001 |
A Novel Hybrid Radix-3/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 62-II(5), pp. 426-430, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Andrew Carter, Paula Ning, William Koven, David Money Harris, Michael Braly, Nathan Jones, Julien Massas, Trevin Murakami, Alexandra Simoni, Sanu Mathew |
Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, November 3-6, 2013, pp. 1144-1148, 2013, IEEE, 978-1-4799-2390-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | Waqar Hussain 0001, Fabio Garzia, Jari Nurmi |
Evaluation of Radix-2 and Radix-4 FFT processing on a reconfigurable platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 249-254, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Peter Westermann, Hartmut Schröder |
Constraints on the SIMD vectorization of radix-2 and mixed-radix FFTS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 17th European Signal Processing Conference, EUSIPCO 2009, Glasgow, Scotland, UK, August 24-28, 2009, pp. 1274-1278, 2009, IEEE, 978-161-7388-76-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
28 | Saad Bouguezel, M. Omair Ahmad, M. N. Shanmukha Swamy |
New radix-(2×2×2)/(4×4×4) and radix-(2×2×2)/(8×8×8) DIF FFT algorithms for 3-D DFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2), pp. 306-315, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Alexander A. Petrovsky, Sergei L. Shkredov |
Radix 2 and split radix 2-4 algorithms in formal synthesis of parallel-pipeline FFT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 2004 12th European Signal Processing Conference, Vienna, Austria, September 6-10, 2004, pp. 1529-1532, 2004, IEEE, 978-320-0001-65-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
28 | Chitlur Nagabhushan, Olga Kosheleva, Sergio D. Cabrera, Glenn A. Gibson |
Design of Radix-2 and Radix-4 FFT Processors Using a Modular Architecture Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1996, August 9-11, 1996, Sunnyvale, California, USA, pp. 589-599, 1996, CSREA Press, 0-9648666-4-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP BibTeX RDF |
|
27 | Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi |
An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Public Key Cryptography ![In: Public Key Cryptography - PKC 2008, 11th International Workshop on Practice and Theory in Public-Key Cryptography, Barcelona, Spain, March 9-12, 2008. Proceedings, pp. 214-228, 2008, Springer, 978-3-540-78439-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication |
27 | Zhongfeng Wang 0001 |
High-Speed Recursion Architectures for MAP-Based Turbo Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 470-474, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Y. Wang, Y. Tang, Y. Jiang, Y.-G. Chung, S.-S. Song, M.-S. Lim |
Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 55(5-2), pp. 2338-2349, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Shengmei Mou, Xiaodong Yang 0002 |
Research on the RAW Dependency in Floating-point FFT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SNPD (1) ![In: Proceedings of the 8th ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2007, July 30 - August 1, 2007, Qingdao, China, pp. 88-92, 2007, IEEE Computer Society, 0-7695-2909-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Sylvie Boldo |
Pitfalls of a Full Floating-Point Proof: Example on the Formal Proof of the Veltkamp/Dekker Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCAR ![In: Automated Reasoning, Third International Joint Conference, IJCAR 2006, Seattle, WA, USA, August 17-20, 2006, Proceedings, pp. 52-66, 2006, Springer, 3-540-37187-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Zhongjun Wang, Lee Guek Yeo, Wenzhen Li, Yanxin Yan, Yujing Ting, Masayuki Tomisawa |
A Novel FFT Processor for OFDM UWB Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 374-377, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy |
Efficient output-pruning of the 2-D FFT algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 285-288, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera |
High-Radix Logarithm with Selection by Rounding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 101-110, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu 0002, Ming-Hwa Sheu, Jia-Lin Sheu |
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 500-503, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Stuart F. Oberman, Michael J. Flynn |
Minimizing the complexity of SRT tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(1), pp. 141-149, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
27 | M. C. Mekhallalati, Ahmed S. Ashur, M. K. Ibrahim |
Novel Radix Finite Field Multiplier for GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(3), pp. 233-245, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
27 | Francisco Argüello, Emilio L. Zapata |
Constant geometry split-radix algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 10(2), pp. 141-152, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
27 | Chung Nan Lyu, David W. Matula |
Redundant Binary Booth Recoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 50-, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
27 | Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata |
Digit On-line Large Radix CORDIC Rotator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 246-257, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Digit on-line processing, Pipelined array architecture, VLSI architecture, Application-specific processor, CORDIC algorithm |
27 | Stephen E. McQuillan, John V. McCanny |
Fast VLSI algorithms for division and square root. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 8(2), pp. 151-168, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
24 | Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu |
Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 14-19, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
differential-pair circuit, radix-2 signed-digit adder, reliability |
24 | Jarmo Takala, Konsta Punkka |
Scalable FFT Processors and Pipelined Butterfly Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 43(2-3), pp. 113-123, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
parallel processing, application-specific integrated circuit, CORDIC, distributed arithmetic, radix-2 |
24 | Syed Mahfuzul Aziz, S. J. Carr |
On C-Testability of Carry Free Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 417-424, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Carry-free, C-Testability, Divider, Radix-2 |
24 | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 382-390, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder |
24 | Lutz J. Micheel, Hans L. Hartnagel |
Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 80-85, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion |
24 | Ryutaro Murakami, Yoshiteru Ohkura, Ryosaku Shimada |
2k-ary Cyclic AN Codes for Burst Error Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 228-235, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
2/sup k/-ary cyclic AN codes, burst error correction, radix 2/sup k/ expressions, code structure, arithmetic burst errors, burst error correction ability, binary cyclic AN code, error correction codes, error detection, error detection codes, arithmetic codes, arithmetic operations, cyclic codes |
23 | Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi |
A Radix-2 Digit-by-Digit Architecture for Cube Root. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(4), pp. 562-566, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Cost/performance, High-Speed Arithmetic |
23 | Hani H. Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr. |
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 7-12, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 534-540, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Fault tolerance, error checking, high-speed arithmetic |
23 | Andreas Lindahl, Lars Bengtsson |
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 42-47, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | David Money Harris, Ram Krishnamurthy 0001, Mark A. Anders 0001, Sanu Mathew, Steven Hsu |
An Improved Unified Scalable Radix-2 Montgomery Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 172-178, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy |
An approach for computing the radix-2/4 DIT FHT and FFT algorithms using a unified structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 836-839, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Hosahalli R. Srinivas, Keshab K. Parhi |
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 21(1), pp. 37-60, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Gensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto |
30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 98-, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
simulation, CMOS, division, square root, self-timed, SRT, on-the-fly |
18 | Clemens Heuberger, James A. Muir |
Unbalanced digit sets and the closest choice strategy for minimal weight integer representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 52(2), pp. 185-208, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classifications (2000) 11A63, 94A60, 68W40 |
18 | Markus Püschel, Martin Rötteler |
Algebraic signal processing theory: Cooley-Tukey type algorithms on the 2-D hexagonal spatial lattice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Algebra Eng. Commun. Comput. ![In: Appl. Algebra Eng. Commun. Comput. 19(3), pp. 259-292, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro |
A Digit-by-Digit Algorithm for mth Root Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(12), pp. 1696-1706, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
integer rooting, digit-by-digit algorithms, higher radix, computer arithmetic |
18 | Yingtuo Ju, Guoan Bi |
Generalized Fast Algorithms for the Polynomial Time-Frequency Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 55(10), pp. 4907-4915, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Soo-Chang Pei, Kuo-Wei Chang |
Efficient Bit and Digital Reversal Algorithm Using Vector Calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 55(3), pp. 1173-1175, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Nathaniel Ross Pinckney, David Money Harris |
Parallelized radix-4 scalable montgomery multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 306-311, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cryptography, RSA, Montgomery Multiplication |
18 | Abdulah Abdulah Zadeh |
High Speed Modular Divider Based on GCD Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 9th International Conference, ICICS 2007, Zhengzhou, China, December 12-15, 2007, Proceedings, pp. 189-200, 2007, Springer, 978-3-540-77047-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
GCD algorithm, Radix four, Finite Field, ECC |
18 | Chih-Peng Fan, Guo-An Su |
A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1939-1942, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Marcelo E. Kaihara, Naofumi Takagi |
A Hardware Algorithm for Modular Multiplication/Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(1), pp. 12-21, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
modular division, cryptography, Computer arithmetic, modular multiplication, redundant representation, hardware algorithm |
18 | Alessandro Cilardo, Antonino Mazzeo, Nicola Mazzocca, Luigi Romano |
A Novel Unified Architecture for Public-Key Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 52-57, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu |
Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5254-5257, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | James A. Muir, Douglas R. Stinson |
New Minimal Weight Representations for Left-to-Right Window Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2005, The Cryptographers' Track at the RSA Conference 2005, San Francisco, CA, USA, February 14-18, 2005, Proceedings, pp. 366-383, 2005, Springer, 3-540-24399-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Kyle Kelley, David Money Harris |
Very High Radix Scalable Montgomery Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 400-404, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Yijun Liu, Stephen B. Furber |
The design of a low power asynchronous multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 301-306, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Booth's algorithm, low power, benchmark, multiplier, asynchronous logic |
18 | Attif A. Ibrahem, Hamed Elsimary, Aly E. Salama |
FPGA Implementation of Fast Radix 4 Division Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 69-72, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fast division, radix 4 division, quotient selection, Field programmable gate arrays (FPGAs) |
18 | Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy |
Efficient pruning algorithms for the DFT computation for a subset of output samples. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 97-100, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Shing-Chow Chan, Kai Man Tsui |
Multiplier-less real-valued FFT-like transformation (ML-RFFT) and related real-valued transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 257-260, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | S. C. Chan 0001, P. M. Yiu |
A multiplier-less 1-D and 2-D fast Fourier transform-like transformation using sum-of-powers-of-two (SOPOT) coefficients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 755-758, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu |
Design of an efficient FFT processor for DAB system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 654-657, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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