Search results for "register-file"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
151	Marc Tremblay, Bill Joy 0001, Ken Shin	A three dimensional register file for superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
143	Jinpyo Park, Je-Hyung Lee, Soo-Mook Moon	Register Allocation for Banked Register File.	LCTES/OM	2001	DBLP DOI BibTeX RDF	banked register file, register allocation
125	José-Lorenzo Cruz, Antonio González 0001, Mateo Valero, Nigel P. Topham	Multiple-banked register file architectures.	ISCA	2000	DBLP DOI BibTeX RDF	bypass logic, register file architecture, register file cache, dynamically-scheduled processor
116	Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero	Speculative early register release.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	physical register release, optimization, register file, register renaming
112	Xuan Guan, Yunsi Fei	Reducing power consumption of embedded processors through register file partitioning and compiler support.	ASAP	2008	DBLP DOI BibTeX RDF
105	Masaaki Kondo, Hiroshi Nakamura	A Small, Fast and Low-Power Register File by Bit-Partitioning.	HPCA	2005	DBLP DOI BibTeX RDF
101	Nan Wu 0003, Mei Wen, Ju Ren 0002, Yi He 0008, Chunyuan Zhang	Register Allocation on Stream Processor with Local Register File.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	local register file, spilling, register allocation, VLIW, stream processor
99	Rakesh Nalluri, Rohan Garg 0003, Preeti Ranjan Panda	Customization of Register File Banking Architecture for Low Power.	VLSI Design	2007	DBLP DOI BibTeX RDF
95	Rama Sangireddy	Register Organization for Enhanced On-Chip Parallelism.	ASAP	2004	DBLP DOI BibTeX RDF
95	Jason Cong, Yiping Fan, Junjuan Xu	Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	distributed register file, Behavioral synthesis, resource binding
94	Rahul Nagpal, Y. N. Srikant	Register File Energy Optimization for Snooping Based Clustered VLIW Architectures.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
91	André Seznec, Eric Toullec, Olivier Rochecouste	Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors.	MICRO	2002	DBLP DOI BibTeX RDF
91	Miquel Pericàs, Rubén González 0001, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero	An Optimized Front-End Physical Register File with Banking and Writeback Filtering.	PACS	2004	DBLP DOI BibTeX RDF
90	Jason Cong, Yiping Fan, Wei Jiang	Platform-based resource binding using a distributed register-file microarchitecture.	ICCAD	2006	DBLP DOI BibTeX RDF	distributed register file, behavior synthesis, resource binding
90	Rubén González 0001, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero	A Content Aware Integer Register File Organization.	ISCA	2004	DBLP DOI BibTeX RDF
88	Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie	Bypass aware instruction scheduling for register file power reduction.	LCTES	2006	DBLP DOI BibTeX RDF	architecture-sensitive compiler, bypass-sensitive, forwarding paths, operation table, processor bypasses, reservation table, power consumption, register file
87	Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González 0001	Early Register Release for Out-of-Order Processors with RegisterWindows.	PACT	2007	DBLP DOI BibTeX RDF
86	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Reducing the complexity of the register file in dynamic superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
84	Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev	Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure.	MICRO	2004	DBLP DOI BibTeX RDF
83	Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi	A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors.	HASE	2008	DBLP DOI BibTeX RDF
80	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.	Int. J. Parallel Program.	2004	DBLP DOI BibTeX RDF	register requirements, register file organization, clustered organization, Modulo scheduling, spill code
80	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP synthesis.	CASES	2002	DBLP DOI BibTeX RDF	ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis
79	Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens	Communication Scheduling.	ASPLOS	2000	DBLP DOI BibTeX RDF
78	Yingchao Zhao 0001, Chun Jason Xue, Minming Li, Bessie C. Hu	Energy-aware register file re-partitioning for clustered VLIW architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
77	Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi	The anatomy of the register file in a multiscalar processor.	MICRO	1994	DBLP DOI BibTeX RDF
77	Raid Ayoub, Alex Orailoglu	Power efficient register file update approach for embedded processors.	ICCD	2007	DBLP DOI BibTeX RDF
74	José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo	Power-Aware Compilation for Register File Energy Reduction.	Int. J. Parallel Program.	2003	DBLP DOI BibTeX RDF	register file management, compiler support, energy aware
74	Nam Sung Kim, Trevor N. Mudge	The microarchitecture of a low power register file.	ISLPED	2003	DBLP DOI BibTeX RDF	write queue, low power, instruction level parallelism, register file, out-of-order processor
74	Jun Yan 0008, Wei Zhang 0002	Compiler-guided register reliability improvement against soft errors.	EMSOFT	2005	DBLP DOI BibTeX RDF	register lifetime, reliability, soft errors, register file
73	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Hierarchical Clustered Register File Organization for VLIW Processors.	IPDPS	2003	DBLP DOI BibTeX RDF
72	Jie S. Hu, Shuai Wang 0006, Sotirios G. Ziavras	In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.	DSN	2006	DBLP DOI BibTeX RDF
72	Ming Yang, Lixin Yu, Heping Peng	Energy Efficient Register File with Reduced Window Partition.	ICPADS	2008	DBLP DOI BibTeX RDF
72	Soontae Kim	Reducing ALU and Register File Energy by Dynamic Zero Detection.	IPCCC	2007	DBLP DOI BibTeX RDF
71	Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi	Physical Register Inlining.	ISCA	2004	DBLP DOI BibTeX RDF
69	Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch	Design of superscalar processor with multi-bank register file.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
69	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Increasing the number of effective registers in a low-power processor using a windowed register file.	CASES	2003	DBLP DOI BibTeX RDF	window assignment, low-power, graph partitioning, embedded processor, instruction encoding, register window
68	Ge Zhang, Xu Yang, Yiwei Zhang	Architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File.	NAS	2009	DBLP DOI BibTeX RDF
68	Rama Sangireddy	Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors.	ITNG	2006	DBLP DOI BibTeX RDF
68	Rama Sangireddy, Arun K. Somani	Exploiting Quiescent States in Register Lifetime.	ICCD	2004	DBLP DOI BibTeX RDF
68	C. P. Ravikumar, R. Aggarwal, C. Sharma	A Graph-Theoretic Approach for Register File Based Synthesis.	VLSI Design	1997	DBLP DOI BibTeX RDF
67	Jun Yan 0008, Wei Zhang 0002	Virtual Registers: Reducing Register Pressure Without Enlarging the Register File.	HiPEAC	2007	DBLP DOI BibTeX RDF
65	Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose	Increasing Processor Performance Through Early Register Release.	ICCD	2004	DBLP DOI BibTeX RDF
65	Oguz Ergin, Deniz Balkan, Dmitry Ponomarev 0001, Kanad Ghose	Early Register Deallocation Mechanisms Using Checkpointed Register Files.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	register file optimization, Superscalar processors, precise interrupts
64	Wann-Yun Shieh, Hsin-Dar Chen	Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB.	EUC Workshops	2006	DBLP DOI BibTeX RDF	register leakage power, high-end embedded processor, dynamic voltage scaling (DVS), reorder buffer
64	Krishnan Kailas, Manoj Franklin, Kemal Ebcioglu	A Register File Architecture and Compilation Scheme for Clustered ILP Processors.	Euro-Par	2002	DBLP DOI BibTeX RDF
63	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Versatility of extended subwords and the matrix register file.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	SIMD programming, SIMD architectures, multimedia standards
63	Mazen A. R. Saghir, Rawan Naous	A Configurable Multi-ported Register File Architecture for Soft Processor Cores.	ARC	2007	DBLP DOI BibTeX RDF
63	Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae	A three-port nRERL register file for ultra-low-energy applications.	ISLPED	2000	DBLP DOI BibTeX RDF
63	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang	A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.	VLSI Design	2000	DBLP DOI BibTeX RDF
63	Rajiv V. Joshi, Wei Hwang	Design Considerations and Implementation of a High Performance Dynamic Register File.	VLSI Design	1999	DBLP DOI BibTeX RDF
63	Jan Hoogerbrugge, Henk Corporaal	Register file port requirements of transport triggered architectures.	MICRO	1994	DBLP DOI BibTeX RDF
63	JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally	Register pointer architecture for efficient embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
63	Teresa Monreal, Víctor Viñals, José González 0002, Antonio González 0001, Mateo Valero	Late Allocation and Early Release of Physical Registers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
63	Il Park 0001, Michael D. Powell, T. N. Vijaykumar	Reducing register ports for higher speed and lower energy.	MICRO	2002	DBLP DOI BibTeX RDF
62	G. X. Tyson, M. Smelyanskyi, Edward S. Davidson	Evaluating the Use of Register Queues in Software Pipelined Loops.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW
62	Robert Yung, Neil C. Wilhelm	Caching processor general registers.	ICCD	1995	DBLP DOI BibTeX RDF	caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file
62	Xiangrong Zhou, Chenjie Yu, Peter Petrov	Temperature-aware register reallocation for register file power-density minimization.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF
62	Xiangrong Zhou, Chenjie Yu, Peter Petrov	Compiler-driven register re-assignment for register file power-density and temperature reduction.	DAC	2008	DBLP DOI BibTeX RDF	power-density minimization, thermal management
62	Chung-Wen Huang, Kun-Yuan Hsieh, Jia-Jhe Li, Jenq Kuen Lee	Support of Paged Register Files for Improving Context Switching on Embedded Processors.	CSE (2)	2009	DBLP DOI BibTeX RDF
62	Mallik Kandala, Wei Zhang 0002, Laurence Tianruo Yang	An Area-Efficient Approach to Improving Register File Reliability against Transient Errors.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
62	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Matrix register file and extended subwords: two techniques for embedded media processors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	embedded media processors, multimedia kernels, sub-word parallelism, register file
61	Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen	Software-Directed Register Deallocation for Simultaneous Multithreaded Processors.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	architecture, register file, simultaneous multithreading, Multithreaded architecture
59	Shuai Wang 0006, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras	Asymmetrically Banked Value-Aware Register Files.	ISVLSI	2007	DBLP DOI BibTeX RDF
59	Meng-chou Chang, Feipei Lai	Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors
59	David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy	A Method for Register Allocation to Loops in Multiple Register File Architectures.	IPPS	1996	DBLP DOI BibTeX RDF
58	Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin	Compiler Directed Early Register Release.	IEEE PACT	2005	DBLP DOI BibTeX RDF
58	Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk 0001	Increasing Register File Immunity to Transient Errors.	DATE	2005	DBLP DOI BibTeX RDF
58	Ulrich Hirnschrott, Andreas Krall, Bernhard Scholz	Graph Coloring vs. Optimal Register Allocation for Optimizing Compilers.	JMLC	2003	DBLP DOI BibTeX RDF
58	Xianglong Huang, Steve Carr 0001, Philip H. Sweany	Loop Transformations for Architectures with Partitioned Register Banks.	LCTES/OM	2001	DBLP DOI BibTeX RDF
57	Sandeep Sirsi, Aneesh Aggarwal	Exploring the Limits of Port Reduction in Centralized Register Files.	VLSI Design	2009	DBLP DOI BibTeX RDF
57	Jer-Yu Hsu, Yan-Zu Wu, Xuan-Yi Lin, Yeh-Ching Chung	SCRF - A Hybrid Register File Architecture.	PaCT	2007	DBLP DOI BibTeX RDF	cluster processor architecture, register architecture, register allocation algorithm, VLIW processor
57	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.	DAC	2008	DBLP DOI BibTeX RDF	dynamic resizing, performance, embedded processor, register file
57	Kimish Patel, Wonbok Lee, Massoud Pedram	Active bank switching for temperature control of the register file in a microprocessor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	register file, thermal model, temperature-aware design
56	Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala	Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic.	SAMOS	2008	DBLP DOI BibTeX RDF
56	Zion S. Kwok, Steven J. E. Wilton	Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture.	FCCM	2005	DBLP DOI BibTeX RDF
55	Wann-Yun Shieh, Chien-Chen Chen	Exploiting Register-Usage for Saving Register-File Energy in Embedded Processors.	EUC	2005	DBLP DOI BibTeX RDF
55	Lushan Liu, Ramalingam Sridhar, Shambhu J. Upadhyaya	A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells.	DFT	2006	DBLP DOI BibTeX RDF
55	Laura Pozzi, Paolo Ienne	Exploiting pipelining to relax register-file port constraints of instruction-set extensions.	CASES	2005	DBLP DOI BibTeX RDF	automatic instruction-set extension, constrained scheduling, embedded customised architectures, multi-cycle register access, input/output
55	Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan	Analysis of the influence of register file size on energyconsumption, code size, and execution time.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
55	Soner Önder, Rajiv Gupta 0001	Load and store reuse using register file contents.	ICS	2001	DBLP DOI BibTeX RDF
54	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal	Very wide register: an asymmetric register file organization for low power embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
53	Xuejun Yang, Yu Deng 0001, Li Wang 0027, Xiaobo Yan, Jing Du 0002, Ying Zhang 0032, Guibin Wang, Tao Tang 0001	SRF Coloring: Stream Register File Allocation via Graph Coloring.	J. Comput. Sci. Technol.	2009	DBLP DOI BibTeX RDF	SRF coloring, stream register file, memory management, compiler optimization, graph coloring, stream processor
52	Hui Zeng, Kanad Ghose	Register file caching for energy efficiency.	ISLPED	2006	DBLP DOI BibTeX RDF	register caching, energy-efficiency, register files
52	Yanjun Zhang, Hu He 0001, Yihe Sun	A new register file access architecture for software pipelining in VLIW processors.	ASP-DAC	2005	DBLP DOI BibTeX RDF
52	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
52	Je-Hyung Lee, Jinpyo Park, Soo-Mook Moon	Securing More Registers with Reduced Instruction Encoding Architectures.	RTCSA	2007	DBLP DOI BibTeX RDF
52	Herbert H. J. Hum, Guang R. Gao	A Novel High-Speed Memory Organization for Fine-Grain Multi-Thread Computing.	PARLE (1)	1991	DBLP DOI BibTeX RDF
52	Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001, Oguz Ergin	Exploring the limits of early register release: Exploiting compiler analysis.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	compiler, energy efficiency, Low-power design, microarchitecture, register file
51	Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim	Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture.	DAC	2007	DBLP DOI BibTeX RDF
51	Xuemei Zhao, Yizheng Ye	Design and Realization of a Low Power Register File Using Energy Model.	PATMOS	2002	DBLP DOI BibTeX RDF
48	Gilles Pokam, Olivier Rochecouste, André Seznec, François Bodin	Speculative software management of datapath-width for energy optimization.	LCTES	2004	DBLP DOI BibTeX RDF	narrow-width regions, compiler, reconfigurable computing, speculative execution, energy management, clock-gating
48	Matthias Müller 0002, Andreas Wortmann 0002, Dominik Mader, Sven Simon 0001	Register Isolation for Synthesizable Register Files.	PATMOS	2004	DBLP DOI BibTeX RDF
48	Nam Sung Kim, Trevor N. Mudge	Reducing register ports using delayed write-back queues and operand pre-fetch.	ICS	2003	DBLP DOI BibTeX RDF	write queue, low power, instruction level parallelism, register file, out-of-order processor
48	Stephen Roderick Hines, Gary S. Tyson, David B. Whalley	Addressing instruction fetch bottlenecks by using an instruction register file.	LCTES	2007	DBLP DOI BibTeX RDF	L0/filter cache, instruction packing, instruction register file
48	Rama Sangireddy, Arun K. Somani	Application-Specific Computing with Adaptive Register File Architectures.	ASAP	2003	DBLP DOI BibTeX RDF	Computing capacity, compute-intensive Function, Memory bandwidth, Register File
48	Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan	Evaluating register file size in ASIP design.	CODES	2001	DBLP DOI BibTeX RDF	instruction power model, synthesis, application specific instruction set processor, instruction set, register file, register spill
48	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Aneesh Aggarwal	Address-Value Decoupling for Early Register Deallocation.	ICPP	2006	DBLP DOI BibTeX RDF
48	Montserrat Ros, Peter Sutton	A post-compilation register reassignment technique for improving hamming distance code compression.	CASES	2005	DBLP DOI BibTeX RDF	register reassignment, hamming distance, code compression
48	R. David Weldon, Steven S. Chang, Hong Wang 0003, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen	Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF
48	Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev	Reducing register pressure in SMT processors through L2-miss-driven early register release.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	register file, Simultaneous multithreading