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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 360 occurrences of 230 keywords
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Results
Found 408 publication records. Showing 408 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
98 | Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
A SIMD optimization framework for retargetable compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(1), pp. 2:1-2:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SIMD, vectorization, ASIP, subword parallelism, retargetable compilers |
98 | Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren 0001 |
Retargetable code optimization with SIMD instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 148-153, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SIMD, vectorization, subword parallelism, retargetable compilers |
74 | Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001 |
A retargetable framework for instruction-set architecture simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 431-452, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm |
70 | Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens |
Processor modeling and code selection for retargetable compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 277-307, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
code selection, graph instruction set graph, retargetable code generation, embedded systems, system design, retargetable compilation, processor modeling |
66 | Emilio Wuerges, Luiz C. V. dos Santos, Olinto J. V. Furtado, Sandro Rigo |
An early real-time checker for retargetable compile-time analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
compile-time WCET analysis, time-constraint feasibility analysis |
66 | Manuel Hohenauer, Felix Engel 0001, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh |
Retargetable Code Optimization for Predicated Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1492-1497, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
66 | Sejong Oh, Yunheung Paek |
A Quantitative Comparison of Two Retargetable Compilation Approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October 2003, Kaohsiung, Taiwan, pp. 29-, 2003, IEEE Computer Society, 0-7695-2017-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
66 | Jay W. Warfield, Henry R. Bauer III |
An expert system for a retargetable peephole optimizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 23(10), pp. 123-130, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
63 | Heekyung Kim, Dukyoung Yun, Soonhoi Ha |
Scalable and retargetable simulation techniquesfor multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 89-98, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
simulation, scalable, parallel, distributed, multiprocessor, retargetable |
63 | Jason Hiser, Jack W. Davidson |
EMBARC: an efficient memory bank assignment algorithm for retargetable compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 182-191, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
partition assignment, embedded systems, retargetable compilers |
59 | Hans M. Mulder, Robert J. Portier |
Cost-effective design of application specific VLIW processors using the SCARCE framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989, pp. 35-42, 1989, ACM/IEEE, 0-89791-324-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
55 | Lothar Nowak, Peter Marwedel |
Verification of Hardware Descriptions by Retargetable Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 441-447, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
51 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra 0001, Xu Cheng 0001 |
A Retargetable Software Timing Analyzer Using Architecture Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 396-401, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis |
51 | Wei Qin, Joseph D'Errico, Xinping Zhu |
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 193-198, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
retargetable, instruction set simulator, compiled simulation |
51 | Hoonmo Yang, Moonkey Lee |
Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 33(1-2), pp. 19-32, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cycle-accurate, validation, system-on-chip (SoC), architecture description language (ADL), retargetable, instruction-set simulator |
51 | Xinping Zhu, Wei Qin, Sharad Malik |
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 66-71, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
on-chip communication architecture, simulator synthesis, multiprocessor system, packet-switching network, design exploration, bus, retargetable simulation |
51 | Lukai Cai, Andreas Gerstlauer, Daniel Gajski |
Retargetable profiling for rapid, early system-level design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 281-286, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
profiling, exploration, system level design, retargetable |
51 | Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt |
An efficient retargetable framework for instruction-set simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 13-18, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm |
51 | Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau |
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(4), pp. 752-773, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
code size minimization, custom templates, instruction format design, noop compression, retargetable assembly, VLIW, design automation, EPIC |
51 | Scott R. Tilley |
Domain-retargetable reverse engineering. III. Layered modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: Proceedings of the International Conference on Software Maintenance, ICSM 1995, Opio (Nice), France, October 17-20, 1995, pp. 52-, 1995, IEEE Computer Society, 0-8186-7141-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
layered modeling, domain-retargetable reverse engineering, structural understanding, large information spaces, reverse engineering, relational databases, software maintenance, software tools, conceptual modeling, tools, hypertext, artifacts |
51 | Robert A. Mueller, Michael R. Duda, Philip H. Sweany, Jack S. Walicki |
Horizon: A Retargetable Compiler for Horizontal Microarchitectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 14(5), pp. 575-583, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
horizontal microarchitectures, vertical migration, complex application code, horizontal microcode, optimized microcode, concurrency, abstraction, timing, program compilers, microprogramming, retargetable compiler, assembly languages, Horizon |
47 | Yong-Kyu Jung |
Fault-recovery Non-FPGA-based Adaptable Computing System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 709-716, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | José O. Carlomagno Filho, Luiz F. P. Santos, Luiz C. V. dos Santos |
An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 86-95, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Dan Wu, Zhiying Wang 0003, Kui Dai |
Retargetable Machine-Description System: Multi-layer Architecture Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCC ![In: Grid and Cooperative Computing - GCC 2005, 4th International Conference, Beijing, China, November 30 - December 3, 2005, Proceedings, pp. 1161-1166, 2005, Springer, 3-540-30510-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang |
RCGES: Retargetable Code Generation for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings, pp. 415-425, 2004, Springer, 3-540-23610-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Gabriele Luculli |
An ISA-Retargetable Framework for Embedded Software Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 10th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2003), 7-10 April 2003, Huntsville, AL, USA, pp. 183-190, 2003, IEEE Computer Society, 0-7695-1917-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Ling Liu, Wennan Feng, Song Jia, Anping Jiang, Lijiu Ji |
Design Retargetable Platform System for Microprocessor Functional Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 458-461, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Valérie Bertin, Jean-Marc Daveau, Philippe Guillaume, Thierry Lepley, Denis Pilat, Claire Richard, Miguel Santana, Thomas Thery |
FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Embedded Software, Second International Conference, EMSOFT 2002, Grenoble, France, October 7-9, 2002, Proceedings, pp. 382-398, 2002, Springer, 3-540-44307-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama |
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11), pp. 1319-1328, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Rajiv A. Ravindran, Rajat Moona |
Retargetable Cache Simulation Using High Level Processor Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 6th Australasian Computer Systems Architecture Conference (ACSAC 2001), 29-30 January 2001, Gold Coast, Queensland, Australia, pp. 114-129, 2001, IEEE Computer Society, 0-7695-0954-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | B. S. Visser |
A Framework for Retargetable Code Generation Using Simulated Annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1458-1462, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Silvina Hanono, Srinivas Devadas |
Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 510-515, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian |
43 | David Ung, Cristina Cifuentes |
SRL 3/4-A Simple Retargetable Loader. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Software Engineering Conference ![In: 1997 Australian Software Engineering Conference (ASWEC '97), 28 September - 2 October 1997, Sydney, Australia, pp. 60-69, 1997, IEEE Computer Society, 0-8186-8081-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
43 | Thomas M. Morgan, Lawrence A. Rowe |
Analyzing Exotic Instructions for a Retargetable Code Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGPLAN Symposium on Compiler Construction ![In: Proceedings of the SIGPLAN '82 Symposium on Compiler Construction, Boston, Massachusetts, USA, June 23-25, 1982, pp. 197-204, 1982, ACM, 0-89791-074-5. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
39 | Francesco Papariello, Gabriele Luculli |
Optimization of a Retargetable Functional Simulator for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 9th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2002), 8-11 April 2002, Lund, Sweden, pp. 203-210, 2002, IEEE Computer Society, 0-7695-1549-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
retargetable ISS, platform design, system-on-chip, embedded processors, system-level design |
39 | John H. Shamilian, Henry S. Baird, Thomas L. Wood |
A retargetable table reader. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: 4th International Conference Document Analysis and Recognition (ICDAR '97), 2-Volume Set, August 18-20, 1997, Ulm, Germany, Proceedings, pp. 158-163, 1997, IEEE Computer Society, 0-8186-7898-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
retargetable table reader, machine-printed documents, predefined tabular-data layout, textual data, record lines, fixed-width fields, field-specific contextual knowledge, small print, tight line-spacing, photocopies, line-art, background patterns, pitch-estimation, high-performance OCR, segmentation, graphical user interface, neural nets, document image processing, skew-correction |
39 | Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya |
Industrial experience using rule-driven retargetable code generation for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 60-68, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VideoPhone codec controller, audio telecommunications, dedicated compiler availability, high-fidelity audio, optimization abilities, rule-driven retargetable code generation, video telecommunications, knowledge based systems, computer architecture, multiprocessing systems, multimedia systems, application specific integrated circuits, multimedia applications, application-specific instruction set processors, instruction sets, telecommunication computing, codecs, VLIW processor, VLIW architecture, transformation rules, controller architecture, optimising compilers, industrial experience, videotelephony, target architecture, MPEG audio |
35 | Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren 0001 |
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1276-1283, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Norman Ramsey, Jack W. Davidson |
Machine Descriptions to Build Tools for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES'98, Montreal, Canada, June 1998, Proceedings, pp. 176-192, 1998, Springer, 3-540-65075-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | João Dias, Norman Ramsey |
Automatically generating instruction selectors using declarative machine descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Proceedings of the 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2010, Madrid, Spain, January 17-23, 2010, pp. 403-416, 2010, ACM, 978-1-60558-479-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
declarative machine descriptions, retargetable compilers, instruction selection |
31 | Xinping Zhu, Sharad Malik |
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 6:1-6:24, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
on-chip communication architecture, network-on-chip, multiprocessor system, object-oriented modeling, packet-switching network, design exploration, bus, Retargetable simulation |
31 | Florian Brandner, Dietmar Ebner, Andreas Krall |
Compiler generation from structural architecture descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 13-22, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ADL, architecture description, retargetable compiler |
31 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau |
Operation tables for scheduling in the presence of incomplete bypassing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 194-199, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hazard detection, operation table, reservation table, scheduling, retargetable compilers, bypass |
31 | Ronan Amicel, François Bodin |
Mastering Startup Costs in Assembler-Based Compiled Instruction-Set Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USA, pp. 39-44, 2002, IEEE Computer Society, 0-7695-1534-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
compiled instruction-set simulation, embedded systems, high performance, assembler, development tools, retargetable |
31 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 252-261, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis |
31 | Young Geol Kim, Tag Gon Kim |
A Design and Tool Reuse Methodology for Rapid Prototyping of Application Specific Instruction Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 46-51, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Rapid prototyping, ASIP, Design reuse, Architecture description, Retargetable simulator |
31 | Alessandro Balboni, William Fornaciari, Massimo Vincenzi, Donatella Sciuto |
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 9th International Symposium on System Synthesis, ISSS '96, San Diego, CA, USA, November 6-8, 1996., pp. 77-82, 1996, ACM / IEEE Computer Society, 0-8186-7563-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
virtual instruction set, control-dominated hardware-software system, retargetable code synthesis, real-time systems, embedded systems, software development, performance estimation, embedded computing, software synthesis, real-time constraints, system synthesis, static scheduling |
31 | Eero Lassila |
A Macro Expansion Approach to Embedded Processor Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 136-142, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
macro expansion approach, embedded processor code generation, embedded special-purpose processors, retargetable assembly-code-level macro expander, program flow analysis, hierarchical macro libraries, compiler writer, assembly language programmer, computer architecture |
31 | Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek |
A retargetable parallel-programming framework for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 39:1-39:18, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
parallel-programming, design-space exploration, Embedded software, multiprocessor system on chip, software generation |
31 | Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang |
Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 117-118, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Max R. de O. Schultz, Alexandre Keunecke Ignácio Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. dos Santos |
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 13-23, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Koen Van Renterghem, Pieter Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu |
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1418-1423, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau |
Retargetable pipeline hazard detection for partially bypassed processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 791-801, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Xinping Zhu, Wei Qin, Sharad Malik |
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(7), pp. 707-716, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | K. Vasanta Lakshmi, Deepak Sreedhar, Easwaran Raman, Priti Shankar |
Integrating a New Cluster Assignment and Scheduling Algorithm into an Experimental Retargetable Code Generation Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2005, 12th International Conference, Goa, India, December 18-21, 2005, Proceedings, pp. 518-527, 2005, Springer, 3-540-30936-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Jean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana |
A retargetable register allocation framework for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 202-210, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
register allocation, embedded processors |
31 | Xinping Zhu, Sharad Malik |
Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1244-1249, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Hoonmo Yang, Moonkey Lee |
Design of a Cycle-Accurate User-Retargetable Instruction-Set Simulator Using Process-Based Scheduling Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIS ![In: Computational and Information Science, First International Symposium, CIS 2004, Shanghai, China, December 16-18, 2004, Proceedings, pp. 266-273, 2004, Springer, 3-540-24127-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Wei Qin, Sharad Malik |
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10556-10561, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Daniel Kästner |
TDL: A Hardware Description Language for Retargetable Postpass Optimizations and Analyses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPCE ![In: Generative Programming and Component Engineering, Second International Conference, GPCE 2003, Erfurt, Germany, September 22-25, 2003, Proceedings, pp. 18-36, 2003, Springer, 3-540-20102-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Wei Qin, Sharad Malik |
Automated synthesis of efficient binary decoders for retargetable software toolkits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 764-769, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
binary decoder, decoding tree, decision tree, instruction set simulator |
31 | Wai Sum Mong, Jianwen Zhu |
A retargetable micro-architecture simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 752-757, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Edward Lank |
A Retargetable Framework for Interactive Diagram Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: 7th International Conference on Document Analysis and Recognition (ICDAR 2003), 2-Volume Set, 3-6 August 2003, Edinburgh, Scotland, UK, pp. 185-189, 2003, IEEE Computer Society, 0-7695-1960-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Guilan Dai, Jinlan Tian, Suqing Zhang, Weidu Jiang, Jun Dai |
Retargetable cross compilation techniques: comparison and analysis of GCC and Zephyr. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 37(6), pp. 38-44, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
compiler infrastructures, zephyr, intermediate representations, GCC, machine descriptions, cross compilation |
31 | Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan, Tai-An Lu |
A Retargetable Embedded In-Circuit Emulation Module for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(4), pp. 28-38, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Frank Wolz, Reiner Kolla |
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 997-1006, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Nagisa Ishiura, Tatsuo Watanabe |
Datapath oriented codesign method of application specific DSPs using retargetable compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 55-58, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Maghsoud Abbaspour, Jianwen Zhu |
Retargetable binary utilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 331-336, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Dmitri Boulytchev, Dmitry Lomov |
An Empirical Study of Retargetable Compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ershov Memorial Conference ![In: Perspectives of System Informatics, 4th International Andrei Ershov Memorial Conference, PSI 2001, Akademgorodok, Novosibirsk, Russia, July 2-6, 2001, Revised Papers, pp. 328-335, 2001, Springer, 3-540-43075-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Rajiv A. Ravindran, Rajat Moona |
Retargetable Program Profiling Using High Level Processor Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2001, 8th International Conference, Hyderabad, India, December, 17-20, 2001, Proceedings, pp. 224-236, 2001, Springer, 3-540-43009-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Stefan Pees, Andreas Hoffmann 0002, Heinrich Meyr |
Retargetable compiled simulation of embedded processors using a machine description language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(4), pp. 815-834, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
HW/SW cosimulation, machine description languages, processor modeling and simulation, system-on-chip, instruction set simulators, compiled simulation, DSP processors |
31 | Subhash Chandra, Rajat Moona |
Retargetable Functional Simulator Using High Level Processor Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 424-429, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Rainer Leupers, Peter Marwedel |
Retargetable generation of code selectors from HDL processor models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 140-144, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe |
Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 1308-1315, 1997, Springer, 3-540-63440-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Jack W. Davidson, Sanjay Jinturkar |
Aggressive Loop Unrolling in a Retargetable Optimizing Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 59-73, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Code improving transformations, Compiler optimizations, Loop transformations, Loop unrolling |
31 | Dawson R. Engler |
VCODE: a Retargetable, Extensible, Very Fast Dynamic Code Generation System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), Philadephia, Pennsylvania, USA, May 21-24, 1996, pp. 160-170, 1996, ACM, 0-89791-795-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Cristina Cifuentes, Vishv M. Malhotra |
Binary Translation: Static, Dynamic, Retargetable? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 1996 International Conference on Software Maintenance (ICSM '96), 4-8 November 1996, Monterey, CA, USA, Proceedings, pp. 340-349, 1996, IEEE Computer Society, 0-8186-7677-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Norman Ramsey, David R. Hanson |
A Retargetable Debugger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), San Francisco, California, USA, June 17-19, 1992, pp. 22-31, 1992, ACM, 0-89791-475-9. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
C, PostScript |
31 | Christopher W. Fraser |
A retargetable compiler for ANSI C. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 26(10), pp. 29-43, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
C |
31 | Philip H. Sweany, Steven J. Beaty |
Post-compaction register assignment in a retargetable compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 107-116, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
31 | Hartmut Feuerhahn |
A data-flow driven resource allocation in a retargetable microcode compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988, pp. 105-107, 1988, ACM/IEEE, 0-8186-1919-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
31 | Philip J. Hatcher, J. W. Tuller |
Efficient retargetable compiler code generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCL ![In: 1988 Internation Conference on Computer Languages, October 9-13, 1988, Miami, Florida, USA, pp. 25-30, 1988, IEEE Computer Society, 0-8186-0874-9. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
31 | Michael A. Howland, Robert A. Mueller, Philip H. Sweany |
Trace scheduling optimization in a retargetable microcode compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 106-114, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
31 | Lothar Nowak |
Graph based retargetable microcode compilation in the MIMOLA design system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 126-132, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
31 | Jack W. Davidson |
A retargetable instruction reorganizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGPLAN Symposium on Compiler Construction ![In: Proceedings of the 1986 SIGPLAN Symposium on Compiler Construction, Palo Alto, California, USA, June 25-27, 1986, pp. 234-241, 1986, ACM, 0-89791-197-0. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
31 | Vishv M. Malhotra, Sanjeev Kumar |
Automatic Retargetable Code Generation: A New Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: Foundations of Software Technology and Theoretical Computer Science, Sixth Conference, New Delhi, India, December 18-20, 1986, Proceedings, pp. 57-80, 1986, Springer, 3-540-17179-7. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
24 | Dmitri Boulytchev |
BURS-Based Instruction Set Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ershov Memorial Conference ![In: Perspectives of Systems Informatics, 6th International Andrei Ershov Memorial Conference, PSI 2006, Novosibirsk, Russia, June 27-30, 2006. Revised Papers, pp. 431-437, 2006, Springer, 978-3-540-70880-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun |
C Compiler Retargeting Based on Instruction Semantics Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1150-1155, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Gunnar Braun, Achim Nohl, Andreas Hoffmann 0002, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr |
A universal technique for fast and flexible instruction-set architecture simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1625-1639, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Jens Braunes, Steffen Köhler, Rainer G. Spallek |
RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Organic and Pervasive Computing - ARCS 2004, International Conference on Architecture of Computing Systems, Augsburg, Germany, March 23-26, 2004, Proceedings, pp. 156-166, 2004, Springer, 3-540-21238-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Christoph W. Keßler, Andrzej Bednarski |
Optimal integrated code generation for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 102-111, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection |
24 | Sungjoon Jung, Yunheung Paek |
The very portable optimizer for digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 84-92, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Norman Ramsey, Mary F. Fernandez |
Specifying Representations of Machine Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 19(3), pp. 492-524, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
encoding, decoding, compiler generation, relocation, object code, machine description, machine code |
24 | Jie Gong, Daniel D. Gajski, Alexandru Nicolau |
Performance evaluation for application-specific architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(4), pp. 483-490, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
24 | Jack W. Davidson, David B. Whalley |
Ease: An Environment for Architecture Study and Experimentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems, University of Colorado, Boulder, Colorado, USA, May 22-25, 1990, pp. 259-260, 1990, ACM, 0-89791-359-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
20 | Chao Wang 0003, Huizhen Zhang, Xuehai Zhou, Jinsong Ji, Aili Wang 0003 |
Tool Chain Support with Dynamic Profiling for RISP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2011, Busan, Korea, 26-28 May, 2011, pp. 155-160, 2011, IEEE Computer Society, 978-1-4577-0391-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
reconfigurable instruction set processor, code mapping, retargetable compilation, dynamic profiling |
20 | Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado |
An open-source binary utility generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 27:1-27:17, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Platform debugging, retargetable tools, TLM |
20 | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau |
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 123-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers |
20 | Prabhat Mishra 0001, Aviral Shrivastava, Nikil D. Dutt |
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(3), pp. 626-658, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable architecture, design space exploration, Architecture description language, embedded processor, retargetable compilation |
20 | Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini |
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 167-172, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping |
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