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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 272 occurrences of 155 keywords
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Results
Found 211 publication records. Showing 211 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
68 | André Seznec, François Bodin |
Skewed-associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE ![In: PARLE '93, Parallel Architectures and Languages Europe, 5th International PARLE Conference, Munich, Germany, June 14-17, 1993, Proceedings, pp. 304-316, 1993, Springer, 3-540-56891-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
skewed-associative cache, cache, microprocessors, set-associative cache |
63 | Brannon Batson, T. N. Vijaykumar |
Reactive-Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 49-60, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
57 | Jia-Jhe Li, Yuan-Shin Hwang |
Snug set-associative caches: reducing leakage power while improving performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 345-350, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
leakage power, set-associative caches |
56 | Yuguang Wu, Richard R. Muntz |
Stack Evaluation of Arbitrary Set-Associative Multiprocessor Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(9), pp. 930-942, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
coherence by invalidation, stack evaluation, simulation, Cache memory, set-associative |
55 | Mohsen Sharifi, Behrouz Zolfaghari |
YAARC: yet another approach to further reducing the rate of conflict misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 44(1), pp. 24-40, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Skewed associative cache, YAARC cache, Hit rate, Cache, Conflict misses |
55 | Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar |
A way-halting cache for low-energy high-performance systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 2(1), pp. 34-54, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, low power, Cache, dynamic optimization, low energy |
49 | Peter Sanders 0001 |
Accessing Multiple Sequences Through Set Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 26th International Colloquium, ICALP'99, Prague, Czech Republic, July 11-15, 1999, Proceedings, pp. 655-664, 1999, Springer, 3-540-66224-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multi merge, memory hierarchy, external memory algorithm, Set associative cache |
49 | Rabin A. Sugumar, Santosh G. Abraham |
Set-Associative Cache Simulation Using Generalized Binomial Trees ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 13(1), pp. 32-56, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
all-associativity simulation, binomial tree, inclusion properties, single-pass simulation, trace-driven simulation, cache modeling, set-associative caches |
48 | James C. Browne, Kevin Kane, Hongxia Tian |
An Associative Broadcast Based Coordination Model for Distributed Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COORDINATION ![In: Coordination Models and Languages, 5th International Conference, COORDINATION 2002, YORK, UK, April 8-11, 2002, Proceedings, pp. 96-110, 2002, Springer, 3-540-43410-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Prasanna Palsodkar, Amol Y. Deshmukh, Preeti R. Bajaj, Avinash G. Keskar |
An Approach for Four Way Set Associative Multilevel CMOS Cache Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 11th International Conference, KES 2007, XVII Italian Workshop on Neural Networks, Vietri sul Mare, Italy, September 12-14, 2007. Proceedings, Part I, pp. 740-746, 2007, Springer, 978-3-540-74817-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Masamichi Takagi, Kei Hiraki |
Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004, pp. 20-30, 2004, ACM, 1-58113-839-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cache memory, replacement algorithm, set-associative cache |
41 | Rui Min, Wen-Ben Jone, Yiming Hu |
Location cache: a low-power L2 cache system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 120-125, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
L1/L2 caches, data location, power, TLB, set-associative caches |
41 | Henk L. Muller, Paul W. A. Stallard, David H. D. Warren |
The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 41-49, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios |
38 | Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi |
Fault Tolerant and Low Energy Write-Back Heterogeneous Set Associative Cache for DSM Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Forth International Conference on Availability, Reliability and Security, ARES 2009, March 16-19, 2009, Fukuoka, Japan, pp. 448-453, 2009, IEEE Computer Society, 978-1-4244-3572-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
37 | Michael D. Powell, Amit Agarwal 0001, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy 0001 |
Reducing set-associative cache energy via way-prediction and selective direct-mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 54-65, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar |
A way-halting cache for low-energy high-performance systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 126-131, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low power techniques, cache design |
34 | S. Subha |
A Set Associative Cache Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Seventh International Conference on Information Technology: New Generations, ITNG 2010, Las Vegas, Nevada, USA, 12-14 April 2010, pp. 1316-1317, 2010, IEEE Computer Society, 978-0-7695-3984-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Set Associative mapping, XOR mapping |
34 | John Stuart Harper, Darren J. Kerbyson, Graham R. Nudd |
Analytical Modeling of Set-Associative Cache Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(10), pp. 1009-1024, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
performance evaluation, analytical modeling, data locality, Cache modeling, set-associative, cache interference |
34 | Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu |
Efficient Stack Simulation for Set-Associative Virtual Address Cache with Real Tags. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(5), pp. 719-723, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Stack simulation, V/R-type cache, pseudonym, set-associative cache, synonym, miss ratio |
34 | Robert Yung |
Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 178-190, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor |
31 | Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen 0001, Hai Li 0001 |
Tolerating process variations in large, set-associative caches: The buddy cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(2), pp. 8:1-8:34, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
caches, Processor architectures, fault recovery, memory structures |
31 | Yuan-Shin Hwang, Jia-Jhe Li |
Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(1), pp. 6, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Caches, leakage power, drowsy caches, cache decay |
30 | S. Subha |
A Set Associative Cache Model with Energy Saving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 1249-1250, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Cache, Energy Savings |
30 | Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone |
Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 183-188, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Megalingam Rajesh Kannan, K. B. Deepu, Joseph P. Iype, Ravishankar Parthasarathy, Popuri Gautham |
Power Consumption Analysis of Direct, Set Associative and Phased Set Associative Cache Organizations in Alpha AXP 21064 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BAIP ![In: Information Processing and Management - International Conference on Recent Trends in Business Administration and Information Processing, BAIP 2010, Trivandrum, Kerala, India, March 26-27, 2010. Proceedings, pp. 114-119, 2010, Springer, 978-3-642-12213-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
30 | Seiichiro Fujii, Toshinori Sato |
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings, pp. 217-226, 2004, Springer, 3-540-22906-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Randall T. White, Christopher A. Healy, David B. Whalley, Frank Mueller 0001, Marion G. Harmon |
Timing Analysis for Data Caches and Set-Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 3rd IEEE Real-Time Technology and Applications Symposium, RTAS '97, Montreal, Canada, June 9-11, 1997, pp. 192-202, 1997, IEEE Computer Society, 0-8186-8016-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Hamid R. Zarandi, Seyed Ghassem Miremadi |
Hierarchical Multiple Associative Mapping in Cache Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 12th IEEE International Conference on the Engineering of Computer-Based Systems (ECBS 2005), 4-7 April 2005, Greenbelt, MD, USA, pp. 95-101, 2005, IEEE Computer Society, 0-7695-2308-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Jung-Wook Park, Cheong-Ghil Kim, Jung-Hoon Lee, Shin-Dug Kim |
An energy efficient cache memory architecture for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), Nicosia, Cyprus, March 14-17, 2004, pp. 884-890, 2004, ACM, 1-58113-812-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
selective way access, skewed associativity, embedded system, memory hierarchy, low power cache |
29 | Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim |
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 42-47, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Sangmin Seo, Jaejin Lee, Zehra Sura |
Design and implementation of software-managed caches for multicores with local memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 55-66, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Rui Min, Yiming Hu |
Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1191-1201, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Novel memory architectures, cache, memory systems, TLB, performance enhancement |
28 | Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John |
Modeling and Analysis of The Difference-Bit Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 140-145, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hit access time, cache mapping strategies*, Cache memory, critical path |
28 | Rabin A. Sugumar, Santosh G. Abraham |
Efficient Simulation of Caches under Optimal Replacement with Applications to Miss Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Santa Clara, California, USA, May 10-14, 1993, pp. 24-35, 1993, ACM, 0-89791-580-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
27 | Yoav Etsion, Dror G. Feitelson |
L1 Cache Filtering Through Random Selection of Memory References. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 235-244, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Jih-Kwon Peir, Yongjoon Lee, Windsor W. Hsu |
Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 240-250, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Jaume Abella 0001, Antonio González 0001 |
Heterogeneous way-size cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006, Cairns, Queensland, Australia, June 28 - July 01, 2006, pp. 239-248, 2006, ACM, 1-59593-282-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive, low power, cache memories, set-associative |
27 | Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe |
Cache modeling for real-time software: beyond direct mapped instruction caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), December 4-6, 1996, Washington, DC, USA, pp. 254-263, 1996, IEEE Computer Society, 0-8186-7689-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
direct mapped instruction caches, worst case timing analysis, cache hits, set associative instruction caches, unified caches, cinderella, research, integer-linear-programming, worst case execution time, data caches, cache storage, design tool, memory performance, cache misses, real-time software, tight bound, cache modeling, hardware system |
26 | Mainak Chaudhuri |
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 401-412, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
chip-multiprocessor, replacement policy, last-level cache |
23 | Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras |
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Transactions on High-Performance Embedded Architectures and Compilers II, pp. 4-22, 2009, Springer, 978-3-642-00903-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras |
Applying Decay to Reduce Dynamic Power in Set-Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 38-53, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke |
Compiler-managed partitioned data caches for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 237-247, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hardware/software co-managed cache, instruction-driven cache management, partitioned cache, low-power, embedded processor |
23 | Moinuddin K. Qureshi, David Thompson, Yale N. Patt |
The V-Way Cache: Demand Based Associativity via Global Replacement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 544-555, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Sebastian Altmeyer, Claire Maiza, Jan Reineke 0001 |
Resilience analysis: tightening the CRPD bound for set-associative caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010, pp. 153-162, 2010, ACM, 978-1-60558-953-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cache-related preemption delay, lru caches, timing analysis |
22 | Mrinmoy Ghosh, Emre Özer 0001, Simon Ford, Stuart Biles, Hsien-Hsin S. Lee |
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 165-170, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power, bloom filter |
22 | Clément Ballabriga, Hugues Cassé, Pascal Sainrat |
An improved approach for set-associative instruction cache partial analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 360-367, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
WCET computation, partial cache analysis, partial static analysis, abstract interpretation, COTS, instruction cache |
22 | SangKyun Yun |
Hardware-Based IP Lookup Using n-Way Set Associative Memory and LPM Comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 406-414, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Jaume Abella 0001, Antonio González 0001 |
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Stefanos Kaxiras, Georgios Keramidas |
IPStash: a set-associative memory approach for efficient IP-lookup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 13-17 March 2005, Miami, FL, USA, pp. 992-1001, 2005, IEEE, 0-7803-8968-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami |
A Low Energy Set-Associative I-Cache with Extended BTB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 187-, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Chuanjun Zhang |
An efficient direct mapped instruction cache for application-specific embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 45-50, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
efficient cache design, instruction cache, low power cache |
22 | Jun Xu 0014, Mukesh Singhal |
Cost-Effective Flow Table Designs for High-Speed Routers: Architecture and Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(9), pp. 1089-1099, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Flow table, performance analysis, router architecture, universal hashing |
21 | J. Adam Butts, Gurindar S. Sohi |
Use-Based Register Caching with Decoupled Indexing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 302-313, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Stefanos Kaxiras, Georgios Keramidas |
IPStash: a Power-Efficient Memory Architecture for IP-lookup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 361-372, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
IP |
20 | André Seznec |
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 924-927, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiple page size, skewed associativity, TLB |
19 | Fong Pong, Nian-Feng Tzeng |
HaRP: Rapid Packet Classification via Hashing Round-Down Prefixes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 22(7), pp. 1105-1119, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
filter data sets, incremental rule updates, IP prefixes, set-associative hash tables, tuple space search, decision trees, hashing functions, routers, packet classification, Classification rules |
19 | Salvador Petit, Julio Sahuquillo, Jose M. Such, David R. Kaeli |
Exploiting temporal locality in drowsy cache policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 371-377, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
drowsy cache policies, reuse information, low-power, temporal locality, set-associative caches |
19 | Mark D. Hill, Alan Jay Smith |
Evaluating Associativity in CPU Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(12), pp. 1612-1630, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
CPU caches, cache miss ratio, forest simulation, all-associativity simulation, stack simulation, associativity, buffer storage, content-addressable storage, direct-mapped, set-associative |
19 | Kimming So, Rudolph N. Rechtschaffen |
Cache Operations by MRU Change. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(6), pp. 700-709, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
MRU change, most recently used, prefetch algorithms, performance evaluation, performance, storage management, CPU, content-addressable storage, virtual storage, replacement algorithms, memory access, cache simulation, set associative caches |
19 | James E. Smith, James R. Goodman |
Instruction Cache Replacement Policies and Organizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(3), pp. 234-241, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
fully associative, loop model, Cache memories, replacement algorithms, memory organization, direct-mapped, set-associative |
17 | Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosenberg, Charles C. Weems |
Using the Compiler to Improve Cache Replacement Decisions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 199-208, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Hongwei Zhou, Chengyi Zhang, Mingxuan Zhang |
Improved Way Prediction Policy for Low-Energy Instruction Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 425-436, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Jih-Kwon Peir, Windsor W. Hsu, Honesty C. Young, Shauchi Ong |
Improving Cache Performance with Balanced Tag and Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VII Proceedings - Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, USA, October 1-5, 1996., pp. 268-278, 1996, ACM Press, 0-89791-767-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
15 | Chuanjun Zhang, Frank Vahid, Walid A. Najjar |
A highly configurable cache for low energy embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(2), pp. 363-387, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning |
15 | Wei Song 0002, Zihan Xue, Jinchi Han, Zhenzhen Li, Peng Liu 0005 |
Randomizing Set-Associative Caches Against Conflict-Based Cache Side-Channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 73(4), pp. 1019-1033, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Michael A. Bender, Rathish Das, Martin Farach-Colton, Guido Tagliavini |
An Associativity Threshold Phenomenon in Set-Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2304.04954, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Michael A. Bender, Rathish Das, Martin Farach-Colton, Guido Tagliavini |
An Associativity Threshold Phenomenon in Set-Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: Proceedings of the 35th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA 2023, Orlando, FL, USA, June 17-19, 2023, pp. 117-127, 2023, ACM, 978-1-4503-9545-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu |
ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022, pp. 86:1-86:9, 2022, ACM, 978-1-4503-9217-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
15 | Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen |
Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 1799-1802, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
15 | Wei Zhang 0173, Nan Guan, Lei Ju 0001, Yue Tang 0001, Weichen Liu, Zhiping Jia |
Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10), pp. 2333-2346, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar |
Bounding Cache Persistence Reload Overheads for Set-Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 26th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2020, Gangnueng, Korea (South), August 19-21, 2020, pp. 1-10, 2020, IEEE, 978-1-7281-4403-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
15 | Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti |
Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(12), pp. 1950203:1-1950203:25, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
15 | Payman Behnam, Arjun Pal Chowdhury, Mahdi Nazm Bojnordi |
R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 36th IEEE International Conference on Computer Design, ICCD 2018, Orlando, FL, USA, October 7-10, 2018, pp. 423-430, 2018, IEEE Computer Society, 978-1-5386-8477-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
15 | Wenming Li, Lingjun Fan, Zihou Wang, Xiaochun Ye, Da Wang, Hao Zhang 0009, Liang Zhang, Dongrui Fan, Xianghui Xie 0001 |
Thread ID based power reduction mechanism for multi-thread shared set-associative caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IGSC ![In: Sixth International Green and Sustainable Computing Conference, IGSC 2015, Las Vegas, NV, USA, December 14-16, 2015, pp. 1-4, 2015, IEEE Computer Society, 978-1-5090-0172-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
15 | Wei Zhang 0044, Hang Zhang 0031, John C. Lach |
Reducing dynamic energy of set-associative L1 instruction cache by early tag lookup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 2015, pp. 49-54, 2015, IEEE, 978-1-4673-8009-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
15 | Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors |
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, pp. 1-4, 2014, European Design and Automation Association, 978-3-9815370-2-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
15 | Pavlos Maniotis, D. Fitsios, George T. Kanellos, Nikos Pleros |
A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2014, San Francisco, CA, USA, March 9-13, 2014, pp. 1-3, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
15 | Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors |
Speculative tag access for reduced energy dissipation in set-associative L1 data caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013, pp. 302-308, 2013, IEEE Computer Society, 978-1-4799-2987-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
15 | Jiongyao Ye, Hongfeng Ding, Yingtao Hu, Takahiro Watanabe |
A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Process. ![In: J. Inf. Process. 20(1), pp. 26-36, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Marjan Gusev, Sasko Ristov |
Performance Gains and Drawbacks using Set Associative Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Next Gener. Inf. Technol. ![In: J. Next Gener. Inf. Technol. 3(3), pp. 87-98, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | C. J. Janraj, T. Venkata Kalyan, Tripti S. Warrier, Madhu Mutyam |
Way Sharing Set Associative Cache Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 25th International Conference on VLSI Design, Hyderabad, India, January 7-11, 2012, pp. 251-256, 2012, IEEE Computer Society, 978-1-4673-0438-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
15 | Stefano Di Carlo, Paolo Prinetto, Alessandro Savino |
Software-Based Self-Test of Set-Associative Cache Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 60(7), pp. 1030-1044, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem |
Advanced hashing schemes for packet forwarding using set associative memory architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 71(1), pp. 1-15, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Sungjae Lee, Jin-Ku Kang, Inhwan Lee |
Way-lookup buffer for low-power set-associative cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 8(23), pp. 1961-1966, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
15 | Yun Liang 0001, Tulika Mitra |
Improved procedure placement for set associative caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2010, Scottsdale, AZ, USA, October 24-29, 2010, pp. 147-156, 2010, ACM, 978-1-60558-903-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
15 | Benjamin Lesage, Damien Hardy, Isabelle Puaut |
WCET Analysis of Multi-Level Set-Associative Data Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCET ![In: 9th Intl. Workshop on Worst-Case Execution Time Analysis, WCET 2009, Dublin, Ireland, July 1-3, 2009, 2009, Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
15 | Claire Burguière, Jan Reineke 0001, Sebastian Altmeyer |
Cache-Related Preemption Delay Computation for Set-Associative Caches - Pitfalls and Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCET ![In: 9th Intl. Workshop on Worst-Case Execution Time Analysis, WCET 2009, Dublin, Ireland, July 1-3, 2009, 2009, Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
15 | Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem |
Progressive hashing for packet processing using set associative memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2009, Princeton, New Jersey, USA, October 19-20, 2009, pp. 153-162, 2009, ACM, 978-1-60558-630-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Jonathan R. Haigh, Lawrence T. Clark |
High performance set associative translation lookaside buffers for low power microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 41(4), pp. 509-523, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Damien Hardy, Isabelle Puaut |
WCET analysis of multi-level set-associative instruction caches ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/0807.0993, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
15 | Clément Ballabriga, Hugues Cassé |
Improving the First-Miss Computation in Set-Associative Instruction Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 20th Euromicro Conference on Real-Time Systems, ECRTS 2008, 2-4 July 2008, Prague, Czech Republic, Proceedings, pp. 341-350, 2008, IEEE Computer Society, 978-0-7695-3298-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino |
Applying March Tests to K-Way Set-Associative Cache Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008, pp. 77-83, 2008, IEEE Computer Society, 978-0-7695-3150-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cache memories, memory test, march test |
15 | Damien Hardy, Isabelle Puaut |
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 29th IEEE Real-Time Systems Symposium, RTSS 2008, Barcelona, Spain, 30 November - 3 December 2008, pp. 456-466, 2008, IEEE Computer Society, 978-0-7695-3477-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Chih-Hui Ting, Juinn-Dar Huang, Yu-Hsiang Kao |
Cycle-time-aware sequential way-access set-associative cache for low energy consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 854-857, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Biju K. Raveendran, T. S. B. Sudarshan, Avinash Patil, Komal B. Randive, S. Gurunarayanan 0001 |
An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2007 International Conference on Embedded Systems & Applications, USA 2007, June 25-28, 2007, Las Vegas, Nevada, USA, pp. 188-196, 2007, CSREA Press, 1-60132-052-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
15 | Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau |
Using a Way Cache to Improve Performance of Set-Associative Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High-Performance Computing - 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers, pp. 93-104, 2005, Springer, 978-3-540-77703-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | José Luis Hamkalo, Andrés Djordjalian, Bruno Cernuschi-Frías |
A Shared-Way Set Associative On-Chip Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Their Appl. ![In: Int. J. Comput. Their Appl. 11(4), pp. 224-233, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
15 | James D. Fix |
The set-associative cache performance of search trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Fourteenth Annual ACM-SIAM Symposium on Discrete Algorithms, January 12-14, 2003, Baltimore, Maryland, USA., pp. 565-572, 2003, ACM/SIAM, 0-89871-538-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
15 | Perng-Fei Lin, James B. Kuo |
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(10), pp. 1307-1317, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Perng-Fei Lin, James B. Kuo |
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 36(4), pp. 666-675, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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