Search results for "settling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Fule Li, Zhihua Wang 0001, Dongmei Li	An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters.	ISCAS	2007	DBLP DOI BibTeX RDF
76	Hamed Aminzadeh, Mohammad Danaie	Systematic design of two-stage operational amplifiers based on settling time and open-loop constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	frequency compensation, stability, design methodology, operational amplifiers, switched-capacitor circuits, settling time
68	Joe Kelly, Dean Nicholson, Edwin Lowery, Victor Grothen	Light-Enhanced FET Switch Improves ATE RF Power Settling.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	FET, RF switch, power settling, HVM, high-volume manufacturing, ATE, test time, settling time
61	Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi	Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling Model.	VLSI Design	2007	DBLP DOI BibTeX RDF
50	Amal Kumar Kundu, Subho Chatterjee, Tarun Kanti Bhattacharyya	A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation.	VLSI Design	2008	DBLP DOI BibTeX RDF
50	Barbara F. Csima	Comparing C.E. Sets Based on Their Settling Times.	CiE	2007	DBLP DOI BibTeX RDF
50	David I. Bergman, Bryan C. Waltrip	Low thermal error sampling comparator for accurate settling measurements.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
50	Jie Yan, Randall L. Geiger	Fast-settling CMOS operational amplifiers with negative conductance voltage gain enhancement.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
48	Marco Zuniga, Bhaskar Krishnamachari	Optimal Transmission Radius for Flooding in Large Scale Sensor Networks.	Clust. Comput.	2005	DBLP DOI BibTeX RDF	wireless sensor networks, MAC, flooding, settling time
44	Angel Abusleme, Boris Murmann	Predictive control algorithm for phase-locked loops.	ISCAS	2008	DBLP DOI BibTeX RDF
39	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.	PATMOS	2008	DBLP DOI BibTeX RDF	CMOS analog integrated circuits, frequency compensation, operational amplifiers, transient response
39	Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo	Settling Time Minimization of Operational Amplifiers.	PATMOS	2007	DBLP DOI BibTeX RDF
39	Gianluca Giustolisi	Two-Stage OTA Design Based on Settling-Time Constraints.	ISCAS	2007	DBLP DOI BibTeX RDF
39	Mohammad Yavari, Omid Shoaei	Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications.	ISLPED	2003	DBLP DOI BibTeX RDF	cascode compensation, class AB, switched-capacitor circuits, operational transconductance amplifiers
39	José M. de la Rosa 0001, Maria Belen Pérez-Verdú, Fernando Medeiro, Rocío del Río, Ángel Rodríguez-Vázquez	Effect of non-linear settling error on the harmonic distortion of fully-differential switched-current bandpass Sigma-Delta modulators.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
37	Zhen Qi, John E. McInroy	Improved Image Based Visual Servoing with Parallel Robot.	J. Intell. Robotic Syst.	2008	DBLP DOI BibTeX RDF	Position regulation, Image Jacobian, Adaptive supervisory fuzzy logic controller, Fuzzy scaling matrix, Parallel robot, Settling time
37	Wen-Jer Wu, Chuan Yi Tang	Memory test time reduction by interconnecting test items.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	memory test time reduction, test items interconnection, initialization sequences, verification sequences, signal settling time, interconnection problem, rural Chinese postman problem, integer linear programming model, successive ILP models, graph theory, constraints, linear programming, integrated circuit testing, integer programming, iterations, NP-hard problem, integrated memory circuits
37	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
37	Minsoo Ryu, Seongsoo Hong, Manas Saksena	Streamlining real-time controller design: From performance specifications to end-to-end timing constraints.	IEEE Real Time Technology and Applications Symposium	1997	DBLP DOI BibTeX RDF	real-time controller design, performance specifications, end-to-end timing constraints, control theoretic approach, schedulability constraint, control output responses, steady state error maximum overshoot, rise time, loop processing periods, input-to-output latency, heuristic optimization algorithm, embedded real-time controller, period calibration method, real-time systems, performance requirements, control performance, real-time control system, temporal requirements, settling time
33	Juan Pablo Alegre, Belén Calvo, Santiago Celma	A fast compact CMOS feedforward automatic gain control circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
33	Haider A. F. Mohamed, En Lau Lau, Soo Siang Yang, Mahmoud Moghavvemi	Fuzzy-SMC-PI Flux and Speed Control for Induction Motors.	RAM	2008	DBLP DOI BibTeX RDF
33	Chao Yang 0030, Andrew J. Mason	Zero-IF VGA with novel offset cancellation.	ISCAS	2006	DBLP DOI BibTeX RDF
33	Win Chaivipas, Akira Matsuzawa, Philipus Chandra Oh	Feedforward compensation technique for all digital phase locked loop based synthesizers.	ISCAS	2006	DBLP DOI BibTeX RDF
33	Salvatore Levantino, Luca Romanò, Carlo Samori, Andrea L. Lacaita	Fast-switching analog PLL with finite-impulse response.	ISCAS (4)	2004	DBLP DOI BibTeX RDF
28	B. Straka, Hans A. R. Manhaeve, J. Brenkus, Stefaan Kerckenaere	Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality.	DATE	2008	DBLP DOI BibTeX RDF
28	Hsuan-Yu Marcus Pan, Lawrence E. Larson	Improved Dynamic Model of Fast-Settling Linear-in-dB Automatic Gain Control Circuit.	ISCAS	2007	DBLP DOI BibTeX RDF
28	Josh Carnes, Un-Ku Moon	The effect of switch resistance on pipelined ADC MDAC settling time.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Haibin Huang, Ezz I. El-Masry	A fast settling CMOS operational amplifier.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
28	Yiwu Tang, Mohammed Ismail 0001, Steven Bibyk	A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
28	Ljubomir T. Grujic, Zoran R. Novakovic	Robot control: Tracking with the required settling time.	J. Intell. Robotic Syst.	1991	DBLP DOI BibTeX RDF	Tracking, robot control, nonlinear systems
26	Mustafa Keskin, Nurcan Keskin	A Tuning Technique for Switched-Capacitor Circuits.	AHS	2006	DBLP DOI BibTeX RDF	Switched capacitor, settling, on-resistance, switch, transfer function, tuning, charge
22	Zeljko Ignjatovic, Yang Zhang, Mark F. Bocko	CMOS image sensor readout employing in-pixel transistor current sensing.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Shuilong Huang, Zhihua Wang	A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Mohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez	Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation.	DATE	2006	DBLP DOI BibTeX RDF
22	G. Reza Chaji, Arokia Nathan	High-precision, fast current source for large-area current-programmed a-Si flat panels.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Yi-Da Wu, Chang-Ming Lai, Chih-Yuan Chou, Po-Chiun Huang	An OPLL-DDS based frequency synthesizer for DCS-1800 receiver.	ISCAS	2006	DBLP DOI BibTeX RDF
22	H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler	A rail to rail, slew-boosted pre-charge buffer.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Tord Johnson, Johnny Holmberg	Nonlinear state-space model of charge-pump based frequency synthesizers.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
22	Eduardo Gómez-Ramírez, Armando Chávez-Placencia	Tuning of Fuzzy Controllers.	MICAI	2004	DBLP DOI BibTeX RDF
22	George Jie Yuan, Nabil H. Farhat	A compensation-based optimization methodology for gain-boosted opamp.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
22	Romero Tavares, Bruno Vaz, João Goes, Nuno F. Paulino, Adolfo Steiger-Garção	Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	N. Christoffers, Rainer Kokozinski, Stephan Kolnsberg, Bedrich J. Hosticka	High loop-filter-order ΣΔ-fractional-n frequency synthesizers for use in frequency-hopping-spread-spectrum communication-systems.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
22	Jozef Adut, José Silva-Martínez	Cascode transconductance amplifiers for HF switched-capacitor applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	Marco Zuniga, Bhaskar Krishnamachari	Optimal Transmission Radius for Flooding in Large Scale Sensor Networks.	ICDCS Workshops	2003	DBLP DOI BibTeX RDF
22	I. Robandi	An improvement of frequency performance in a power system optimization via controller parameter design using genetic algorithm.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
22	Hoi Lee, Philip K. T. Mok	A CMOS current-mirror amplifier with compact slew rate enhancement circuit for large capacitive load applications.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	Xuelei Qi, Chen Li, Wei Ni, Hong-Jun Ma	A novel adaptive fuzzy prescribed performance congestion control for network systems with predefined settling time.	Neural Comput. Appl.	2024	DBLP DOI BibTeX RDF
17	Xing Li, Liming Wang, Guomin Zhong, Mingxuan Sun	Fixed-time convergent RNNs with logarithmic settling time for time-variant quadratic programming solving with application to repetitive motion planning.	Neural Comput. Appl.	2024	DBLP DOI BibTeX RDF
17	Heejin Yang, Ji-Hwan Seol, Rohit Rothe, Zichen Fan, Qirui Zhang 0001, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester	A 1.5-μW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
17	Hyunjin Kim, ChangHun Park, Inho Park, Taehyeong Park, Seungwoo Park, Chulwoo Kim	A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
17	A. Ghaemnia, M. B. Ghaznavi-Ghoushchi	QD-PFD: Quasi Dynamic Dead-Zone/Blind-Zone Free PFD With 23 nW-38 μW for 2 MHz-5 GHz Range and 150-ns Settling Time PLL Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
17	Zhi Feng, Guoqiang Hu 0001, Xiwang Dong, Jinhu Lü	Settling-Time Estimation for Finite-Time Connectivity-Preserving Rendezvous of Networked Uncertain Euler-Lagrange Systems.	IEEE Trans. Syst. Man Cybern. Syst.	2024	DBLP DOI BibTeX RDF
17	Haobin Jiang, Ziluo Ding, Zongqing Lu	Settling Decentralized Multi-Agent Coordinated Exploration by Novelty Sharing.	CoRR	2024	DBLP DOI BibTeX RDF
17	Sina Borzooei, Leonardo F. S. Scabini, Gisele Helena Barboni Miranda, Saba Daneshgar, Lukas Deblieck, Piet De Langhe, Odemir Martinez Bruno, Bernard De Baets, Ingmar Nopens, Elena Torfs	Prediction of Activated Sludge Settling Characteristics from Microscopy Images with Deep Convolutional Neural Networks and Transfer Learning.	CoRR	2024	DBLP DOI BibTeX RDF
17	Frederick V. Qiu, S. Matthew Weinberg	Settling the Communication Complexity of VCG-based Mechanisms for all Approximation Guarantees.	CoRR	2024	DBLP DOI BibTeX RDF
17	Mahsa Derakhshan, Emily Ryu, S. Matthew Weinberg, Eric Xue 0001	Settling the Competition Complexity of Additive Buyers over Independent Items.	CoRR	2024	DBLP DOI BibTeX RDF
17	Andrew Draganov, David Saulpic, Chris Schwiegelshohn	Settling Time vs. Accuracy Tradeoffs for Clustering Big Data.	CoRR	2024	DBLP DOI BibTeX RDF
17	Yancheng Yan, Jianhui Wang, Jiarui Liu, C. L. Philip Chen, Zhi Liu 0001, Chunliang Zhang	Adaptive fuzzy prescribed settling time consensus control for multi-agent systems with input hysteresis via dynamic event-triggered mechanism.	Commun. Nonlinear Sci. Numer. Simul.	2024	DBLP DOI BibTeX RDF
17	Haobin Jiang, Ziluo Ding, Zongqing Lu	Settling Decentralized Multi-Agent Coordinated Exploration by Novelty Sharing.	AAAI	2024	DBLP DOI BibTeX RDF
17	Zeeshan Ali, Pallavi Paliwal, Phani Raj, Deepak Anand, Debasattam Pal, Shalabh Gupta	Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs).	IEEE Control. Syst. Lett.	2023	DBLP DOI BibTeX RDF
17	Okure Udo Obot, Faith-Michael E. Uzoka, Anietie E. John, Samuel S. Udoh	Soft-computing method for settling land disputes cases based on text similarity.	Int. J. Bus. Inf. Syst.	2023	DBLP DOI BibTeX RDF
17	Wang Xue, Yushun Guo, Yuliang Zhang, Chang Shu	Exact Settling Performance Design for CMOS Three-Stage Nested-Miller-Compensated Amplifiers.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
17	Stephanie Esmeralda Velázquez Pérez, Eric Campos-Cantón, Guillermo Huerta-Cuéllar, Héctor Eduardo Gilardi Velázquez	Bidimensional Deterministic Model for Diffusion and Settling of Particles.	Axioms	2023	DBLP DOI BibTeX RDF
17	Fanchao Kong, Cheng Hu 0005, Leimin Wang, Tingwen Huang	Fixed-Time Stabilization of Leakage-Delayed Neural Networks Modeled by Delayed Filippov Systems: Leakage-Delay-Dependent Settling-Time.	IEEE Trans. Netw. Sci. Eng.	2023	DBLP DOI BibTeX RDF
17	Zehao Zhang, Shiheng Yang, Yueduo Liu, Zihao Zhu, Jiahui Lin, Rongxin Bao, Tailong Xu, Zhizhan Yang, Mingkang Zhang, Jiaxin Liu, Xiong Zhou, Jun Yin 0001, Pui-In Mak, Qiang Li 0021	On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
17	Yury Orlov 0001, Ramón I. Verdés Kairuz	Autonomous Output Feedback Stabilization With Prescribed Settling-Time Bound.	IEEE Trans. Autom. Control.	2023	DBLP DOI BibTeX RDF
17	Tsorng-Whay Pan, Shang-Huan Chiu	A DLM/FD method for simulating balls settling in Oldroyd-B viscoelastic fluids.	J. Comput. Phys.	2023	DBLP DOI BibTeX RDF
17	Timothy Sun	Settling the genus of the n-prism.	Eur. J. Comb.	2023	DBLP DOI BibTeX RDF
17	Chaoqun Guo, Jiangping Hu	Fixed-Time Stabilization of High-Order Uncertain Nonlinear Systems: Output Feedback Control Design and Settling Time Analysis.	J. Syst. Sci. Complex.	2023	DBLP DOI BibTeX RDF
17	Abdul Muqueem, Shanky Saxena, Govind Singh Patel	An Ultra-Low-Power C-Band FMCW Transmitter Using a Fast Settling Fractional-N DPLL and Ring-Based Pulse Injection Locking Oscillator.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
17	Leimin Wang, Xingxing Tan, Qingyi Wang, Junhao Hu	Multiple finite-time synchronization and settling-time estimation of delayed competitive neural networks.	Neurocomputing	2023	DBLP DOI BibTeX RDF
17	Warren Singh, Timothy Sun	Settling the Nonorientable Genus of the Nearly Complete Bipartite Graphs.	Graphs Comb.	2023	DBLP DOI BibTeX RDF
17	Hadi Pahlavanzadeh, Mohammad Azim Karami	A low settling time switching scheme for SAR ADCs with reset-free regenerative comparator.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
17	Aris Filos-Ratsikas, Panagiotis Kanellopoulos, Alexandros A. Voudouris, Rongsen Zhang	Settling the Distortion of Distributed Facility Location.	CoRR	2023	DBLP DOI BibTeX RDF
17	Zihan Zhang, Yuxin Chen 0002, Jason D. Lee, Simon S. Du	Settling the Sample Complexity of Online Reinforcement Learning.	CoRR	2023	DBLP DOI BibTeX RDF
17	Edith Elkind, Warut Suksompong, Nicholas Teh	Settling the Score: Portioning with Cardinal Preferences.	CoRR	2023	DBLP DOI BibTeX RDF
17	Andrey E. Polyakov, Miroslav Krstic	Fixed-time Stabilization with a Prescribed Constant Settling Time by Static Feedback for Delay-Free and Input Delay Systems.	CoRR	2023	DBLP DOI BibTeX RDF
17	Majid Shahbazzadeh, Seyed Jalil Sadati	A linear matrix inequality-based approach for estimating upper bound of settling time.	J. Syst. Control. Eng.	2023	DBLP DOI BibTeX RDF
17	Leimin Wang, Haoyu Li, Cheng Hu 0005, Junhao Hu, Qingyi Wang	Synchronization and settling-time estimation of fuzzy memristive neural networks with time-varying delays: Fixed-time and preassigned-time control.	Fuzzy Sets Syst.	2023	DBLP DOI BibTeX RDF
17	Zicong Chen, Hui Zhang 0045, Jianqi Liu, Qinruo Wang, Jianhui Wang	Adaptive prescribed settling time periodic event-triggered control for uncertain robotic manipulators with state constraints.	Neural Networks	2023	DBLP DOI BibTeX RDF
17	Jianhui Wang 0003, Qijuan Gong, Kunfeng Huang, Zhi Liu 0001, C. L. Philip Chen, Jie Liu	Event-Triggered Prescribed Settling Time Consensus Compensation Control for a Class of Uncertain Nonlinear Systems With Actuator Failures.	IEEE Trans. Neural Networks Learn. Syst.	2023	DBLP DOI BibTeX RDF
17	Miguel Ramírez-Barrios, Fadi Dohnal	Settling Time Reduction by Open-Loop Control Based on Parametric Anti-Resonance.	CCE	2023	DBLP DOI BibTeX RDF
17	Young-Nam Lee, Kyung-Sik Choi, Seong-Won Jo, Gul Rahim, Kyeongha Kwon, Sang-Gug Lee 0001	Fast-settling Onboard Electrochemical Impedance Spectroscopy System Adopting Quasi-linear-phase Band-pass Filter.	I2MTC	2023	DBLP DOI BibTeX RDF
17	Liyu Chen, Andrea Tirinzoni, Matteo Pirotta, Alessandro Lazaric	Reaching Goals is Hard: Settling the Sample Complexity of the Stochastic Shortest Path.	ALT	2023	DBLP BibTeX RDF
17	Hong-Yi Huang, Yu-Ming Tsao, Angelo Nico M. Daroy, Kuo-Hsing Cheng	A 1~50mA 20ns Settling Time Low Dropout Regulator.	ICECS	2023	DBLP DOI BibTeX RDF
17	Young-Nam Lee, Min Jae Jung, Seong-Won Jo, Gul Rahim, Sang-Gug Lee 0001, Kyung-Sik Choi	Fast-Settling Onboard Electrochemical Impedance Spectroscopy System Adopting Two-Stage Hilbert Transform.	IECON	2023	DBLP DOI BibTeX RDF
17	Edith Elkind, Warut Suksompong, Nicholas Teh	Settling the Score: Portioning with Cardinal Preferences.	ECAI	2023	DBLP DOI BibTeX RDF
17	Javad Bagheri Asli, Alireza Saberkari, Atila Alvandpour	A Parallel-Path Amplifier for Fast Output Settling.	NEWCAS	2023	DBLP DOI BibTeX RDF
17	Ji-Hwan SeoI, Heejin Yang, Rohit Rothe, Zichen Fan, Qirui Zhang 0001, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester	A $1.5\mu\mathrm{W}$ End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling and Fast-Settling Analog Frontend.	ISSCC	2023	DBLP DOI BibTeX RDF
17	Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye	A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.	ISSCC	2023	DBLP DOI BibTeX RDF
17	Dong-Jick Min, Jun-Gi Lee, Kunhee Cho, Jae Hoon Shim	An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling Time.	ISCAS	2023	DBLP DOI BibTeX RDF
17	Feng Tai, Ziqin Nie, Yinhao Wang, Xingchen Chao, Qiang Li 0021	A Low-Noise and Settling-Enhanced Switched-Capacitor Amplifier With Correlated Level Shifting and Bandwidth Switching.	ISCAS	2023	DBLP DOI BibTeX RDF
17	Ziying Huang, Wei Deng 0001, Haikun Jia, Bufan Zhu, Angxiao Yan, Baoyong Chi	A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator.	ISCAS	2023	DBLP DOI BibTeX RDF
17	Attila Frankó, Gergely Hollósi	Settling Issues in IEEE 802.1AS Networks in PI Based Clock Servos.	CNSM	2023	DBLP DOI BibTeX RDF
17	Ren Jie Chin, Sai Hin Lai, Lloyd Ling, Ya Qi Yeo, Kar Hui Chan, Wing Son Loh	Settling Velocity Prediction for Fine Sediment Using Generalised Regression Neural Network and Nonlinear Autoregressive Exogenous.	IICAIET	2023	DBLP DOI BibTeX RDF
17	Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko	A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3.	A-SSCC	2023	DBLP DOI BibTeX RDF
17	Michael Bowling, John D. Martin, David Abel, Will Dabney	Settling the Reward Hypothesis.	ICML	2023	DBLP BibTeX RDF
17	Sumit Kumar, Nagendra Krishnapura	Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis.	APCCAS	2023	DBLP DOI BibTeX RDF
17	Aris Filos-Ratsikas, Panagiotis Kanellopoulos, Alexandros A. Voudouris, Rongsen Zhang	Settling the Distortion of Distributed Facility Location.	AAMAS	2023	DBLP BibTeX RDF
17	Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong, Jun-Eun Park	A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF