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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 164 occurrences of 122 keywords
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Results
Found 422 publication records. Showing 421 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
140 | Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay |
Slew-aware clock tree design for reliable subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 15-20, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
slew, clocks, subthreshold |
103 | Yuantao Peng, Xun Liu |
Low-power repeater insertion with both delay and slew rate constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 302-307, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power, interconnect, repeater insertion, slew rate |
91 | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li 0001, Weiping Shi, Cliff C. N. Sze |
Fast algorithms for slew constrained minimum cost buffering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 308-313, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
slew constraint, physical design, buffer insertion |
80 | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li 0001, Weiping Shi, Chin Ngai Sze |
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11), pp. 2009-2022, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
80 | Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
A simple metric for slew rate of RC circuits based on two circuit moments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9), pp. 1346-1354, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
79 | Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock |
A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 273-276, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
opamp, feedback, CMOS, compensation, operational amplifier, slew rate |
68 | Jeremy R. Tolbert, Saibal Mukhopadhyay |
Accurate buffer modeling with slew propagation in subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 91-96, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
68 | Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown |
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 143-149, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
68 | H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler |
A rail to rail, slew-boosted pre-charge buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
68 | Bjorn Dahlberg |
Increasing Test Accuracy by Varying Driver Slew Rate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 8(3), pp. 44-48, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
67 | Andre Vilas Boas, Eduardo Ribeiro, Alfredo Olmos, Ricardo Maltione |
Self-adaptable slew rate control output buffer for embedded microcontroller port applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 205-209, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
I/O pad, slew rate control, self-adaptable, microcontroller, output buffer |
67 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan |
Closed form expressions for extending step delay and slew metrics to ramp inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003, pp. 24-31, 2003, ACM, 1-58113-650-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Elmore, slew, delay, timing, interconnects, PDF, moments, median, skewness |
67 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan |
PERI: a technique for extending delay and slew metrics to ramp inputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 57-62, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Elmore, slew, delay, interconnects, PDF, moments, median, skewness, standard deviation |
60 | Ying-Yu Chen, Chen Dong 0003, Deming Chen |
Clock tree synthesis under aggressive buffer insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 86-89, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
slew, buffer insertion, buffer sizing, clock tree, maze routing |
56 | Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind |
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 685-691, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
56 | Xiaoji Ye, Frank Liu 0001, Peng Li 0001 |
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 913-926, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
56 | Xiaoji Ye, Peng Li 0001, Frank Liu 0001 |
Practical variation-aware interconnect delay and slew analysis for statistical timing verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 54-59, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu |
High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Andrew Havlir, David Z. Pan |
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 171-178, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Charles J. Alpert, Frank Liu 0001, Chandramouli V. Kashyap, Anirudh Devgan |
Closed-form delay and slew metrics made easy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1661-1669, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
56 | Shabbir H. Batterywala, Narendra V. Shenoy |
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 989-994, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
56 | Shabbir H. Batterywala, Narendra V. Shenoy |
A Method to Estimate Slew and Delay in Coupled Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 411-416, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
56 | Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
Simple metrics for slew rate of RC circuits based on two circuit moments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 950-953, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
56 | Charles J. Alpert, Frank Liu 0001, Chandramouli V. Kashyap, Anirudh Devgan |
Delay and slew metrics using the lognormal distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 382-385, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
56 | Hoi Lee, Philip K. T. Mok |
A CMOS current-mirror amplifier with compact slew rate enhancement circuit for large capacitive load applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 220-223, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
55 | Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi |
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 340-344, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage |
51 | Pooi Yuen Kam, Seng Slew Ng, Tok Soon Ng |
Optimum symbol-by-symbol detection of uncoded digital data over the Gaussian channel with unknown carrier phase. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 42(8), pp. 2543-2552, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
43 | Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang |
A metal-only-ECO solver for input-slew and output-loading violations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 191-198, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
input skew violation, output loading, buffer insertion, eco |
43 | Young-Ho Kwak, Inhwa Jung, Chulwoo Kim |
A slew-rate controlled output driver with one-cycle tuning time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 99-100, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín |
High slew rate two stage A/AB and AB/AB op-amps with phase lead compensation at output node and local common mode feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 288-291, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown |
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 815-820, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Ratnakar Goyal, Sachin Shrivastava, Harindranath Parameswaran, Parveen Khurana |
Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 278-282, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula |
A framework for statistical timing analysis using non-linear delay and slew models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 225-230, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Amorn Jiraseree-amornkun, Apisak Worapishet, Eric A. M. Klumperink, Bram Nauta, Wanlop Surakampontorn |
Slew rate induced distortion in switched-resistor integrators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye 0001 |
Interconnect Delay and Slew Metrics Using the First Three Moments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 598-602, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
D3M, ID3M, SS3M, SIS3M |
43 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan |
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4), pp. 509-516, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Markus Tahedl, Hans-Jörg Pfleiderer |
Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 69-78, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Soroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer |
TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 19-24, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
elmore, threshold-based filtering algorithm, static timing analysis, moments, AWE |
43 | Bernard N. Sheehan |
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 866-869, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
static timing analysis, effective capacitance |
43 | Rung-Bin Lin, Jinq-Chang Chen |
Low Power CMOS Off-Chip Drivers with Slew-rate Difference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 169-172, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
42 | Jing Zhang |
A Low-Power and High Slew-rate CMOS Voltage Follower. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MVHI ![In: 2010 International Conference on Machine Vision and Human-machine Interface, MVHI 2010, Kaifeng, China, April 24-25, 2010, pp. 210-213, 2010, IEEE Computer Soceity, 978-0-7695-4009-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CSTN-LCD, voltage-follower, high slew-rate, low-power |
38 | Kyungho Ryu, Ji-Yong Jeong, Jung-Pil Lim, Kil-Hoon Lee, Kyongho Kim, Yongil Kwon, Seongjong Yoo, Siwoo Kim, Hyun-Wook Lim, Jae-Youl Lee |
A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 382-383, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
38 | Scott Lerner, Baris Taskin |
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(1), pp. 1-10, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
38 | Scott Lerner, Eric Leggett, Baris Taskin |
Slew-down: analysis of slew relaxation for low-impact clock buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, TX, USA, June 17, 2017, pp. 1-4, 2017, IEEE Computer Society, 978-1-5386-1536-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
36 | Ruiming Chen, Hai Zhou 0001 |
Fast Min-Cost Buffer Insertion under Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 338-343, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
Non-gaussian statistical interconnect timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 533-538, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama |
A Gaussian mixture model for statistical timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 110-115, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
slew distribution, variability, Gaussian mixture model, statistical timing analysis, delay distribution |
36 | José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski |
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 96-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate |
36 | Pradip Mandal, V. Visvanathan |
Design of high performance two stage CMOS cascode op-amps with stable biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 234-237, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability |
36 | John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin |
Optimal wire sizing and buffer insertion for low power and a generalized delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 138-143, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Timing Optization, Dynamic Power Dissipation, Signal Slew, Dynamic Programming, Elmore Delay |
31 | J. V. R. Ravindra, M. B. Srinivas |
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 325-330, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Tongyu Song, Shouli Yan |
A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 477-480, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Joongho Choi, Jinup Lim, Cheng-Chew Lim |
A low-voltage operational amplifier with high slew-rate for sigma-delta modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Sushmita Baswa, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal |
A novel family of low-voltage very low power super class AB OTAs with significantly enhanced slew rate and bandwidth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 729-732, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio Jesús Torralba Silgado, Carlos Nieva |
A new class AB differential input stage for implementation of low-voltage high slew rate op amps and linear transconductors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 671-674, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Iyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis |
A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 792-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Gustavo E. Téllez, Majid Sarrafzadeh |
Minimal buffer insertion in clock trees with skew and slew rate constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(4), pp. 333-342, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Seungwhun Paik, Sangmin Kim, Youngsoo Shin |
Wakeup synthesis and its buffered tree construction for power gating circuit designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 413-418, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
wakeup synthesis, leakage, power gating |
24 | Michael Lustig, Seung-Jean Kim, John M. Pauly |
A Fast Method for Designing Time-Optimal Gradient Waveforms for Arbitrary k-Space Trajectories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Medical Imaging ![In: IEEE Trans. Medical Imaging 27(6), pp. 866-873, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Mohamed H. Abu-Rahma, Mohab Anis |
A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 1983-1995, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Amit Goel, Sarma B. K. Vrudhula |
Current source based standard cell model for accurate signal integrity and timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 574-579, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye |
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 377-382, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Janet Meiling Wang, Jun Li 0066, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla |
Modeling the Driver Load in the Presence of Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2264-2275, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Zushu Yan, Qiang Bian, Yuanfu Zhao |
Freqency Compensation for Multistage Amplifiers using Active-Feedback Current Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1710-1714, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout |
A multi-port current source model for multiple-input switching effects in CMOS library cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 247-252, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MCSM, cell library characterization, multiple input switching, timing analysis, current source model, cell model |
24 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VGTA: Variation Aware Gate Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 351-356, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Salvatore Pennisi |
High-performance CMOS current feedback operational amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1573-1576, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 426-430, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay |
24 | Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo |
Probabilistic crosstalk delay estimation for ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9), pp. 1377-1383, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
A library compatible driver output model for on-chip RLC transmission lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 128-136, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Shanta Thoutam, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal |
Power efficient fully differential low-voltage two stage class AB/AB op-amp architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 733-736, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Ruchir Puri, David S. Kung 0001, Anthony D. Drumm |
Fast and accurate wire delay estimation for physical synthesis of large ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 30-36, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
placement driven synthesis, wire delay, estimation, integrated circuit design |
24 | Kanak Agarwal, Dennis Sylvester, David T. Blaauw |
A library compatible driving point model for on-chip RLC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 63-69, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Nathan Kalyanasundharam, Nital Patwa |
Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 118-123, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance |
24 | S. Turgis, Daniel Auvergne |
A novel macromodel for power estimation in CMOS structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11), pp. 1090-1098, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
23 | Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester |
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 848-854, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate |
19 | Hyunjun Park, Woojoong Jung, Minsu Kim, Hyung-Min Lee |
A Wide-Load-Range and High-Slew Capacitor-Less NMOS LDO With Adaptive-Gain Nested Miller Compensation and Pre-Emphasis Inverse Biasing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(10), pp. 2696-2708, October 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka |
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(2), pp. 428-438, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang |
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 90, pp. 245-260, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Sougata Ghosh |
Low-Voltage Super Class-AB Bulk-Driven Single-Stage Subthreshold OTA with Very High DC Gain, Slew Rate, and High Driving Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(3), pp. 1279-1292, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Xiaoyan Gui, Renjie Tang, Kai Li, Kanan Wang, Dan Li 0011, Quan Pan 0002, Li Geng |
A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 17(1), pp. 13-28, January 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Mohd Asim Saeed, Manoj Kumar, B. Umapathi, Devarshi Mrinal Das |
Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta-Sigma Modulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(6), pp. 1821-1825, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Bhawna Aggarwal, Vaishali Sharma |
A New Improved Current Splitter OTA with Higher Transconductance and Slew Rate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 131(4), pp. 2477-2492, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Jingwen Huang, Zihao Zhao |
Synchronous slew/translation positioning and swing suppression control for 4-DOF tower crane system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Inst. Meas. Control ![In: Trans. Inst. Meas. Control 45(16), pp. 3077-3091, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Francesco Gagliardi 0002, Alessandro Catania, Massimo Piotto, Paolo Bruschi, Michele Dei |
A Novel High-Performance Parallel-Type Slew-Rate Enhancer for LCD-Driving Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 18th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023, Valencia, Spain, June 18-21, 2023, pp. 65-68, 2023, IEEE, 979-8-3503-0320-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | V. H. Arzate Palma, F. Sandoval-Ibarra |
Slew-rate Comparison of single-ended amplifiers-the Folded Cascode and the Recycling Folded Cascode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCE ![In: 20th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2023, Mexico City, Mexico, October 25-27, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-0676-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Ren Lu, Wei Zhang, Lieqiu Jiang, Genggeng Liu |
Slew-Driven Layer Assignment for Advanced Non-default-rule Wires. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISA ![In: Web Information Systems and Applications - 20th International Conference, WISA 2023, Chengdu, China, September 15-17, 2023, Proceedings, pp. 539-550, 2023, Springer, 978-981-99-6221-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Bjørn Andreas Kristiansen, Dennis D. Langer, Joseph L. Garrett, Simen Berg, Jan Tommy Gravdahl, Tor Anders Johansen |
Accuracy of a slew maneuver for the HYPSO-1 hyperspectral imaging satellite - in-orbit results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WHISPERS ![In: 13th Workshop on Hyperspectral Imaging and Signal Processing: Evolution in Remote Sensing, WHISPERS 2023, Athens, Greece, October 31 - November 2, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-9557-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Seunghwa Shin, Gyeong-Gu Kang, Gyu-Wan Lim, Hyun-Sik Kim |
A Mobile OLED Source-Driver IC featuring Ultra-Compact 3-Stage-Cascaded 10-Bit DAC and 42V/μs-Slew-Rate True-DC-Interpolative Super-OTA Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Archisman Ghosh, Md. Abdur Rahman, Debayan Das, Santosh Ghosh, Shreyas Sen |
Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-9948-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Yarallah Koolivand, Yasser Rezayean, Milad Zamani, Meysam Akbari, Omid Shoaei, Kea-Tiong Tang, Farshad Moradi |
A 69MHz-Bandwidth 40V/μs-Slew-rate 3nV/√Hz-Noises 4.5μV-Offset Chopper Operational Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-9948-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Wangchen Fan, Zhongyuan Fang, Yongjia Lil, Minggang Chen, Weifeng Sun |
A Transient-Enhanced Capacitor-Less LDO With 30-MHz Bandwidth and High Slew Rate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 202-206, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
19 | Mihika Mahendra, Shweta Kumari, Maneesha Gupta |
Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 84, pp. 47-61, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Cristian Raducan, Marius Neag |
Slew-Rate Booster and Frequency Compensation Circuit for Automotive LDOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(1), pp. 465-477, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Emad Ebrahimi, Amin Roozbakhsh, Mohammadreza Rasekhi |
A new slew rate enhancement technique for operational transconductance amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 50(3), pp. 997-1014, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Caffey Jindal, Rishikesh Pandey |
High Slew-Rate and Very-Low Output Resistance Class-AB Flipped Voltage Follower Cell for Low-Voltage Low-Power Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 123(1), pp. 215-228, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Mehdi Moradian Boanloo, Mohammad Yavari |
A push-pull FVF based LDO voltage regulator with slew rate enhancement at the gate of power transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 122, pp. 105389, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang |
LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
19 | Ionut-Constantin Guran, Adriana Florescu, Lucian Andrei Perisoara |
Optimized Slew Rate Control Technique for Automotive Low-Dropout Linear Voltage Regulators Simulation Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECAI ![In: 14th International Conference on Electronics, Computers and Artificial Intelligence, ECAI 2022, Ploiesti, Romania, June 30 - July 1, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-9535-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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19 | Karthik Debbadi, Yoann Pascal, Marco Liserre |
dv/dt filter design incorporating machine impedance and voltage slew rate for WBG-based electric drives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2022 - 48th Annual Conference of the IEEE Industrial Electronics Society, Brussels, Belgium, October 17-20, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-8025-3. The full citation details ...](Pics/full.jpeg) |
2022 |
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