Search results for "slew"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
140	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
103	Yuantao Peng, Xun Liu	Low-power repeater insertion with both delay and slew rate constraints.	DAC	2006	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion, slew rate
91	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li 0001, Weiping Shi, Cliff C. N. Sze	Fast algorithms for slew constrained minimum cost buffering.	DAC	2006	DBLP DOI BibTeX RDF	slew constraint, physical design, buffer insertion
80	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li 0001, Weiping Shi, Chin Ngai Sze	Fast Algorithms for Slew-Constrained Minimum Cost Buffering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
80	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A simple metric for slew rate of RC circuits based on two circuit moments.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
79	Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock	A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	opamp, feedback, CMOS, compensation, operational amplifier, slew rate
68	Jeremy R. Tolbert, Saibal Mukhopadhyay	Accurate buffer modeling with slew propagation in subthreshold circuits.	ISQED	2009	DBLP DOI BibTeX RDF
68	Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF
68	H. Dine, S. Chuang, Phillip E. Allen, Paul E. Hasler	A rail to rail, slew-boosted pre-charge buffer.	ISCAS	2006	DBLP DOI BibTeX RDF
68	Bjorn Dahlberg	Increasing Test Accuracy by Varying Driver Slew Rate.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
67	Andre Vilas Boas, Eduardo Ribeiro, Alfredo Olmos, Ricardo Maltione	Self-adaptable slew rate control output buffer for embedded microcontroller port applications.	SBCCI	2008	DBLP DOI BibTeX RDF	I/O pad, slew rate control, self-adaptable, microcontroller, output buffer
67	Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan	Closed form expressions for extending step delay and slew metrics to ramp inputs.	ISPD	2003	DBLP DOI BibTeX RDF	Elmore, slew, delay, timing, interconnects, PDF, moments, median, skewness
67	Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan	PERI: a technique for extending delay and slew metrics to ramp inputs.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	Elmore, slew, delay, interconnects, PDF, moments, median, skewness, standard deviation
60	Ying-Yu Chen, Chen Dong 0003, Deming Chen	Clock tree synthesis under aggressive buffer insertion.	DAC	2010	DBLP DOI BibTeX RDF	slew, buffer insertion, buffer sizing, clock tree, maze routing
56	Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind	Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.	VLSI Design	2008	DBLP DOI BibTeX RDF
56	Xiaoji Ye, Frank Liu 0001, Peng Li 0001	Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
56	Xiaoji Ye, Peng Li 0001, Frank Liu 0001	Practical variation-aware interconnect delay and slew analysis for statistical timing verification.	ICCAD	2006	DBLP DOI BibTeX RDF
56	Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu	High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit.	ISCAS	2006	DBLP DOI BibTeX RDF
56	Andrew Havlir, David Z. Pan	Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines.	ISQED	2006	DBLP DOI BibTeX RDF
56	Charles J. Alpert, Frank Liu 0001, Chandramouli V. Kashyap, Anirudh Devgan	Closed-form delay and slew metrics made easy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
56	Shabbir H. Batterywala, Narendra V. Shenoy	Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables.	VLSI Design	2004	DBLP DOI BibTeX RDF
56	Shabbir H. Batterywala, Narendra V. Shenoy	A Method to Estimate Slew and Delay in Coupled Digital Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
56	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	Simple metrics for slew rate of RC circuits based on two circuit moments.	DAC	2003	DBLP DOI BibTeX RDF
56	Charles J. Alpert, Frank Liu 0001, Chandramouli V. Kashyap, Anirudh Devgan	Delay and slew metrics using the lognormal distribution.	DAC	2003	DBLP DOI BibTeX RDF
56	Hoi Lee, Philip K. T. Mok	A CMOS current-mirror amplifier with compact slew rate enhancement circuit for large capacitive load applications.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
55	Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi	A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique.	ISLPED	2003	DBLP DOI BibTeX RDF	CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage
51	Pooi Yuen Kam, Seng Slew Ng, Tok Soon Ng	Optimum symbol-by-symbol detection of uncoded digital data over the Gaussian channel with unknown carrier phase.	IEEE Trans. Commun.	1994	DBLP DOI BibTeX RDF
43	Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang	A metal-only-ECO solver for input-slew and output-loading violations.	ISPD	2009	DBLP DOI BibTeX RDF	input skew violation, output loading, buffer insertion, eco
43	Young-Ho Kwak, Inhwa Jung, Chulwoo Kim	A slew-rate controlled output driver with one-cycle tuning time.	ASP-DAC	2008	DBLP DOI BibTeX RDF
43	Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín	High slew rate two stage A/AB and AB/AB op-amps with phase lead compensation at output node and local common mode feedback.	ISCAS	2008	DBLP DOI BibTeX RDF
43	Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.	ISQED	2008	DBLP DOI BibTeX RDF
43	Ratnakar Goyal, Sachin Shrivastava, Harindranath Parameswaran, Parveen Khurana	Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation.	VLSI Design	2007	DBLP DOI BibTeX RDF
43	Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula	A framework for statistical timing analysis using non-linear delay and slew models.	ICCAD	2006	DBLP DOI BibTeX RDF
43	Amorn Jiraseree-amornkun, Apisak Worapishet, Eric A. M. Klumperink, Bram Nauta, Wanlop Surakampontorn	Slew rate induced distortion in switched-resistor integrators.	ISCAS	2006	DBLP DOI BibTeX RDF
43	Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye 0001	Interconnect Delay and Slew Metrics Using the First Three Moments.	ISQED	2005	DBLP DOI BibTeX RDF	D3M, ID3M, SS3M, SIS3M
43	Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu 0001, Anirudh Devgan	Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
43	Markus Tahedl, Hans-Jörg Pfleiderer	Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures.	PATMOS	2004	DBLP DOI BibTeX RDF
43	Soroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer	TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	elmore, threshold-based filtering algorithm, static timing analysis, moments, AWE
43	Bernard N. Sheehan	Osculating Thevenin model for predicting delay and slew of capacitively characterized cells.	DAC	2002	DBLP DOI BibTeX RDF	static timing analysis, effective capacitance
43	Rung-Bin Lin, Jinq-Chang Chen	Low Power CMOS Off-Chip Drivers with Slew-rate Difference.	ASP-DAC	1999	DBLP DOI BibTeX RDF
42	Jing Zhang	A Low-Power and High Slew-rate CMOS Voltage Follower.	MVHI	2010	DBLP DOI BibTeX RDF	CSTN-LCD, voltage-follower, high slew-rate, low-power
38	Kyungho Ryu, Ji-Yong Jeong, Jung-Pil Lim, Kil-Hoon Lee, Kyongho Kim, Yongil Kwon, Seongjong Yoo, Siwoo Kim, Hyun-Wook Lim, Jae-Youl Lee	A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond.	ISSCC	2023	DBLP DOI BibTeX RDF
38	Scott Lerner, Baris Taskin	Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
38	Scott Lerner, Eric Leggett, Baris Taskin	Slew-down: analysis of slew relaxation for low-impact clock buffers.	SLIP	2017	DBLP DOI BibTeX RDF
36	Ruiming Chen, Hai Zhou 0001	Fast Min-Cost Buffer Insertion under Process Variations.	DAC	2007	DBLP DOI BibTeX RDF
36	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	Non-gaussian statistical interconnect timing analysis.	DATE	2006	DBLP DOI BibTeX RDF
36	Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama	A Gaussian mixture model for statistical timing analysis.	DAC	2009	DBLP DOI BibTeX RDF	slew distribution, variability, Gaussian mixture model, statistical timing analysis, delay distribution
36	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
36	Pradip Mandal, V. Visvanathan	Design of high performance two stage CMOS cascode op-amps with stable biasing.	VLSI Design	1996	DBLP DOI BibTeX RDF	two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability
36	John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin	Optimal wire sizing and buffer insertion for low power and a generalized delay model.	ICCAD	1995	DBLP DOI BibTeX RDF	Timing Optization, Dynamic Power Dissipation, Signal Slew, Dynamic Programming, Elmore Delay
31	J. V. R. Ravindra, M. B. Srinivas	A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.	DSD	2007	DBLP DOI BibTeX RDF
31	Tongyu Song, Shouli Yan	A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter.	ISCAS	2007	DBLP DOI BibTeX RDF
31	Joongho Choi, Jinup Lim, Cheng-Chew Lim	A low-voltage operational amplifier with high slew-rate for sigma-delta modulators.	ISCAS	2006	DBLP DOI BibTeX RDF
31	Sushmita Baswa, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	A novel family of low-voltage very low power super class AB OTAs with significantly enhanced slew rate and bandwidth.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
31	Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio Jesús Torralba Silgado, Carlos Nieva	A new class AB differential input stage for implementation of low-voltage high slew rate op amps and linear transconductors.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
31	Iyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis	A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection.	DATE	1999	DBLP DOI BibTeX RDF
31	Gustavo E. Téllez, Majid Sarrafzadeh	Minimal buffer insertion in clock trees with skew and slew rate constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
24	Seungwhun Paik, Sangmin Kim, Youngsoo Shin	Wakeup synthesis and its buffered tree construction for power gating circuit designs.	ISLPED	2010	DBLP DOI BibTeX RDF	wakeup synthesis, leakage, power gating
24	Michael Lustig, Seung-Jean Kim, John M. Pauly	A Fast Method for Designing Time-Optimal Gradient Waveforms for Arbitrary k-Space Trajectories.	IEEE Trans. Medical Imaging	2008	DBLP DOI BibTeX RDF
24	Mohamed H. Abu-Rahma, Mohab Anis	A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
24	Amit Goel, Sarma B. K. Vrudhula	Current source based standard cell model for accurate signal integrity and timing analysis.	DATE	2008	DBLP DOI BibTeX RDF
24	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters.	VLSI Design	2008	DBLP DOI BibTeX RDF
24	Janet Meiling Wang, Jun Li 0066, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla	Modeling the Driver Load in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Zushu Yan, Qiang Bian, Yuanfu Zhao	Freqency Compensation for Multistage Amplifiers using Active-Feedback Current Buffers.	CCECE	2006	DBLP DOI BibTeX RDF
24	Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout	A multi-port current source model for multiple-input switching effects in CMOS library cells.	DAC	2006	DBLP DOI BibTeX RDF	MCSM, cell library characterization, multiple input switching, timing analysis, current source model, cell model
24	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VGTA: Variation Aware Gate Timing Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
24	Salvatore Pennisi	High-performance CMOS current feedback operational amplifier.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
24	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay
24	Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo	Probabilistic crosstalk delay estimation for ASICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
24	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driver output model for on-chip RLC transmission lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
24	Shanta Thoutam, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	Power efficient fully differential low-voltage two stage class AB/AB op-amp architectures.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
24	Ruchir Puri, David S. Kung 0001, Anthony D. Drumm	Fast and accurate wire delay estimation for physical synthesis of large ASICs.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	placement driven synthesis, wire delay, estimation, integrated circuit design
24	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driving point model for on-chip RLC interconnects.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
24	Nathan Kalyanasundharam, Nital Patwa	Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor.	ICCD	1999	DBLP DOI BibTeX RDF	multiported, supply inductance, TLB, simultaneous switching noise, decoupling capacitance
24	S. Turgis, Daniel Auvergne	A novel macromodel for power estimation in CMOS structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
23	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF	RLC model, loop inductance, switch-factor, current return loop, data-bus and clock, static timing analysis, slew rate
19	Hyunjun Park, Woojoong Jung, Minsu Kim, Hyung-Min Lee	A Wide-Load-Range and High-Slew Capacitor-Less NMOS LDO With Adaptive-Gain Nested Miller Compensation and Pre-Emphasis Inverse Biasing.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
19	Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka	An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
19	Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang	A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.	Integr.	2023	DBLP DOI BibTeX RDF
19	Sougata Ghosh	Low-Voltage Super Class-AB Bulk-Driven Single-Stage Subthreshold OTA with Very High DC Gain, Slew Rate, and High Driving Capability.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
19	Xiaoyan Gui, Renjie Tang, Kai Li, Kanan Wang, Dan Li 0011, Quan Pan 0002, Li Geng	A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique.	IET Circuits Devices Syst.	2023	DBLP DOI BibTeX RDF
19	Mohd Asim Saeed, Manoj Kumar, B. Umapathi, Devarshi Mrinal Das	Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta-Sigma Modulator.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
19	Bhawna Aggarwal, Vaishali Sharma	A New Improved Current Splitter OTA with Higher Transconductance and Slew Rate.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
19	Jingwen Huang, Zihao Zhao	Synchronous slew/translation positioning and swing suppression control for 4-DOF tower crane system.	Trans. Inst. Meas. Control	2023	DBLP DOI BibTeX RDF
19	Francesco Gagliardi 0002, Alessandro Catania, Massimo Piotto, Paolo Bruschi, Michele Dei	A Novel High-Performance Parallel-Type Slew-Rate Enhancer for LCD-Driving Applications.	PRIME	2023	DBLP DOI BibTeX RDF
19	V. H. Arzate Palma, F. Sandoval-Ibarra	Slew-rate Comparison of single-ended amplifiers-the Folded Cascode and the Recycling Folded Cascode.	CCE	2023	DBLP DOI BibTeX RDF
19	Ren Lu, Wei Zhang, Lieqiu Jiang, Genggeng Liu	Slew-Driven Layer Assignment for Advanced Non-default-rule Wires.	WISA	2023	DBLP DOI BibTeX RDF
19	Bjørn Andreas Kristiansen, Dennis D. Langer, Joseph L. Garrett, Simen Berg, Jan Tommy Gravdahl, Tor Anders Johansen	Accuracy of a slew maneuver for the HYPSO-1 hyperspectral imaging satellite - in-orbit results.	WHISPERS	2023	DBLP DOI BibTeX RDF
19	Seunghwa Shin, Gyeong-Gu Kang, Gyu-Wan Lim, Hyun-Sik Kim	A Mobile OLED Source-Driver IC featuring Ultra-Compact 3-Stage-Cascaded 10-Bit DAC and 42V/μs-Slew-Rate True-DC-Interpolative Super-OTA Buffer.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
19	Archisman Ghosh, Md. Abdur Rahman, Debayan Das, Santosh Ghosh, Shreyas Sen	Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits.	CICC	2023	DBLP DOI BibTeX RDF
19	Yarallah Koolivand, Yasser Rezayean, Milad Zamani, Meysam Akbari, Omid Shoaei, Kea-Tiong Tang, Farshad Moradi	A 69MHz-Bandwidth 40V/μs-Slew-rate 3nV/√Hz-Noises 4.5μV-Offset Chopper Operational Amplifier.	CICC	2023	DBLP DOI BibTeX RDF
19	Wangchen Fan, Zhongyuan Fang, Yongjia Lil, Minggang Chen, Weifeng Sun	A Transient-Enhanced Capacitor-Less LDO With 30-MHz Bandwidth and High Slew Rate.	APCCAS	2023	DBLP DOI BibTeX RDF
19	Mihika Mahendra, Shweta Kumari, Maneesha Gupta	Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application.	Integr.	2022	DBLP DOI BibTeX RDF
19	Cristian Raducan, Marius Neag	Slew-Rate Booster and Frequency Compensation Circuit for Automotive LDOs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
19	Emad Ebrahimi, Amin Roozbakhsh, Mohammadreza Rasekhi	A new slew rate enhancement technique for operational transconductance amplifiers.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
19	Caffey Jindal, Rishikesh Pandey	High Slew-Rate and Very-Low Output Resistance Class-AB Flipped Voltage Follower Cell for Low-Voltage Low-Power Analog Circuits.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
19	Mehdi Moradian Boanloo, Mohammad Yavari	A push-pull FVF based LDO voltage regulator with slew rate enhancement at the gate of power transistor.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
19	Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang	LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
19	Ionut-Constantin Guran, Adriana Florescu, Lucian Andrei Perisoara	Optimized Slew Rate Control Technique for Automotive Low-Dropout Linear Voltage Regulators Simulation Models.	ECAI	2022	DBLP DOI BibTeX RDF
19	Karthik Debbadi, Yoann Pascal, Marco Liserre	dv/dt filter design incorporating machine impedance and voltage slew rate for WBG-based electric drives.	IECON	2022	DBLP DOI BibTeX RDF