Search results for "switches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
75	Dimitrios N. Serpanos, Poluxeni Mountrouidou, Maria Gamvrili	Evaluation of hardware and software schedulers for embedded switches.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	embedded switches, scheduling, embedded systems, packet switches, ATM switches
73	Cheng-Shang Chang, Jay Cheng, Duan-Shin Lee, Chi-Feung Wu	Quasi-Output-Buffered Switches.	IEEE Trans. Parallel Distributed Syst.	2011	DBLP DOI BibTeX RDF	Delay performance, load-balanced switches, output-buffered switches, packet-pair switches, quasi-output-buffered switches
71	Claus Bauer	Distributed scheduling policies in networks of input-queued packet switches.	Comput. Commun. Rev.	2004	DBLP DOI BibTeX RDF
70	Cheng-Ping Wang, Chin-Long Wey	Test Generation Of Analog Switched-Current Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	switched current circuits, analog switched-current circuits, current switches, voltage switches, noncatastrophic faults, transistor switches, full testability, current copiers, stray inductance, CMOS switch, BIST design, fault model, circuit simulation, macromodel, switched-capacitor circuits, test sequence generation, catastrophic faults
69	Yann-Hang Lee, Randy Chow, Sandra E. Cheung	Circular window control schemes in fast packet switches.	ICCCN	1995	DBLP DOI BibTeX RDF	circular window control scheme, fast packet switches, packet switch fabrics, fixed length window, circular transmission sequences, contentions minimisation, maximal throughput, nonblocking switches, banyan-based blocking switches, performance analysis, packet switching, scheduling algorithm, queueing, simulation results
65	Cheng-Shang Chang, Jay Cheng, Duan-Shin Lee, Chi-Feung Wu	Quasi-Output-Buffered Switches.	INFOCOM	2008	DBLP DOI BibTeX RDF
63	Saad Mneimneh, Vishal Sharma, Kai-Yeung Siu	Switching using parallel input-output queued switches with no speedup.	IEEE/ACM Trans. Netw.	2002	DBLP DOI BibTeX RDF	parallel switches, switching, speedup, delay guarantee
60	Matthew Andrews, Lisa Zhang	Scheduling Protocols for Switches with Large Envelopes.	J. Sched.	2004	DBLP DOI BibTeX RDF	switches with large envelopes, input-queued and output-queued switches, stability, scheduling protocols
59	Chuan-Bi Lin, Roberto Rojas-Cessa	Module-First Matching Schemes for Scalable Input-Queued Space-Space-Space Clos-Network Packet Switches.	ICC	2008	DBLP DOI BibTeX RDF
59	Deng Pan, Yuanyuan Yang 0001	Providing flow based performance guarantees for buffered crossbar switches.	IPDPS	2008	DBLP DOI BibTeX RDF
59	Xuesong Tan, Shuo-Yen Robert Li	Mixed Preservation of Conditionally Nonblocking Switches under 2-stage Interconnection.	PDCAT	2006	DBLP DOI BibTeX RDF
57	Biju K. Raveendran, K. Durga Prasad, Sundar Balasubramaniam, S. Gurunarayanan 0001	Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems.	ICDCN	2006	DBLP DOI BibTeX RDF	preemption and context switches, scheduling, Real time systems, low power
57	Deng Pan, Yuanyuan Yang 0001	Localized asynchronous packet scheduling for buffered crossbar switches.	ANCS	2006	DBLP DOI BibTeX RDF	100% throughput, buffered crossbar switches, priority encoders, packet scheduling
54	Cheng-Shang Chang, Duan-Shin Lee, Chi-Yao Yue	Providing guaranteed rate services in the load balanced Birkhoff-von Neumann switches.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	Birkhoff-von Neumann switches, guaranteed rate services, multi-stage switches, multicasting flows, variable length packets
54	Hsiang-Hui Huang, Ching-Hwa Cheng	Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit.	VTS	2007	DBLP DOI BibTeX RDF
53	Claus Bauer	Low complexity, stable scheduling algorithms for networks of input queued switches with no or very low speed-up.	Comput. Commun. Rev.	2006	DBLP DOI BibTeX RDF	modeling of communication networks, stability, scheduling algorithms
53	Claus Bauer	Distributed Scheduling Policies of Low Complexity for Networks of Input-Queued Switches.	HSNMC	2004	DBLP DOI BibTeX RDF
53	Matthew Andrews, Lisa Zhang	Scheduling protocols for switches with large envelopes.	SODA	2002	DBLP BibTeX RDF
53	D. Manjunath, Biplab Sikdar 0001	Variable Length Packet Switches: Input Queued Fabrics with Finite Buffers, Speedup, and Parallelism.	HiPC	2001	DBLP DOI BibTeX RDF
53	Jahng S. Park, Nathaniel J. Davis IV	The Folded Hypercube ATM Switches.	ICN (2)	2001	DBLP DOI BibTeX RDF
53	P. D. Grant, M. W. Denhoff, Raafat R. Mansour	A Comparison between RF MEMS Switches and Semiconductor Switches.	ICMENS	2004	DBLP DOI BibTeX RDF
51	Zhenghao Zhang, Yuanyuan Yang	A novel analytical model for switches with shared buffer.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	Markov chain, aggregation, analytical model, switches, shared buffer
51	Matthew Andrews, Lisa Zhang	Achieving stability in networks of input-queued switches.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	scheduling, stability, input-queued switches
48	Xiaohua Jia, Chan-Hee Lee, Jim M. Ng, Edward Chan	Routing multicast connections with optimal network cost in ATM networks.	ICCCN	1995	DBLP DOI BibTeX RDF	optimal network cost, multicast connections routing, virtual path switches, virtual channel switches, optimal multicast routing, simulations, asynchronous transfer mode, packet switching, network topology, routing algorithm, bandwidth, ATM networks, switching functions
47	Zhenghao Zhang, Yuanyuan Yang 0001	A novel analytical model for electronic and optical switches with shared buffer.	INFOCOM	2005	DBLP DOI BibTeX RDF
47	Claus Bauer	Stable Local Scheduling Algorithms With Low Complexity and Without Speedup for a Network of Input-Buffered Switches.	CAAN	2004	DBLP DOI BibTeX RDF
45	Gary E. Burnett, Ainojie Alexander Irune	Drivers' quality ratings for switches in cars: assessing the role of the vision, hearing and touch senses.	AutomotiveUI	2009	DBLP DOI BibTeX RDF	in-car switches, quality perception, usability, affective design
45	Madhusudan Hosaagrahara, Harish Sethu	Max-Min Fair Scheduling in Input-Queued Switches.	IEEE Trans. Parallel Distributed Syst.	2008	DBLP DOI BibTeX RDF	quality-of-service, fairness, Routers, input-queued switches
45	Alexander Kesselman, Adi Rosén	Scheduling policies for CIOQ switches.	SPAA	2003	DBLP DOI BibTeX RDF	CIOQ switches, competitive analysis, buffer management, scheduling policies
45	Wenjian Qiao, Lionel M. Ni, Tomas Rokicki	Adaptive-Trail Routing and Performance Evaluation in Irregular Networks Using Cut-Through Switches.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	incremental scalability, performance evaluation, Adaptive routing, deadlock-free routing, irregular networks, cut-through switches
45	Aristotel Tentov, Aksenti L. Grnarov	Performance Analysis of ATM Switches with Multistage Packet Switching Interconnection Networks.	LCN	1996	DBLP DOI BibTeX RDF	multistage packet switching interconnection networks, mathematical method, finite buffering capacity, switching elements output, uniform traffic, buffered interconnection networks, synchronous buffered switching element, finite buffer size, performance analysis, asynchronous transfer mode, blocking, ATM switches, output buffering, traffic patterns, nonuniform traffic
41	Deng Pan, Yuanyuan Yang 0001	Localized Independent Packet Scheduling for Buffered Crossbar Switches.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
41	Paolo Giaccone, Emilio Leonardi	Asymptotic Performance Limits of Switches With Buffered Crossbars Supporting Multicast Traffic.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
41	Shuo-Yen Robert Li, Xuesong Jonathan Tan	Preservation of Conditionally Nonblocking Switches Under Two-Stage Interconnection.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
41	Ilias Iliadis, Wolfgang E. Denzel	Resequencing Worst-Case Analysis for Parallel Buffered Packet Switches.	IEEE Trans. Commun.	2007	DBLP DOI BibTeX RDF
41	Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez	Testing and Diagnosis of Power Switches in SOCs.	ETS	2006	DBLP DOI BibTeX RDF
41	Luis García, Hugo Opazo, Enrique López	Switches Optimum Location in Medium Voltage Network Via Minimization of Energy Not Supplied.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
41	Maruti Gupta, Satyajit Grover, Suresh Singh	A Feasibility Study for Power Management in LAN Switches.	ICNP	2004	DBLP DOI BibTeX RDF
41	Claus Bauer	Distributed Scheduling Policies for Networks of Switches with a Configuration Overhead.	ICOIN	2004	DBLP DOI BibTeX RDF
41	Luís G. C. Cancela, João J. O. Pires	Crosstalk Effects in Large Strictly Non-blocking Optical Switches Based on Directional Couplers.	HSNMC	2003	DBLP DOI BibTeX RDF
39	Sundar Iyer, Ramana Rao Kompella, Nick McKeown	Designing packet buffers for router linecards.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	hit-rate, line-card, cache, memory hierarchy, router, switches, packet buffer
39	Cheng-Shang Chang, Yi-Ting Chen, Duan-Shin Lee	Constructions of optical FIFO queues.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF	first-in-first-out (FIFO) queues, optical memory, switched delay lines (SDLs), optical switches, Clos networks
39	Koji M. Kobayashi, Shuichi Miyazaki, Yasuo Okabe	Competitive buffer management for multi-queue switches in qos networks using packet buffering algorithms.	SPAA	2009	DBLP DOI BibTeX RDF	multi-queue switches, competitive analysis, buffer management
39	Madhusudan Hosaagrahara, Harish Sethu	Degree-sequenced matching algorithms for input-queued switches.	Telecommun. Syst.	2007	DBLP DOI BibTeX RDF	Scheduling and matching algorithms, Input-queued switches
39	Koji M. Kobayashi, Shuichi Miyazaki, Yasuo Okabe	A tight bound on online buffer management for two-port shared-memory switches.	SPAA	2007	DBLP DOI BibTeX RDF	shared memory switches, competitive analysis, buffer management
39	Lin Liu 0004, Yuanyuan Yang 0001	Optimal packet scheduling in output-buffered optical switches with limited-range wavelength conversion.	ANCS	2007	DBLP DOI BibTeX RDF	WDM optical switches, minimum cost maximum flow, output-queued (OQ), packet scheduling, wavelength conversion
39	Choudhury A. Al Sayeed, Ashraf Matrawy	Guaranteed Maximal Matching for Input Buffered Crossbar Switches.	CNSR	2006	DBLP DOI BibTeX RDF	Guaranteed maximal matching, iSLIP, MWM, scheduling, perfect matching, crossbar switches
39	Giuseppe Ascia, Vincenzo Catania, Daniela Panno	An evolutionary management scheme in high-performance packet switches.	IEEE/ACM Trans. Netw.	2005	DBLP DOI BibTeX RDF	genetic algorithm, fuzzy logic, shared-memory, packet switches, buffer management
39	Brian Towles, William J. Dally	Guaranteed scheduling for switches with configuration overhead.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	packet switching, optical switches
39	Emilio Leonardi, Marco Mellia, Fabio Neri, Marco Ajmone Marsan	Bounds on delays and queue lengths in input-queued cell switches.	J. ACM	2003	DBLP DOI BibTeX RDF	scheduling, Performance evaluation, delay bounds, input queued switches
36	Der-Rong Din	A Heuristic Algorithm for Solving the Network Expanded Problem on Wireless ATM Environment.	ICCSA (1)	2007	DBLP DOI BibTeX RDF	network expanded problem, cell assignment problem, cell splitting, Heuristic algorithm, wireless ATM
36	Gaspar Mora, Pedro Javier García, José Flich, José Duato	RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management.	ICPP	2007	DBLP DOI BibTeX RDF
36	Der-Rong Din	Simulated Annealing Algorithm for Solving Network Expanded Problem in Wireless ATM Network.	IEA/AIE	2007	DBLP DOI BibTeX RDF
36	Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani	A Network on Chip Architecture and Design Methodology.	ISVLSI	2002	DBLP DOI BibTeX RDF	System on Chip, IP, Platform based design, On-chip communication
35	Helmut Hlavacs, Georges Da Costa, Jean-Marc Pierson	Energy Consumption of Residential and Professional Switches.	CSE (1)	2009	DBLP DOI BibTeX RDF
35	Jian Wang, Ted H. Szymanski	Power analysis of Input-Queued and Crosspoint-Queued crossbar switches.	CCECE	2009	DBLP DOI BibTeX RDF
35	Ziqian Dong, Roberto Rojas-Cessa	Input- and Output-Based Shared-Memory Crosspoint-Buffered Packet Switches for Multicast Traffic Switching and Replication.	ICC	2008	DBLP DOI BibTeX RDF
35	Deng Pan, Yuanyuan Yang 0001	Max-Min Fair Bandwidth Allocation Algorithms for Packet Switches.	IPDPS	2007	DBLP DOI BibTeX RDF
35	Norbert Eicker, Thomas Lippert	Scalable Ethernet Clos-Switches.	Euro-Par	2006	DBLP DOI BibTeX RDF
35	Marina Alonso, Juan-Miguel Martínez 0001, Vicente Santonja, Pedro López 0001, José Duato	Power Saving in Regular Interconnection Networks Built with High-Degree Switches.	IPDPS	2005	DBLP DOI BibTeX RDF
35	David Elata, Vitaly Leus	Switching time, impact velocity and release response, of voltage and charge driven electrostatic switches.	ICMENS	2005	DBLP DOI BibTeX RDF
35	Deng Pan, Yuanyuan Yang	Pipelined two step iterative matching algorithms for CIOQ crossbar switches.	ANCS	2005	DBLP DOI BibTeX RDF	scheduling, pipeline, convergence, iterative algorithms
35	Saswati Sarkar	Optimum scheduling and memory management in input queued switches with finite buffer space.	IEEE Trans. Inf. Theory	2004	DBLP DOI BibTeX RDF
35	Chun Kit Hung, Mounir Hamdi, Chi-Ying Tsui	Design and implementation of high-speed arbiter for large scale VOQ crossbar switches.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
35	Shashank Gupta, Adnan Aziz	Multicast Scheduling for Switches with Multiple Input-Queues.	Hot Interconnects	2002	DBLP DOI BibTeX RDF
35	Deshanand P. Singh, Stephen Dean Brown	The case for registered routing switches in field programmable gate arrays.	FPGA	2001	DBLP DOI BibTeX RDF
35	Aristotel Tentov	Performance Analysis of ATM Switches with Multistage Multipath Packet Switching Interconnection Networks.	LCN	1997	DBLP DOI BibTeX RDF
35	Jaehyung Park, Hyunsoo Yoon, Jung Wan Cho	Novel algorithms for multicast communication in self-routing MIN-based ATM switches.	ICNP	1996	DBLP DOI BibTeX RDF
33	Aditya Agrawal, Anand Raju, Sachidanand Varadarajan, Magdy A. Bayoumi	A scalable shared buffer ATM switch architecture.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access
33	Aleksandra Smiljanic	Rate and delay guarantees provided by Clos packet switches with load balancing.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	scalability, performance analysis, packet switches, non-blocking, internet routers, delay guarantees
33	Simin He 0001, Shutao Sun, Hong-Tao Guan, Qiang Zheng, Youjian Zhao, Wen Gao 0001	On guaranteed smooth switching for buffered crossbar switches.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	scheduling, smoothness, switches, buffered crossbar
33	Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.	ASP-DAC	2007	DBLP DOI BibTeX RDF	reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current
33	Zhizhong Zhang, Fang Cheng, Jiangtao Luo, Qijian Mao, Jun Wang, Shaofeng Qiu	Preemptive and non-preemptive scheduling of optical switches with configuration delay.	Sci. China Ser. F Inf. Sci.	2006	DBLP DOI BibTeX RDF	configuration delay, scheduling, optical switches
33	Md. Mamun-ur-Rashid Khandker, Xiaohong Jiang 0001, Pin-Han Ho, Susumu Horiguchi, Hussein T. Mouftah	Performance of Fast Routing Algorithms in Large Optical Switches Built on the Vertical Stacking of Banyan Structures.	Clust. Comput.	2004	DBLP DOI BibTeX RDF	vertically stacked switches, banyan networks, self-routing, optical switch networks
33	Dan Guez, Alexander Kesselman, Adi Rosén	Packet-mode policies for input-queued switches.	SPAA	2004	DBLP DOI BibTeX RDF	packet-mode scheduling, competitive analysis, input-queued switches
33	Marco Ajmone Marsan, Andrea Bianco, Paolo Giaccone, Emilio Leonardi, Fabio Neri	Multicast traffic in input-queued switches: optimal scheduling and maximum throughput.	IEEE/ACM Trans. Netw.	2003	DBLP DOI BibTeX RDF	scheduling, switching, input queued switches, multicast traffic
33	José G. Delgado-Frias, Richard Diaz	A VLSI Self-Compacting Buffer for DAMQ Communication Switches.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	dynamically allocated multi-queue, Communication buffer management, VLSI, Communication Switches
33	George Thomas, Venkateswar Veludandi	ATM switches with bifurcated input queueing.	ICCCN	1997	DBLP DOI BibTeX RDF	bifurcated input queueing, average cell delay, uncorrelated traffic, correlated traffic, performance, asynchronous transfer mode, throughput, upper bound, ATM switches, simulation study
33	Itsuo Takanami, Tadayoshi Horita	Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.	DFT	1997	DBLP DOI BibTeX RDF	self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays
33	Debashis Basak, Abhijit K. Choudhury, Ellen L. Hahne	Sharing memory in multistage ATM switches.	ICCCN	1995	DBLP DOI BibTeX RDF	multistage ATM switches, shared-memory switching elements, banyan topology, output queueing, local cell buffer memory, buffer management technique, delayed pushout, backpressure mechanism, telecommunication traffic, bursty traffic, load conditions
33	Hong Shi, Naeem Abbasi, Charles A. Zukowski, Omar Wing	Buffer size trade-offs in input/output buffered ATM switches under various conditions.	ICCCN	1995	DBLP DOI BibTeX RDF	buffer size trade-offs, input/output buffered ATM switches, nonlinear complex relationship, average packet delay, speed-up factors, VLSI design, telecommunication traffic, packet loss probability, traffic conditions
31	Yuh-Ren Tsai, Che-Wei Lo	Banyan-based Architecture for Quasi-Circuit Switching.	ICNS	2006	DBLP DOI BibTeX RDF	Birkhoff-von Neumann Switches, Quasi-circuit Switching, Multi-stage Switches, Packet Delay Control, Quality of Services
31	Wen-mei W. Hwu, Thomas M. Conte	The Susceptibility of Programs to Context Switching.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	program susceptibility, memory system performance degradation, single-pass method, recurrence/conflict model, voluntary context switches, involuntary context switches, length distribution, address referencing, cache flushing, SPEC89 benchmarks, simulation, performance evaluation, performance analysis, memory hierarchy, cache memories, memory architecture, buffer storage, multiprogramming, multiprogramming, design space, context switching
30	Po-Kai Huang, Cheng-Shang Chang, Jay Cheng, Duan-Shin Lee	Recursive Constructions of Parallel FIFO and LIFO Queues With Switched Delay Lines.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
30	Timo Schönwald, Jochen Zimmermann, Oliver Bringmann 0001, Wolfgang Rosenstiel	Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures.	DSD	2007	DBLP DOI BibTeX RDF
30	Sathish Gopalakrishnan, Marco Caccamo, Lui Sha	Switch Scheduling and Network Design for Real-Time Systems.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
30	Roberto Rojas-Cessa, Eiji Oki, H. Jonathan Chao	On the combined input-crosspoint buffered switch with round-robin arbitration.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
30	Yuanyuan Yang 0001, Jianchao Wang	Fault-Tolerant Rearrangeable Permutation Network.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	losing-contact fault, Fault tolerance, routing, cluster computing, fault model, permutation, switching networks, Clos networks, rearrangeable
30	Somdip Datta, Subir K. Biswas, Sudipta Sengupta, Debanjan Saha	Routing and Grooming in Two-Tier Survivable Optical Mesh Networks.	IWQoS	2003	DBLP DOI BibTeX RDF
30	O. Kibar, Philippe J. Marchand, Sadik C. Esener	High-speed CMOS switch designs for free-space optoelectronic MIN's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
30	Avrim Blum, Prasad Chalasani	Learning Switching Concepts.	COLT	1992	DBLP DOI BibTeX RDF
29	Amir Gourgy, Ted H. Szymanski	Cooperative Token-Ring Scheduling For Input-Queued Switches.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
29	Lotfi Mhamdi	On the Integration of Unicast and Multicast Cell Scheduling in Buffered Crossbar Switches.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
29	Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar	Complementary nano-electromechanical switches for ultra-low power embedded processors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	nems, cmos, switch, device, ultra-low power
29	Masaki Yamada, Takeki Yazaki, Shinji Nishimura, Naoya Ikeda	Technologies to Save Power for Carrier Class Routers and Switches.	SAINT	2008	DBLP DOI BibTeX RDF	Optical backplane
29	Hans Eberle, Pedro Javier García, José Flich, José Duato, Robert J. Drost, Nils Gura, David Hopkins 0001, Wladek Olesinski	High-radix crossbar switches enabled by proximity communication.	SC	2008	DBLP DOI BibTeX RDF
29	Yong Lee 0003, Jianyu Lou, Junzhou Luo, Xiaojun Shen 0002	An efficient packet scheduling algorithm with deadline guarantees for input-queued switches.	IEEE/ACM Trans. Netw.	2007	DBLP DOI BibTeX RDF	quality of service, real time scheduling, network flow, packet scheduling, input-queued switch
29	Can Emre Koksal	An Analysis of Blocking Switches Using Error Control Codes.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
29	Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes 0001	MOTIM - A Scalable Architecture for Ethernet Switches.	ISVLSI	2007	DBLP DOI BibTeX RDF
29	Yossi Azar, Yossi Richter	An improved algorithm for CIOQ switches.	ACM Trans. Algorithms	2006	DBLP DOI BibTeX RDF	CIOQ, competitive, switch, Qos, on-line