Search results for "virtex-e"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
46	S. Sukhsawas, Khaled Benkrid	A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs.	ISVLSI	2004	DBLP DOI BibTeX RDF
33	Tomasz S. Czajkowski, Jonathan Rose	A synthesis oriented omniscient manual editor.	FPGA	2004	DBLP DOI BibTeX RDF	virtex-e, synthesis, manual
33	Neil Steiner, Peter M. Athanas	An Alternate Wire Database for Xilinx FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
29	Mamoun F. Al-Mistarihi	Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA.	FPL	2008	DBLP DOI BibTeX RDF
24	Pramod Kumar Meher, Jagdish Chandra Patra	Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform.	ASAP	2008	DBLP DOI BibTeX RDF
24	Roar Lien, Tim Grembowski, Kris Gaj	A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512.	CT-RSA	2004	DBLP DOI BibTeX RDF
24	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
24	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.	FCCM	2003	DBLP DOI BibTeX RDF
16	William N. Chelton, Mohammed Benaissa	Fast Elliptic Curve Cryptography on FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Ian Kuon, Aaron Egier, Jonathan Rose	Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
16	Erik Chmelar	Subframe multiplexing for FPGA manufacturing test configuration.	FPGA	2004	DBLP DOI BibTeX RDF
16	Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä	A fully pipelined memoryless 17.8 Gbps AES-128 encryptor.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, pipelining, advanced encryption standard (AES)
16	Jean-Luc Beuchat	FPGA Implementations of the RC6 Block Cipher.	FPL	2003	DBLP DOI BibTeX RDF
16	Jean-Luc Beuchat	Modular Multiplication for FPGA Implementation of the IDEA Block Cipher.	ASAP	2003	DBLP DOI BibTeX RDF
16	Máire McLoone, John V. McCanny	Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm.	FPL	2001	DBLP DOI BibTeX RDF	Encryption, AES, Rijndael, FPGA Implementation
16	Máire McLoone, John V. McCanny	High Performance Single-Chip FPGA Rijndael Algorithm Implementations.	CHES	2001	DBLP DOI BibTeX RDF	Encryption, AES, Rijndael, FPGA Implementation
8	Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira	FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
8	Issam W. Damaj	Higher-Level Hardware Synthesis of the KASUMI Algorithm.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	parallel algorithms, methodology, formal models, data encryption, gate array
8	Issam W. Damaj	Parallel Algorithms Development for Programmable Devices with Application from Cryptography.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	Parallel algorithms, methodologies, formal models, data encryption, gate array
8	Jaime Jimenez, José Luis Martín 0001, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias	Comparison of two designs for the multifunction vehicle bus.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
8	William N. Chelton, Mohammed Benaissa	High-Speed Pipelined EGG Processor on FPGA.	SiPS	2006	DBLP DOI BibTeX RDF
8	James Moscola, Young H. Cho, John W. Lockwood	Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices.	FPL	2006	DBLP DOI BibTeX RDF
8	Li Wang, Youren Wang, Rui Yao, Zhai Zhang	Hardware Implementation of AES Based on Genetic Algorithm.	ICNC (2)	2006	DBLP DOI BibTeX RDF
8	Sherif M. Saif, Hazem M. Abbas, Salwa M. Nassar	An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization.	IJCNN	2006	DBLP DOI BibTeX RDF
8	Thomas W. Fry, Scott Hauck	SPIHT image compression on FPGAs.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
8	Shrutisagar Chandrasekaran, Abbes Amira	An area efficient low power inner product computation for discrete orthogonal transforms.	ICIP (3)	2005	DBLP DOI BibTeX RDF
8	Alessandro Cilardo, Antonino Mazzeo, Luigi Romano	An FPGA-based Key-Store for Improving the Dependability of Security Services.	WORDS	2005	DBLP DOI BibTeX RDF
8	Wai-Kei Mak	I/O placement for FPGAs with multiple I/O standards.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
8	Bret Woz, Andreas E. Savakis	A VHDL MPEG-7 shape descriptor extractor.	FPGA	2004	DBLP DOI BibTeX RDF
8	Dimitris G. Bariamis, Dimitrios K. Iakovidis, Dimitrios E. Maroulis, S. A. Karkanis	An FPGA-Based Architecture for Real Time Image Feature Extraction.	ICPR (1)	2004	DBLP DOI BibTeX RDF
8	Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater	Efficient Modular Division Implementation: ECC over GF(p) Affine Coordinates Application.	FPL	2004	DBLP DOI BibTeX RDF
8	Norbert Pramstaller, Johannes Wolkerstorfer	A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays.	FPL	2004	DBLP DOI BibTeX RDF
8	Wai-Kei Mak	I/O placement for FPGAs with multiple I/O standards.	FPGA	2003	DBLP DOI BibTeX RDF	I/O placement, I/O standards, field-programmable gate array, placement
8	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
8	Abdsamad Benkrid, Danny Crookes, Khaled Benkrid	Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA.	FPGA	2003	DBLP DOI BibTeX RDF
8	Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid	An FPGA-Based Image Connected Component Labeller.	FPL	2003	DBLP DOI BibTeX RDF
8	Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo	An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm.	FPL	2003	DBLP DOI BibTeX RDF
8	Janette Frigo, David Palmer 0006, Maya B. Gokhale, Marc Popkin-Paine	Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware.	FCCM	2003	DBLP DOI BibTeX RDF
8	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA.	FCCM	2003	DBLP DOI BibTeX RDF
8	Sanat Kamal Bahl	Design and Prototyping a Fast Hadamard Transformer for WCDMA.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
8	François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat	Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs.	CHES	2003	DBLP DOI BibTeX RDF
8	William Chow, Jonathan Rose	EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits.	FPGA	2002	DBLP DOI BibTeX RDF	event horizon, manual placement and pipelining, FPGA, programmable logic
8	Miguel Arias-Estrada, Eduardo Rodríguez-Palacios	An FPGA Co-processor for Real-Time Visual Tracking.	FPL	2002	DBLP DOI BibTeX RDF
8	Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo	A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations.	FPL	2002	DBLP DOI BibTeX RDF
8	Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert 0001	Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations.	FPL	2002	DBLP DOI BibTeX RDF
8	Tomoyoshi Kobori, Tsutomu Maruyama	High Speed Computation of Three Dimensional Cellular Automata with FPGA.	FPL	2002	DBLP DOI BibTeX RDF
8	Antti Hämäläinen, Matti Tommiska, Jorma Skyttä	8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm.	FPL	2002	DBLP DOI BibTeX RDF
8	Thomas W. Fry, Scott Hauck	Hyperspectral Image Compression on Reconfigurable Platforms.	FCCM	2002	DBLP DOI BibTeX RDF