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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1164 occurrences of 399 keywords
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Results
Found 1149 publication records. Showing 1149 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
125 | Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer |
Energy-conscious compilation based on voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 2-11, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
energy-aware compilation, optimizing compilers, voltage scaling, loop transformations |
109 | Huizhan Yi, Xuejun Yang |
Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 79-88, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
92 | Le Yan, Lin Zhong 0001, Niraj K. Jha |
User-perceived latency driven voltage scaling for interactive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 624-627, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
adaptive body biasing, computer responsiveness, dynamic voltage scaling, power consumption |
84 | Weixun Wang, Prabhat Mishra 0001 |
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 705-710, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
real-time systems, approximation algorithm, dynamic voltage scaling, energy-aware scheduling |
82 | Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou |
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 381-386, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
stochastic gradient search, scheduling, optimization, power management, dynamic voltage scaling (DVS), heterogeneous systems, multi-processor systems |
80 | Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner |
Theoretical and practical limits of dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 868-873, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
minimum energy point, dynamic voltage scaling |
80 | Seung Woo Son 0001, Konrad Malkowski, Guilin Chen, Mahmut T. Kandemir, Padma Raghavan |
Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 41(3), pp. 179-213, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Parallel sparse matrix, Computation, Dynamic voltage scaling, Communication networks, Energy consumption |
77 | Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner |
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1239-1252, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
76 | Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu |
Collaborative voltage scaling with online STA and variable-latency datapath. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 347-352, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
collaborative voltage scaling, online STA, variable-latency datapath, adaptive voltage scaling |
72 | Saowanee Saewong, Ragunathan Rajkumar |
Practical Voltage-Scaling for Fixed-Priority RT-Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: Proceedings of the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2003), May 27-30, 2003, Toronto, Canada, pp. 106-, 2003, IEEE Computer Society, 0-7695-1956-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
70 | Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg |
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 147-160, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
memory technology, dynamic voltage scaling, DRAM, molecular electronics, molecular memory, low-power memory |
68 | Jiong Luo, Niraj K. Jha, Li-Shiuan Peh |
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 427-437, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
68 | Huizhan Yi, Xuejun Yang, Juan Chen 0001 |
The Optimal Profile-Guided Greedy Dynamic Voltage Scaling in Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 708-719, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
66 | Mongkol Ekpanyapong, Sung Kyu Lim |
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 142-148, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
supply and threshold voltage scaling, low power design, retiming |
63 | Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree |
A Robust Level-Shifter Design for Adaptive Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 383-388, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
63 | Taewhan Kim |
Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 16-18 August 2006, Sydney, Australia, pp. 199-206, 2006, IEEE Computer Society, 0-7695-2676-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
63 | Eduardo Tavares, Paulo Romero Martins Maciel, Bruno Silva 0001, Meuse N. Oliveira Jr. |
A time petri net-based approach for hard real-time systems scheduling considering dynamic voltage scaling, overheads, precedence and exclusion relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 312-317, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
petri nets, dynamic voltage scaling, formal models, hard real-time systems |
63 | Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler |
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001, pp. 243-248, 2001, ACM, 1-58113-364-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
simulated heating, dynamic voltage scaling |
63 | Xiliang Zhong, Cheng-Zhong Xu 0001 |
Energy-Aware Modeling and Scheduling for Dynamic Voltage Scaling with Statistical Real-Time Guarantee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(3), pp. 358-372, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Real-time systems, dynamic voltage scaling, dynamic power management, power-aware scheduling |
62 | Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg |
A case for dynamic pipeline scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 1-8, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating |
62 | Yann-Hang Lee, Yoonmee Doh, C. Mani Krishna 0001 |
EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 221-228, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
dynamic reclaiming, energy and power optimization, scheduling, real-time systems, voltage scaling |
62 | Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob |
A control-theoretic approach to dynamic voltage scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 255-266, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
nqPID, low-power, dynamic voltage scaling, PID |
59 | Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi |
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 514-519, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
59 | Huizhan Yi, Xuejun Yang |
Toward the Optimal Configuration of Dynamic Voltage Scaling Points in Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(6), pp. 893-900, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
languages and compilers, low-power design, energy-aware systems |
59 | Seung Woo Son 0001, Konrad Malkowski, Guilin Chen, Mahmut T. Kandemir, Padma Raghavan |
Integrated link/CPU voltage scaling for reducing energy consumption of parallel sparse matrix applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
59 | Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi |
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 362-369, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
55 | Yu-Wei Yang, Katherine Shu-Min Li |
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 49-54, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
55 | Sylvain Miermont, Pascal Vivet, Marc Renaudin |
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 556-565, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Hai Li, Chen-Yong Cher, Kaushik Roy 0001, T. N. Vijaykumar |
Combined circuit and architectural level variable supply-voltage scaling for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(5), pp. 564-576, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
55 | K. Shyam, R. Govindarajan |
Compiler-Directed Dynamic Voltage Scaling Using Program Phases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 233-244, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
55 | Noureddine Chabini, Wayne H. Wolf |
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(6), pp. 573-589, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
55 | Yifan Zhu, Frank Mueller 0001 |
Feedback EDF Scheduling of Real-Time Tasks Exploiting Dynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 31(1-3), pp. 33-63, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, real-time systems, dynamic voltage scaling, feedback control |
55 | Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo |
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 84-87, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
variable supply voltage, low power, finite state machine, dynamic voltage scaling, formal model, synchronous dataflow |
55 | Albert Mo Kim Cheng, Yan Wang |
A Dynamic Voltage Scaling Algorithm for Dynamic Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(1), pp. 45-57, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dynamic workloads, scheduling, real-time systems, dynamic voltage scaling (DVS), power-aware computing |
54 | Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge |
Reducing pipeline energy demands with local DVS and dynamic retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 319-324, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dynamic retiming with global DVS, local DVS, razor |
54 | Kiyoo Itoh 0001 |
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 273-274, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet |
53 | Sanjeev Baskiyar, Kiran Kumar Palli |
Low Power Scheduling of DAGs to Minimize Finish Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2006, 13th International Conference, Bangalore, India, December 18-21, 2006, Proceedings, pp. 353-362, 2006, Springer, 3-540-68039-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Scheduling, Power, Heterogeneous, DAG, Makespan, Voltage Scaling |
53 | E. N. Elnozahy, Michael Kistler, Ramakrishnan Rajamony |
Energy-Efficient Server Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers, pp. 179-196, 2002, Springer, 3-540-01028-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Clusters, Power Management, Web Servers, Voltage Scaling |
53 | Nevine AbouGhazaleh, Daniel Mossé, Bruce R. Childers, Rami G. Melhem |
Collaborative operating system and compiler power management for real-time applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(1), pp. 82-115, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
collaborative OS and compiler, voltage scaling points placement, Real-time, power-management, dynamic voltage scaling |
51 | Jiong Luo, Niraj K. Jha |
Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 679-692, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Mohamed Elgebaly, Manoj Sachdev |
Variation-Aware Adaptive Voltage Scaling System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(5), pp. 560-571, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Xiliang Zhong, Cheng-Zhong Xu 0001 |
Energy-Aware Modeling and Scheduling of Real-Time Tasks for Dynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 26th IEEE Real-Time Systems Symposium (RTSS 2005), 6-8 December 2005, Miami, FL, USA, pp. 366-375, 2005, IEEE Computer Society, 0-7695-2490-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Yifan Zhu, Frank Mueller 0001 |
Feedback EDF scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 203-212, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, real-time systems, dynamic voltage scaling, feedback control |
51 | Fen Xie, Margaret Martonosi, Sharad Malik |
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(3), pp. 323-367, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low power, compiler, Analytical model, dynamic voltage scaling, mixed-integer linear programming |
51 | Jacob R. Lorch, Alan Jay Smith |
Using User Interface Event Information in Dynamic Voltage Scaling Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 11th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2003), 12-15 October 2003, Orlando, FL, USA, pp. 46-55, 2003, IEEE Computer Society, 0-7695-2039-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Workload characterization and generation, power management, dynamic voltage scaling, response time, modeling and simulation, energy management |
51 | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
An interconnect-aware delay model for dynamic voltage scaling in NM technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 45-50, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic voltage scaling (dvs), interconnects, delay model |
51 | Jianfeng Mao, Christos G. Cassandras, Qianchuan Zhao |
Optimal Dynamic Voltage Scaling in Energy-Limited Nonpreemptive Systems with Real-Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 6(6), pp. 678-688, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nonpreemptive, sensor networks, optimal control, voltage scaling, Hard real-time system |
51 | Yu-Hang Tsai, Kuochen Wang, Jheng-Ming Chen |
A deferred-workload-based inter-task dynamic voltage scaling algorithm for portable multimedia devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing, IWCMC 2007, Honolulu, Hawaii, USA, August 12-16, 2007, pp. 677-682, 2007, ACM, 978-1-59593-695-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
actual workload, deferred-workload-based, inter-task dynamic voltage scaling, worst-case execution time, hard real-time system, slack time |
51 | Mohamed Elgebaly, Manoj Sachdev |
Efficient adaptive voltage scaling system through on-chip critical path emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 375-380, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low-power, CMOS, adaptive voltage scaling |
49 | Eric Karl, Dennis Sylvester, David T. Blaauw |
Timing error correction techniques for voltage-scalable on-chip memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3563-3566, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Noohul Basheer Zain Ali, Mark Zwolinski, Bashir M. Al-Hashimi, Peter Harrod |
Dynamic Voltage Scaling Aware Delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 15-20, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Youngjin Cho, Younghyun Kim 0001, Naehyuck Chang |
PVS: passive voltage scaling for wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 135-140, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded system, low-power, wireless, DVS, PVS, sensor node |
47 | Ramkumar Jayaseelan, Tulika Mitra |
Temperature aware task sequencing and voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 618-623, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | N. Ranganathan, Ashok K. Murugavel |
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 276-281, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Yifan Zhu, Frank Mueller 0001 |
DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 31-40, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
scheduling, real-time systems, dynamic voltage scaling, leakage, feedback control |
47 | Haklin Kimm, Sung Y. Shin, Chang Oan Sung |
Evaluation of interval-based dynamic voltage scaling algorithms on mobile Linux system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 2007, pp. 1141-1145, 2007, ACM, 1-59593-480-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dynamic voltage scaling algorithm, mobile Linux system, scheduling |
47 | Woonseok Kim, Jihong Kim 0001, Sang Lyul Min |
Preemption-aware dynamic voltage scaling in hard real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 393-398, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
real-time systems, dynamic voltage scaling, low-power systems |
47 | Fen Xie, Margaret Martonosi, Sharad Malik |
Compile-time dynamic voltage scaling settings: opportunities and limits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, San Diego, California, USA, June 9-11, 2003, pp. 49-62, 2003, ACM, 1-58113-662-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low power, compiler, analytical model, dynamic voltage scaling, mixed-integer linear programming |
47 | Woonseok Kim, Jihong Kim 0001, Sang Lyul Min |
Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 396-401, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
real-time systems, dynamic voltage scaling, low-power systems |
47 | Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria |
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 221-224, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
supply voltage scaling, performance, power consumption, CMOS, retiming, digital design |
47 | Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda |
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 483-488, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian |
45 | Brian Foo, Mihaela van der Schaar |
A Queuing Theoretic Approach to Processor Power Adaptation for Video Decoding Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(1), pp. 378-392, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Diana Marculescu |
Application adaptive energy efficient clustered architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 344-349, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dynamic voltage scaling, clustered architectures |
45 | Lee Kee Goh, Bharadwaj Veeravalli, Sivakumar Viswanathan |
An Energy-Aware Gradient-Based Scheduling Heuristic for Heterogeneous Multiprocessor Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 331-341, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, power management, dynamic voltage scaling, Energy-aware scheduling, heterogeneous multiprocessor |
45 | Rony Ghattas, Alexander G. Dean |
Energy management for commodity short-bit-width microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 32-42, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic frequency scaling, short-bit-width microcontroller, embedded systems, dynamic voltage scaling, energy modeling |
45 | Anoop Iyer, Diana Marculescu |
Power efficiency of voltage scaling in multiple clock, multiple voltage cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 379-386, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Lin Yuan, Gang Qu 0001 |
Analysis of energy reduction on dynamic voltage scaling-enabled systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12), pp. 1827-1837, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Jungseob Lee, Nam Sung Kim |
Optimizing total power of many-core processors considering voltage scaling limit and process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 201-206, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
voltage and frequency scaling, process variations, parallel applications, many-core processor |
43 | Animesh Kumar, Jan M. Rabaey, Kannan Ramchandran |
SRAM supply voltage scaling: A reliability perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 782-787, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li 0001 |
Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8), pp. 1467-1478, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Emrah Akyol, Mihaela van der Schaar |
Complexity Model Based Proactive Dynamic Voltage Scaling for Video Decoding Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multim. ![In: IEEE Trans. Multim. 9(7), pp. 1475-1492, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Emrah Akyol, Mihaela van der Schaar |
Buffer Constrained Proactive Dynamic Voltage Scaling for Video Decoding Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (6) ![In: Proceedings of the International Conference on Image Processing, ICIP 2007, September 16-19, 2007, San Antonio, Texas, USA, pp. 477-480, 2007, IEEE, 978-1-4244-1436-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Grigorios Magklis, Pedro Chaparro, José González 0002, Antonio González 0001 |
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 49-54, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
MCD, energy efficiency, DVS, microarchitecture, GALS |
43 | Johan A. Pouwelse, Koen Langendoen, Henk J. Sips |
Application-directed voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 812-826, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy 0001 |
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 19-28, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Chingwei Yeh, Yin-Shuin Kang |
Cell-based layout techniques supporting gate-level voltage scaling for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 983-986, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Chingwei Yeh, Yin-Shuin Kang |
Cell-based layout techniques supporting gate-level voltage scaling for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 629-633, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo |
Energy-efficiency for multiframe real-time tasks on a dynamic voltage scaling processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 211-220, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multiframe real-time tasks, dynamic voltage scaling, energy-aware systems, energy-efficient scheduling |
43 | Ahron Yang, Minseok Song 0001 |
Aggressive dynamic voltage scaling for energy-aware video playback based on decoding time estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 9th ACM & IEEE International conference on Embedded software, EMSOFT 2009, Grenoble, France, October 12-16, 2009, pp. 1-10, 2009, ACM, 978-1-60558-627-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
media players, dynamic voltage scaling, real-time embedded systems, low-power systems |
43 | Vinay Devadas, Hakan Aydin |
On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 8th ACM & IEEE International conference on Embedded software, EMSOFT 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 99-108, 2008, ACM, 978-1-60558-468-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
real-time systems, dynamic voltage scaling, energy management, dynamic power management |
43 | Zhen Cao, Brian Foo, Lei He 0001, Mihaela van der Schaar |
Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 179-184, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multimedia, power management, dynamic voltage scaling |
43 | Ruibin Xu, Daniel Mossé, Rami G. Melhem |
Minimizing expected energy consumption in real-time systems through dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 25(4), pp. 9, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
processor acceleration to conserve energy, Real-time, power management, dynamic voltage scaling |
43 | Jian-Jia Chen, Tei-Wei Kuo |
Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 289-294, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
job procrastination, leakage-aware scheduling, scheduling, dynamic voltage scaling, energy-aware systems |
43 | Jian-Jia Chen, Tei-Wei Kuo |
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario, Canada, June 14-16, 2006, pp. 153-162, 2006, ACM, 1-59593-362-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
leakage-aware scheduling, scheduling, dynamic voltage scaling, fixed-priority scheduling, energy-aware systems, rate-monotonic scheduling |
43 | Changjiu Xian, Yung-Hsiang Lu |
Dynamic voltage scaling for multitasking real-time systems with uncertain execution time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 392-397, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
probability, dynamic voltage scaling, multitasking, low energy, hard real-time |
43 | Hyung Sun Lee, Byung Kook Kim |
Dynamic Voltage Scaling for Digital Control System Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 29(2-3), pp. 263-280, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic voltage scaling, Real-time control, control performance, digital control system |
43 | Ivan Matosevic, Tarek S. Abdelrahman, Faraydon Karim, Alain Mellan |
Power Optimization for the MLCA Using Dynamic Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29 - October 1, 2005, pp. 109-123, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
compiler techniques for power, parallel-embedded systems, dynamic voltage scaling, multimedia applications, power optimizations |
43 | Sookyoung Kim, Thomas L. Martin |
DIP: a double-interval-based dynamic voltage scaling scheme for dynamic priority-based task scheduling systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 226-231, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dynamic priority-based task scheduling systems, dynamic voltage scaling, low energy |
43 | Eui-Young Chung, Giovanni De Micheli, Luca Benini |
Contents provider-assisted dynamic voltage scaling for low energy multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 42-47, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DVS(Dynamic Voltage Scaling), contents provider, multimedia, low-power, worst case execution time, characterization |
41 | Jiong Luo, Niraj K. Jha |
Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), pp. 1161-1170, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Noureddine Chabini, Wayne H. Wolf |
An approach for reducing dynamic power consumption in synchronous sequential digital designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 198-204, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke |
Enabling ultra low voltage system operation by tolerating on-chip cache failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 307-310, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fault-tolerant cache, low voltage operation, dynamic voltage scaling |
41 | Hong Jin, Danli Wang, Hongan Wang, Henry (Hui) Wang |
Feedback fuzzy-DVS scheduling of control tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 41(2), pp. 147-162, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Control task, Scheduling, Dynamic voltage scaling, Feedback control, Fuzzy rule |
41 | Yongseok Choi, Naehyuck Chang, Taewhan Kim |
DC-DC converter-aware power management for battery-operated embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 895-900, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, voltage scaling, DC-DC converter |
41 | Jian-Liang Kuo, Tien-Fu Chen |
Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 147-155, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
real-time systems, low power, dynamic voltage scaling |
41 | Heiner Giefers, Achim Rettberg |
Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 113-118, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high-level synthesis, low power design, voltage scaling, bit-serial architecture |
41 | A. Goel, C. Mani Krishna 0001, Israel Koren |
Energy aware kernel for hard real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 185-190, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded system, dynamic voltage scaling, earliest deadline first, real-time operating system, eCos |
41 | C. Mani Krishna 0001, Yann-Hang Lee |
Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(12), pp. 1586-1593, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
real-time systems, dynamic voltage scaling, Power-aware computing |
41 | Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas |
The BubbleWrap many-core: popping cores for sequential acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 447-458, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
power wall, process scaling, processor aging, voltage scaling |
41 | Ajay Dudani, Frank Mueller 0001, Yifan Zhu |
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 213-222, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scheduling, real-time systems, dynamic voltage scaling |
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