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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 30 occurrences of 30 keywords
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Results
Found 81 publication records. Showing 81 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
117 | Matt T. Yourst |
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 23-34, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
client-server networked benchmark, PTLsim, cycle accurate full system, x86-64 microarchitectural simulator, superscalar x86-64 processor core, full-speed native execution, microarchitectural simulators, x86 ISA, microoperation level, multiprocessor capable simulation, Xen hypervisor, AMD Athlon 64 machine, virtual machine |
63 | Dong Ye 0004, Joydeep Ray, Christophe Harle, David R. Kaeli |
Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC 2006, October 25-27, 2006, San Jose, California, USA, pp. 120-127, 2006, IEEE Computer Society, 1-4244-0508-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Yoshiyuki Yamashita, Masato Tsuru |
Implementing Fast Packet Filters by Software Pipelining on x86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 420-435, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel |
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 413-422, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Nehalem, Shanghai, benchmark, multi-core, coherency |
23 | Pat Conway, Nathan Kalyanasundharam, Gregg Donley, Kevin Lepak, Bill Hughes |
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 30(2), pp. 16-29, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
x86-64, cache directory, probe filter, system interconnect, HyperTransport3 technology, power envelopes, cache, multiprocessor, memory hierarchy, processor, blade server |
22 | Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev |
MPTLsim: a simulator for X86 multicore processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 226-231, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
simulator, microprocessor, coherent cache |
22 | Pat Conway, Bill Hughes |
The AMD Opteron Northbridge Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(2), pp. 10-21, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
system topology, northbridge, scalability, microarchitecture, point-to-point networking |
22 | Marek Olszewski, Keir Mierle, Adam Czajkowski, Angela Demke Brown |
JIT instrumentation: a novel approach to dynamically instrument operating systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: Proceedings of the 2007 EuroSys Conference, Lisbon, Portugal, March 21-23, 2007, pp. 3-16, 2007, ACM, 978-1-59593-636-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
kernel analysis tools, dynamic instrumentation, JIT compiler, binary rewriting |
18 | Yuki Naganawa, Hirokazu Kamei, Yamato Kanetaka, Haruki Nogami, Yoshihiro Maeda, Norishige Fukushima |
SIMD-Constrained Lookup Table for Accelerating Variable-Weighted Convolution on x86/64 CPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 15800-15819, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Daniel Engel, Freek Verbeek, Binoy Ravindran |
BIRD: A Binary Intermediate Representation for Formally Verified Decompilation of X86-64 Binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TAP ![In: Tests and Proofs - 17th International Conference, TAP 2023, Leicester, UK, July 18-19, 2023, Proceedings, pp. 3-20, 2023, Springer, 978-3-031-38827-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Benjamin Munger, Kathy Wilcox, Jeshuah Sniderman, Chuck Tung, Brett Johnson, Russell Schreiber, Carson Henrion, Kevin Gillespie, Tom Burd, Harry R. Fair III, Dave Johnson 0002, Jonathan White, Scott McLelland, Steven Bakke, Javin Olson, Ryan McCracken, Matthew Pickett, Aaron Horiuchi, Hien Nguyen, Tim Jackson |
"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 38-39, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Changwei Zou, Yaoqing Gao, Jingling Xue |
Practical Software-Based Shadow Stacks on x86-64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 19(4), pp. 61:1-61:26, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Lukas Bernhard, Michael Rodler, Thorsten Holz, Lucas Davi |
xTag: Mitigating Use-After-Free Vulnerabilities via Software-Based Pointer Tagging on Intel x86-64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2203.04117, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Jyun-Kai Lai, Wuu Yang |
Hyperchaining for LLVM-Based Binary Translators on the x86-64 Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 94(12), pp. 1569-1589, December 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Eric Schulte, Michael D. Brown, Vlad Folts |
A Broad Comparative Evaluation of x86-64 Binary Rewriters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSET @ USENIX Security Symposium ![In: CSET 2022: Cyber Security Experimentation and Test Workshop, Virtual Event, 8 August 2022, pp. 129-144, 2022, ACM, 978-1-4503-9684-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Lukas Bernhard, Michael Rodler, Thorsten Holz, Lucas Davi |
xTag: Mitigating Use-After-Free Vulnerabilities via Software-Based Pointer Tagging on Intel x86-64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroS&P ![In: 7th IEEE European Symposium on Security and Privacy, EuroS&P 2022, Genoa, Italy, June 6-10, 2022, pp. 502-519, 2022, IEEE, 978-1-6654-1614-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Freek Verbeek, Joshua A. Bockenek, Zhoulai Fu, Binoy Ravindran |
Formally verified lifting of C-compiled x86-64 binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: PLDI '22: 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation, San Diego, CA, USA, June 13 - 17, 2022, pp. 934-949, 2022, ACM, 978-1-4503-9265-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson 0002, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger |
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022, pp. 428-429, 2022, IEEE, 978-1-6654-2800-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Thomas Burd, Wilson Li, James Pistole, Srividhya Venkataraman, Michael McCabe, Timothy Johnson, James Vinh, Thomas Yiu, Mark Wasio, Hon-Hin Wong, Daryl Lieu, Jonathan White, Benjamin Munger, Joshua Lindner, Javin Olson, Steven Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar |
Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022, pp. 1-3, 2022, IEEE, 978-1-6654-2800-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Chaorun Liu, Huayou Su, Yong Dou, Qinglin Wang |
Optimize DGL Operations on x86-64 Multi-Core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HP3C ![In: HP3C 2022: 6th International Conference on High Performance Compilation, Computing and Communications, Virtual Event, China, June 23-25, 2022, pp. 117-123, 2022, ACM, 978-1-4503-9629-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Jyun-Kai Lai, Wuu Yang |
Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: ICPP Workshops 2021: 50th International Conference on Parallel Processing, Virtual Event / Lemont (near Chicago), IL, USA, August 9-12, 2021, pp. 13:1-13:9, 2021, ACM, 978-1-4503-8441-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | William Woodruff, Niki Carroll, Sebastiaan Peters |
Differential analysis of x86-64 instruction decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SP (Workshops) ![In: IEEE Security and Privacy Workshops, SP Workshops 2021, San Francisco, CA, USA, May 27, 2021, pp. 152-161, 2021, IEEE, 978-1-6654-3732-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Conor Pirry, Hector Marco-Gisbert, Carolyn Begg |
A Review of Memory Errors Exploitation in x86-64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. ![In: Comput. 9(2), pp. 48, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Georgios Georgis, Alexios Thanos, Marcin Filo, Konstantinos Nikitopoulos |
A DSP Acceleration Framework For Software-Defined Radios On X86 64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 2020 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2020, Barcelona, Spain, May 4-8, 2020, pp. 1648-1652, 2020, IEEE, 978-1-5090-6631-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Teja Singh, Sundar Rangarajan, Deepesh John, Russell Schreiber, Spence Oliver, Rajit Seahra, Alex Schaefer |
2.1 Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020, pp. 42-44, 2020, IEEE, 978-1-7281-3205-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Xuewei Feng, Dongxia Wang 0001, Zhechao Lin, Xiaohui Kuang, Gang Zhao |
Enhancing Randomization Entropy of x86-64 Code while Preserving Semantic Consistency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TrustCom ![In: 19th IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2020, Guangzhou, China, December 29, 2020 - January 1, 2021, pp. 1-12, 2020, IEEE, 978-1-6654-0392-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Freek Verbeek, Pierre Olivier, Binoy Ravindran |
Sound C Code Decompilation for a Subset of x86-64 Binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEFM ![In: Software Engineering and Formal Methods - 18th International Conference, SEFM 2020, Amsterdam, The Netherlands, September 14-18, 2020, Proceedings, pp. 247-264, 2020, Springer, 978-3-030-58767-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Brandon Neth, Michelle Mills Strout |
Automatic Parallelization of Irregular x86-64 Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2019, Washington, DC, USA, February 16-20, 2019, pp. 266, 2019, IEEE, 978-1-7281-1436-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Joshua A. Bockenek, Freek Verbeek, Peter Lammich, Binoy Ravindran |
Formal Verification of Memory Preservation of x86-64 Binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAFECOMP ![In: Computer Safety, Reliability, and Security - 38th International Conference, SAFECOMP 2019, Turku, Finland, September 11-13, 2019, Proceedings, pp. 35-49, 2019, Springer, 978-3-030-26600-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Caitlin Fanning, Saturnino Garcia |
Below C Level: A Student-Centered x86-64 Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 2019 ACM Conference on Innovation and Technology in Computer Science Education, Aberdeen, Scotland, UK, July 15-17, 2019., pp. 381-387, 2019, ACM, 978-1-4503-6301-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Amogh Akshintala, Bhushan Jain, Chia-che Tsai, Michael Ferdman, Donald E. Porter |
x86-64 instruction usage among C/C++ applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYSTOR ![In: Proceedings of the 12th ACM International Conference on Systems and Storage, SYSTOR 2019, Haifa, Israel, June 3-5, 2019, pp. 68-79, 2019, ACM, 978-1-4503-6749-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Sandeep Dasgupta, Daejun Park 0001, Theodoros Kasampalis, Vikram S. Adve, Grigore Rosu |
A complete formal semantics of x86-64 user-level instruction set architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2019, Phoenix, AZ, USA, June 22-26, 2019., pp. 1133-1148, 2019, ACM, 978-1-4503-6712-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Yi-Ping You, Tsung-Chun Lin, Wuu Yang |
Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 48th International Conference on Parallel Processing, ICPP 2019 Workshop Proceedings, Kyoto, Japan, August 05-08, 2019., pp. 12:1-12:7, 2019, ACM, 978-1-4503-7196-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Andrés Rainiero Hernández Coronado, Wonjun Lee 0003 |
Are We Referring to the Same x86 64?: Detection of Cache Events in AMD's Zen Micro-architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 39th IEEE International Conference on Distributed Computing Systems, ICDCS 2019, Dallas, TX, USA, July 7-10, 2019, pp. 2217-2227, 2019, IEEE, 978-1-7281-2519-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Yishen Chen, Ajay Brahmakshatriya, Charith Mendis, Alex Renda, Eric Atkinson, Ondrej Sýkora, Saman P. Amarasinghe, Michael Carbin |
BHive: A Benchmark Suite and Measurement Framework for Validating x86-64 Basic Block Performance Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IISWC ![In: IEEE International Symposium on Workload Characterization, IISWC 2019, Orlando, FL, USA, November 3-5, 2019, pp. 167-177, 2019, IEEE, 978-1-7281-4045-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Ian Roessle, Freek Verbeek, Binoy Ravindran |
Formally verified big step semantics out of x86-64 binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPP ![In: Proceedings of the 8th ACM SIGPLAN International Conference on Certified Programs and Proofs, CPP 2019, Cascais, Portugal, January 14-15, 2019, pp. 181-195, 2019, ACM, 978-1-4503-6222-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Gregory Michael Price |
Virtual Breakpoints for x86/64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1801.09250, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
18 | Caitlin Fanning |
Below C Level: A Simulator for Visualizing x86-64 (Abstract Only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE ![In: Proceedings of the 49th ACM Technical Symposium on Computer Science Education, SIGCSE 2018, Baltimore, MD, USA, February 21-24, 2018, pp. 274, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Paul Muntean, Matthias Fischer, Gang Tan, Zhiqiang Lin, Jens Grossklags, Claudia Eckert 0001 |
τCFI: Type-Assisted Control Flow Integrity for x86-64 Binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAID ![In: Research in Attacks, Intrusions, and Defenses - 21st International Symposium, RAID 2018, Heraklion, Crete, Greece, September 10-12, 2018, Proceedings, pp. 423-444, 2018, Springer, 978-3-030-00469-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Manuel Rigger, Stefan Marr, Stephen Kell, David Leopoldseder, Hanspeter Mössenböck |
An Analysis of x86-64 Inline Assembly in C Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 14th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, VEE 2018, Williamsburg, VA, USA, March 25-25, 2018, pp. 84-99, 2018, ACM, 978-1-4503-5579-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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18 | Christian Knauth, Boran Adas, Daniel Whitfield, Xuesong Wang, Lydia Ickler, Tim Conrad 0001, Oliver Serang |
Practically efficient methods for performing bit-reversed permutation in C++11 on the x86-64 architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1708.01873, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
18 | Junho Jeong, Yunsik Son 0001, Seman Oh |
The x86/64 Binary Code to Smart Intermediate Language Translation for Software Weakness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAIP ![In: Proceedings of the International Conference on Advances in Image Processing, ICAIP 2017, Bangkok, Thailand, August 25-27, 2017, pp. 129-134, 2017, ACM, 978-1-4503-5295-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Buddhika Chamith, Bo Joel Svensson, Luke Dalessandro, Ryan R. Newton |
Instruction punning: lightweight instrumentation for x86-64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2017, Barcelona, Spain, June 18-23, 2017, pp. 320-332, 2017, ACM, 978-1-4503-4988-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | George Papadimitriou 0001, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, Dimitris Gizopoulos |
Voltage margins identification on commercial x86-64 multicore microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, July 3-5, 2017, pp. 51-56, 2017, IEEE, 978-1-5386-0352-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Shigeki Akiyama, Kenjiro Taura |
Scalable Work Stealing of Native Threads on an x86-64 Infiniband Cluster. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Process. ![In: J. Inf. Process. 24(3), pp. 583-596, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Stefan Heule, Eric Schkufza, Rahul Sharma 0001, Alex Aiken |
Stratified synthesis: automatically learning the x86-64 instruction set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2016, Santa Barbara, CA, USA, June 13-17, 2016, pp. 237-250, 2016, ACM, 978-1-4503-4261-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger |
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 74-75, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein |
Short Note on Costs of Floating Point Operations on current x86-64 Architectures: Denormals, Overflow, Underflow, and Division by Zero. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1506.03997, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
18 | Marco Elver, Vijay Nagarajan |
RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 2015 International Conference on Parallel Architectures and Compilation, PACT 2015, San Francisco, CA, USA, October 18-21, 2015, pp. 292-304, 2015, IEEE Computer Society, 978-1-4673-9524-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Kevin Hammond, Christopher Brown 0002, Susmit Sarkar |
Timing Properties and Correctness for Structured Parallel Programs on x86-64 Multicores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOPARA ![In: Foundational and Practical Aspects of Resource Analysis - 4th International Workshop, FOPARA 2015, London, UK, April 11, 2015, Revised Selected Papers, pp. 101-125, 2015, 978-3-319-46558-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift |
BadgerTrap: a tool to instrument x86-64 TLB misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 42(2), pp. 20-23, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | John Gatewood Ham |
An ECMA-55 Minimal BASIC Compiler for x86-64 Linux. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. ![In: Comput. 3(3), pp. 69-116, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Jason Power, Mark D. Hill, David A. Wood 0001 |
Supporting x86-64 address translation for 100s of GPU lanes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 568-578, 2014, IEEE Computer Society, 978-1-4799-3097-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox |
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 104-105, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger |
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 106-107, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Visvesh S. Sathe 0001, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger |
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(1), pp. 140-149, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Teja Singh, Joshua Bell, Shane Southard |
Jaguar: A next-generation low-power x86-64 core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2013 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2013, San Francisco, CA, USA, February 17-21, 2013, pp. 52-53, 2013, IEEE, 978-1-4673-4515-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Magnus O. Myreen, Gregorio Curello |
Proof Pearl: A Verified Bignum Implementation in x86-64 Machine Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPP ![In: Certified Programs and Proofs - Third International Conference, CPP 2013, Melbourne, VIC, Australia, December 11-13, 2013, Proceedings, pp. 66-81, 2013, Springer, 978-3-319-03544-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh |
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 47(1), pp. 164-176, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Denis Foley, Pankaj Bansal, Don Cherepacha, Robert Wasmuth, Aswin Gunasekar, Srinivasa Rao Gutta, Ajay Naini |
A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 47(1), pp. 220-231, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Antoni Portero, Alberto Scionti, Zhibin Yu, Paolo Faraboschi, Caroline Concatto, Luigi Carro, Arne Garbade, Sebastian Weis, Theo Ungerer, Roberto Giorgi |
Simulating the future kilo-x86-64 core processors and their infrastructure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpringSim (ANSS) ![In: 2012 Spring Simulation Multiconference, SpringSim '12, Orlando, FL, USA - March 26-29, 2012, Proceedings of the 45th Annual Simulation Symposium, pp. 9, 2012, SCS/ACM, 978-1-61839-784-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
18 | Steve J. Dillen, Donald A. Priore, Aaron Horiuchi, Samuel Naffziger |
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-1555-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Visvesh S. Sathe 0001, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger |
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, pp. 68-70, 2012, IEEE, 978-1-4673-0376-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Amy Novak, Sam Naffziger |
An x86-64 Core in 32 nm SOI CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 46(1), pp. 162-172, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Sean White |
High-performance power-efficient x86-64 server and desktop processors using the core codenamed "Bulldozer". ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2011 IEEE Hot Chips 23 Symposium (HCS), Stanford, CA, USA, August 17-19, 2011, pp. 1-32, 2011, IEEE, 978-1-4673-8877-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Michael Golden, Srikanth Arekapudi, James Vinh |
40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011, pp. 80-82, 2011, IEEE, 978-1-61284-303-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Srinivasa Rao Gutta, Denis Foley, Ajay Naini, Robert Wasmuth, Don Cherepacha |
A low-power integrated x86-64 and graphics processor for mobile computing devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011, pp. 270-272, 2011, IEEE, 978-1-61284-303-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
18 | Patrick Longa, Catherine H. Gebotys |
Analysis of Efficient Techniques for Fast Elliptic Curve Cryptography on x86-64 based Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2010, pp. 335, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
18 | Daniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller |
Characterizing the energy consumption of data transfers and arithmetic operations on x86-64 processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Green Computing Conference ![In: International Green Computing Conference 2010, Chicago, IL, USA, 15-18 August 2010, pp. 123-133, 2010, IEEE Computer Society, 978-1-4244-7612-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Gao Xia, Bin Liu 0001 |
Accelerating network applications on X86-64 platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the 15th IEEE Symposium on Computers and Communications, ISCC 2010, Riccione, Italy, June 22-25, 2010, pp. 906-912, 2010, IEEE Computer Society, 978-1-4244-7755-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Greg Constant, Amy Novak, Sam Naffziger |
An x86-64 core implemented in 32nm SOI CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, pp. 106-107, 2010, IEEE, 978-1-4244-6033-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry Ponomarev 0001 |
MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 37(2), pp. 2-9, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | William Keshlear, Spence Oliver, Robert Colyer, Jeremy Schreiber, Ted Antoniadis, Tom Mickelson, Tim Puzey, Michael Bates |
Design optimizations for reduced power and higher operating frequency in a custom x86-64 processor core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings, pp. 17-20, 2009, IEEE, 978-1-4244-4071-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Frank van der Linden 0001 |
Porting NetBSD to the AMD x86-64: A Case Study in OS Portability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BSDCon ![In: Proceedings of BSDCon 2002, San Francisco, California, USA, February 11-14, 2002, pp. 1-9, 2002, USENIX, 1-880446-02-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
11 | Thomas W. Barr, Alan L. Cox, Scott Rixner |
Translation caching: skip, don't walk (the page table). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 48-59, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
page walk caching, memory management, tlb |
11 | Michael Kistler, John A. Gunnels, Daniel A. Brokenshire, Brad Benton |
Petascale computing with accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 241-250, 2009, ACM, 978-1-60558-397-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
hybrid programming models, accelerators |
11 | Leslie Barnes |
Performance Modeling and Analysis for AMD's High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Timothy Furtak, José Nelson Amaral, Robert Niewiadomski |
Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, San Diego, California, USA, June 9-11, 2007, pp. 348-357, 2007, ACM, 978-1-59593-667-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
sorting, instruction-level parallelism, SIMD, vectorization, sorting networks, quicksort |
11 | Björn Andersson |
Roadmaps and visions II - Getting ahead, staying ahead: modular sun x64 servers for HPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 276, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Matt T. Yourst, Kanad Ghose |
Incremental Commit Groups for Non-Atomic Trace Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 67-80, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
trace prediction, VLIW, commitment, binary translation |
11 | Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway |
The AMD Opteron Processor for Multiprocessor Servers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(2), pp. 66-76, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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