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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 30 occurrences of 30 keywords
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Results
Found 81 publication records. Showing 81 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
117 | Matt T. Yourst |
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
client-server networked benchmark, PTLsim, cycle accurate full system, x86-64 microarchitectural simulator, superscalar x86-64 processor core, full-speed native execution, microarchitectural simulators, x86 ISA, microoperation level, multiprocessor capable simulation, Xen hypervisor, AMD Athlon 64 machine, virtual machine |
63 | Dong Ye 0004, Joydeep Ray, Christophe Harle, David R. Kaeli |
Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture. |
IISWC |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Yoshiyuki Yamashita, Masato Tsuru |
Implementing Fast Packet Filters by Software Pipelining on x86 Processors. |
APPT |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel |
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
Nehalem, Shanghai, benchmark, multi-core, coherency |
23 | Pat Conway, Nathan Kalyanasundharam, Gregg Donley, Kevin Lepak, Bill Hughes |
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor. |
IEEE Micro |
2010 |
DBLP DOI BibTeX RDF |
x86-64, cache directory, probe filter, system interconnect, HyperTransport3 technology, power envelopes, cache, multiprocessor, memory hierarchy, processor, blade server |
22 | Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev |
MPTLsim: a simulator for X86 multicore processors. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
simulator, microprocessor, coherent cache |
22 | Pat Conway, Bill Hughes |
The AMD Opteron Northbridge Architecture. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
system topology, northbridge, scalability, microarchitecture, point-to-point networking |
22 | Marek Olszewski, Keir Mierle, Adam Czajkowski, Angela Demke Brown |
JIT instrumentation: a novel approach to dynamically instrument operating systems. |
EuroSys |
2007 |
DBLP DOI BibTeX RDF |
kernel analysis tools, dynamic instrumentation, JIT compiler, binary rewriting |
18 | Yuki Naganawa, Hirokazu Kamei, Yamato Kanetaka, Haruki Nogami, Yoshihiro Maeda, Norishige Fukushima |
SIMD-Constrained Lookup Table for Accelerating Variable-Weighted Convolution on x86/64 CPUs. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Daniel Engel, Freek Verbeek, Binoy Ravindran |
BIRD: A Binary Intermediate Representation for Formally Verified Decompilation of X86-64 Binaries. |
TAP |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Benjamin Munger, Kathy Wilcox, Jeshuah Sniderman, Chuck Tung, Brett Johnson, Russell Schreiber, Carson Henrion, Kevin Gillespie, Tom Burd, Harry R. Fair III, Dave Johnson 0002, Jonathan White, Scott McLelland, Steven Bakke, Javin Olson, Ryan McCracken, Matthew Pickett, Aaron Horiuchi, Hien Nguyen, Tim Jackson |
"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core. |
ISSCC |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Changwei Zou, Yaoqing Gao, Jingling Xue |
Practical Software-Based Shadow Stacks on x86-64. |
ACM Trans. Archit. Code Optim. |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Lukas Bernhard, Michael Rodler, Thorsten Holz, Lucas Davi |
xTag: Mitigating Use-After-Free Vulnerabilities via Software-Based Pointer Tagging on Intel x86-64. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Jyun-Kai Lai, Wuu Yang |
Hyperchaining for LLVM-Based Binary Translators on the x86-64 Platform. |
J. Signal Process. Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Eric Schulte, Michael D. Brown, Vlad Folts |
A Broad Comparative Evaluation of x86-64 Binary Rewriters. |
CSET @ USENIX Security Symposium |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Lukas Bernhard, Michael Rodler, Thorsten Holz, Lucas Davi |
xTag: Mitigating Use-After-Free Vulnerabilities via Software-Based Pointer Tagging on Intel x86-64. |
EuroS&P |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Freek Verbeek, Joshua A. Bockenek, Zhoulai Fu, Binoy Ravindran |
Formally verified lifting of C-compiled x86-64 binaries. |
PLDI |
2022 |
DBLP DOI BibTeX RDF |
|
18 | John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson 0002, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger |
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Thomas Burd, Wilson Li, James Pistole, Srividhya Venkataraman, Michael McCabe, Timothy Johnson, James Vinh, Thomas Yiu, Mark Wasio, Hon-Hin Wong, Daryl Lieu, Jonathan White, Benjamin Munger, Joshua Lindner, Javin Olson, Steven Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar |
Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Chaorun Liu, Huayou Su, Yong Dou, Qinglin Wang |
Optimize DGL Operations on x86-64 Multi-Core Processors. |
HP3C |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Jyun-Kai Lai, Wuu Yang |
Hyperchaining Optimizations for an LLVM-Based Binary Translator on x86-64 and RISC-V Platforms. |
ICPP Workshops |
2021 |
DBLP DOI BibTeX RDF |
|
18 | William Woodruff, Niki Carroll, Sebastiaan Peters |
Differential analysis of x86-64 instruction decoders. |
SP (Workshops) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Conor Pirry, Hector Marco-Gisbert, Carolyn Begg |
A Review of Memory Errors Exploitation in x86-64. |
Comput. |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Georgios Georgis, Alexios Thanos, Marcin Filo, Konstantinos Nikitopoulos |
A DSP Acceleration Framework For Software-Defined Radios On X86 64. |
ICASSP |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Teja Singh, Sundar Rangarajan, Deepesh John, Russell Schreiber, Spence Oliver, Rajit Seahra, Alex Schaefer |
2.1 Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core. |
ISSCC |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Xuewei Feng, Dongxia Wang 0001, Zhechao Lin, Xiaohui Kuang, Gang Zhao |
Enhancing Randomization Entropy of x86-64 Code while Preserving Semantic Consistency. |
TrustCom |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Freek Verbeek, Pierre Olivier, Binoy Ravindran |
Sound C Code Decompilation for a Subset of x86-64 Binaries. |
SEFM |
2020 |
DBLP DOI BibTeX RDF |
|
18 | Brandon Neth, Michelle Mills Strout |
Automatic Parallelization of Irregular x86-64 Loops. |
CGO |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Joshua A. Bockenek, Freek Verbeek, Peter Lammich, Binoy Ravindran |
Formal Verification of Memory Preservation of x86-64 Binaries. |
SAFECOMP |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Caitlin Fanning, Saturnino Garcia |
Below C Level: A Student-Centered x86-64 Simulator. |
ITiCSE |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Amogh Akshintala, Bhushan Jain, Chia-che Tsai, Michael Ferdman, Donald E. Porter |
x86-64 instruction usage among C/C++ applications. |
SYSTOR |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Sandeep Dasgupta, Daejun Park 0001, Theodoros Kasampalis, Vikram S. Adve, Grigore Rosu |
A complete formal semantics of x86-64 user-level instruction set architecture. |
PLDI |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Yi-Ping You, Tsung-Chun Lin, Wuu Yang |
Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform. |
ICPP Workshops |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Andrés Rainiero Hernández Coronado, Wonjun Lee 0003 |
Are We Referring to the Same x86 64?: Detection of Cache Events in AMD's Zen Micro-architecture. |
ICDCS |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Yishen Chen, Ajay Brahmakshatriya, Charith Mendis, Alex Renda, Eric Atkinson, Ondrej Sýkora, Saman P. Amarasinghe, Michael Carbin |
BHive: A Benchmark Suite and Measurement Framework for Validating x86-64 Basic Block Performance Models. |
IISWC |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Ian Roessle, Freek Verbeek, Binoy Ravindran |
Formally verified big step semantics out of x86-64 binaries. |
CPP |
2019 |
DBLP DOI BibTeX RDF |
|
18 | Gregory Michael Price |
Virtual Breakpoints for x86/64. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
18 | Caitlin Fanning |
Below C Level: A Simulator for Visualizing x86-64 (Abstract Only). |
SIGCSE |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Paul Muntean, Matthias Fischer, Gang Tan, Zhiqiang Lin, Jens Grossklags, Claudia Eckert 0001 |
τCFI: Type-Assisted Control Flow Integrity for x86-64 Binaries. |
RAID |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Manuel Rigger, Stefan Marr, Stephen Kell, David Leopoldseder, Hanspeter Mössenböck |
An Analysis of x86-64 Inline Assembly in C Programs. |
VEE |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Christian Knauth, Boran Adas, Daniel Whitfield, Xuesong Wang, Lydia Ickler, Tim Conrad 0001, Oliver Serang |
Practically efficient methods for performing bit-reversed permutation in C++11 on the x86-64 architecture. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
18 | Junho Jeong, Yunsik Son 0001, Seman Oh |
The x86/64 Binary Code to Smart Intermediate Language Translation for Software Weakness. |
ICAIP |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Buddhika Chamith, Bo Joel Svensson, Luke Dalessandro, Ryan R. Newton |
Instruction punning: lightweight instrumentation for x86-64. |
PLDI |
2017 |
DBLP DOI BibTeX RDF |
|
18 | George Papadimitriou 0001, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, Dimitris Gizopoulos |
Voltage margins identification on commercial x86-64 multicore microprocessors. |
IOLTS |
2017 |
DBLP DOI BibTeX RDF |
|
18 | Shigeki Akiyama, Kenjiro Taura |
Scalable Work Stealing of Native Threads on an x86-64 Infiniband Cluster. |
J. Inf. Process. |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Stefan Heule, Eric Schkufza, Rahul Sharma 0001, Alex Aiken |
Stratified synthesis: automatically learning the x86-64 instruction set. |
PLDI |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger |
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. |
ISSCC |
2016 |
DBLP DOI BibTeX RDF |
|
18 | Markus Wittmann, Thomas Zeiser, Georg Hager, Gerhard Wellein |
Short Note on Costs of Floating Point Operations on current x86-64 Architectures: Denormals, Overflow, Underflow, and Division by Zero. |
CoRR |
2015 |
DBLP BibTeX RDF |
|
18 | Marco Elver, Vijay Nagarajan |
RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions. |
PACT |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Kevin Hammond, Christopher Brown 0002, Susmit Sarkar |
Timing Properties and Correctness for Structured Parallel Programs on x86-64 Multicores. |
FOPARA |
2015 |
DBLP DOI BibTeX RDF |
|
18 | Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift |
BadgerTrap: a tool to instrument x86-64 TLB misses. |
SIGARCH Comput. Archit. News |
2014 |
DBLP DOI BibTeX RDF |
|
18 | John Gatewood Ham |
An ECMA-55 Minimal BASIC Compiler for x86-64 Linux. |
Comput. |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Jason Power, Mark D. Hill, David A. Wood 0001 |
Supporting x86-64 address translation for 100s of GPU lanes. |
HPCA |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox |
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. |
ISSCC |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger |
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. |
ISSCC |
2014 |
DBLP DOI BibTeX RDF |
|
18 | Visvesh S. Sathe 0001, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger |
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. |
IEEE J. Solid State Circuits |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Teja Singh, Joshua Bell, Shane Southard |
Jaguar: A next-generation low-power x86-64 core. |
ISSCC |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Magnus O. Myreen, Gregorio Curello |
Proof Pearl: A Verified Bignum Implementation in x86-64 Machine Code. |
CPP |
2013 |
DBLP DOI BibTeX RDF |
|
18 | Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh |
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. |
IEEE J. Solid State Circuits |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Denis Foley, Pankaj Bansal, Don Cherepacha, Robert Wasmuth, Aswin Gunasekar, Srinivasa Rao Gutta, Ajay Naini |
A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices. |
IEEE J. Solid State Circuits |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Antoni Portero, Alberto Scionti, Zhibin Yu, Paolo Faraboschi, Caroline Concatto, Luigi Carro, Arne Garbade, Sebastian Weis, Theo Ungerer, Roberto Giorgi |
Simulating the future kilo-x86-64 core processors and their infrastructure. |
SpringSim (ANSS) |
2012 |
DBLP BibTeX RDF |
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18 | Steve J. Dillen, Donald A. Priore, Aaron Horiuchi, Samuel Naffziger |
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules. |
CICC |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Visvesh S. Sathe 0001, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger |
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. |
ISSCC |
2012 |
DBLP DOI BibTeX RDF |
|
18 | Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Amy Novak, Sam Naffziger |
An x86-64 Core in 32 nm SOI CMOS. |
IEEE J. Solid State Circuits |
2011 |
DBLP DOI BibTeX RDF |
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18 | Sean White |
High-performance power-efficient x86-64 server and desktop processors using the core codenamed "Bulldozer". |
Hot Chips Symposium |
2011 |
DBLP DOI BibTeX RDF |
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18 | Michael Golden, Srikanth Arekapudi, James Vinh |
40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core. |
ISSCC |
2011 |
DBLP DOI BibTeX RDF |
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18 | Srinivasa Rao Gutta, Denis Foley, Ajay Naini, Robert Wasmuth, Don Cherepacha |
A low-power integrated x86-64 and graphics processor for mobile computing devices. |
ISSCC |
2011 |
DBLP DOI BibTeX RDF |
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18 | Patrick Longa, Catherine H. Gebotys |
Analysis of Efficient Techniques for Fast Elliptic Curve Cryptography on x86-64 based Processors. |
IACR Cryptol. ePrint Arch. |
2010 |
DBLP BibTeX RDF |
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18 | Daniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller |
Characterizing the energy consumption of data transfers and arithmetic operations on x86-64 processors. |
Green Computing Conference |
2010 |
DBLP DOI BibTeX RDF |
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18 | Gao Xia, Bin Liu 0001 |
Accelerating network applications on X86-64 platforms. |
ISCC |
2010 |
DBLP DOI BibTeX RDF |
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18 | Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Greg Constant, Amy Novak, Sam Naffziger |
An x86-64 core implemented in 32nm SOI CMOS. |
ISSCC |
2010 |
DBLP DOI BibTeX RDF |
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18 | Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry Ponomarev 0001 |
MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches. |
SIGARCH Comput. Archit. News |
2009 |
DBLP DOI BibTeX RDF |
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18 | William Keshlear, Spence Oliver, Robert Colyer, Jeremy Schreiber, Ted Antoniadis, Tom Mickelson, Tim Puzey, Michael Bates |
Design optimizations for reduced power and higher operating frequency in a custom x86-64 processor core. |
CICC |
2009 |
DBLP DOI BibTeX RDF |
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18 | Frank van der Linden 0001 |
Porting NetBSD to the AMD x86-64: A Case Study in OS Portability. |
BSDCon |
2002 |
DBLP BibTeX RDF |
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11 | Thomas W. Barr, Alan L. Cox, Scott Rixner |
Translation caching: skip, don't walk (the page table). |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
page walk caching, memory management, tlb |
11 | Michael Kistler, John A. Gunnels, Daniel A. Brokenshire, Brad Benton |
Petascale computing with accelerators. |
PPoPP |
2009 |
DBLP DOI BibTeX RDF |
hybrid programming models, accelerators |
11 | Leslie Barnes |
Performance Modeling and Analysis for AMD's High Performance Microprocessors. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
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11 | Timothy Furtak, José Nelson Amaral, Robert Niewiadomski |
Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms. |
SPAA |
2007 |
DBLP DOI BibTeX RDF |
sorting, instruction-level parallelism, SIMD, vectorization, sorting networks, quicksort |
11 | Björn Andersson |
Roadmaps and visions II - Getting ahead, staying ahead: modular sun x64 servers for HPC. |
SC |
2006 |
DBLP DOI BibTeX RDF |
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11 | Matt T. Yourst, Kanad Ghose |
Incremental Commit Groups for Non-Atomic Trace Processing. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
trace prediction, VLIW, commitment, binary translation |
11 | Chetana N. Keltcher, Kevin J. McGrath, Ardsher Ahmed, Pat Conway |
The AMD Opteron Processor for Multiprocessor Servers. |
IEEE Micro |
2003 |
DBLP DOI BibTeX RDF |
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