Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Jonas Bertels, Michiel Van Beirendonck, Furkan Turan, Ingrid Verbauwhede |
Hardware Acceleration of FHEW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 57-60, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik |
APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 124-127, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Christian Fibich, Martin Horauer, Roman Obermaisser |
Characterization of Interconnect Fault Effects in SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 65-68, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Maryam Saadat-Safa, Tahoura Mosavirik, Shahin Tajik |
Counterfeit Chip Detection using Scattering Parameter Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 99-104, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Luigi Capogrosso, Federico Cunico, Michele Lora, Marco Cristani, Franco Fummi, Davide Quaglia |
Split-Et-Impera: A Framework for the Design of Distributed Deep Learning Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 39-44, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Sergio Vinagrero Gutierrez, Pietro Inglese, Giorgio Di Natale, Elena Ioana Vatajelu |
Open Automation Framework for Complex Parametric Electrical Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 132-135, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic |
Active Wire Fences for Multitenant FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 13-20, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Mohamed El Bouazzati, Russell Tessier, Philippe A. Tanguy, Guy Gogniat |
A Lightweight Intrusion Detection System against IoT Memory Corruption Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 118-123, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Rune Krauss, Mehran Goli, Rolf Drechsler |
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 73-78, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Robert Hülle, Petr Fiser, Jan Schmidt |
Reducing Output Response Aliasing Using Boolean Optimization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 33-38, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Eleonora Vacca, Sarah Azimi, Luca Sterpone |
A Comprehensive Analysis of Transient Errors on Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 175-180, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Luigi Capogrosso, Luca Geretti, Marco Cristani, Franco Fummi, Tiziano Villa |
HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 87-90, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina |
MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 155-160, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Fabio A. Velarde Gonzalez, Lukas Hahne, Katrin Ortstein, André Lange, Sonja Crocoll |
Supporting analog design for reliability by efficient provision of reliability information to designers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 61-64, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Michal Pinos, Vojtech Mrazek, Lukás Sekanina |
Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 45-50, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Nicolas Gerlin, Endri Kaja, Fabian Vargas 0001, Li Lu, Anselm Breitenreiter, Junchao Chen 0001, Markus Ulbricht 0002, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker |
Bits, Flips and RISCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 140-149, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Bernardi, Gabriele Filipponi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Vincenzo Tancorre |
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 21-26, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Joseline Heuer, Rene Krenz-Baath, Roman Obermaisser |
Verifying Bio-Electronic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 161-166, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Robert Limas Sierra, Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda |
A Reliability-aware Environment for Design Exploration for GPU Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 169-174, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Dominic Korner, Andreas Kramer, Klaus Hofmann, Felix Hausch |
Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug Candidates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 150-154, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez 0001, Alberto Bosio |
Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 181-186, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Maksim Jenihhin, Hana Kubátová, Nele Metens, Jaan Raik, Foisal Ahmed, Jan Belohoubek (eds.) |
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023 ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![IEEE, 979-8-3503-3277-3 The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Elias Trommer, Bernd Waschneck, Akash Kumar 0001 |
High-Throughput Approximate Multiplication Models in PyTorch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 79-82, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Letícia Maria Veiras Bolzani |
Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 167-168, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Vojtech Mrazek |
Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 91-92, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Zahra Hojati, Zainalabedin Navabi |
A Low-Cost Combinational Approximate Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 136-139, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Jure Vreca, Anton Biasizzo |
A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 128-131, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Ali Monavari Bidgoli, Sepideh Fattahi, Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Masoud Daneshtalab |
NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 51-56, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Swantje Plambeck, Görschwin Fey |
Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 27-32, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Öhlinger, Ulrich Schmid 0001 |
A Digital Delay Model Supporting Large Adversarial Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 111-117, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Marcel Merten, Muhammad Hassan 0002, Rolf Drechsler |
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 105-110, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Nooshin Nosrati, Zainalabedin Navabi |
A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 83-86, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Carl Riehm, Christoph Frisch, Florin Burcea, Matthias Hiller, Michael Pehl, Ralf Brederlow |
Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 93-98, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Khakim Akhunov, Kasim Sinan Yildirim |
LUTIC: A CRAM-based Architecture for Power Failure Resilient In-Memory Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 69-72, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Michal Kekely, Jan Korenek |
Optimizing Packet Classification on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 7-12, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Adebayo Omotosho, Sirine IIahi, Ernesto Cristopher Villegas Castillo, Christian Hammer 0001, Christian Sauer 0001 |
Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-3277-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
1 | Roshwin Sengupta, Ilia Polian, John P. Hayes |
Stochastic Computing Architectures for Lightweight LSTM Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 124-129, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Jan Klhufek, Vojtech Mrazek |
ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 44-47, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Matús Oleksák, Vojtech Miskovský |
Correlation Power Analysis of SipHash. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 84-87, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Milan Funck, Vladimir Herdt, Rolf Drechsler |
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 14-19, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Owen Hoffend, John P. Hayes |
Analyzing Multilevel Stochastic Circuits using Correlation Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 130-135, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Salah Daddinounou, Elena Ioana Vatajelu |
Synaptic Control for Hardware Implementation of Spike Timing Dependent Plasticity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 106-111, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Levent Aksoy, Alexander Hepp, Johanna Baehr, Samuel Pagliarini |
Hardware Obfuscation of Digital FIR Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 68-73, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Antonios Banos, Yannick Verbelen, Suresh Kaluvan, Chris Hutson, Matthew Ryan Tucker, Tom B. Scott 0001 |
Hexapod robotic system for indoor neutron and gamma radiation mapping and inspection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 48-53, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Christopher A. Metz, Mehran Goli, Rolf Drechsler |
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 166-171, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari |
Functional Verification of Arithmetic Circuits: Survey of Formal Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 94-99, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Gerold Fink, Medina Hamidovic, Werner Haselmayr, Robert Wille |
A Concept Towards Pressure-Controlled Microfluidic Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 118-123, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola |
A Design Space Exploration Framework for Memristor-Based Crossbar Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 38-43, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Zaheer Tabassam, Syed Rameez Naqvi, Andreas Steininger |
AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 32-37, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Weiyan Zhang, Mehran Goli, Rolf Drechsler |
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 20-25, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Kemal Çaglar Coskun, Muhammad Hassan 0002, Rolf Drechsler |
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 160-165, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Richard Ravasz, Adam Hudec, Daniel Arbet, Viera Stopjaková |
On-Chip Current Sensing Approaches for DC-DC Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 64-67, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Patrick Karl, Tim Fritzmann, Georg Sigl |
Hardware Accelerated FrodoKEM on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 154-159, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | David Maljar, Daniel Arbet, Martin Kovác, Róbert Ondica, Viera Stopjaková |
Autocalibration Approach for Improving Robustness of Analog ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 54-59, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Rolf Drechsler, Alireza Mahzoon, Mehran Goli |
Towards Polynomial Formal Verification of Complex Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Alessandro Veronesi, Francesco Dall'Occo, Davide Bertozzi, Michele Favalli, Milos Krstic |
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 142-147, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Josef Strnadel |
Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 88-93, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Troya Çagil Köylü, Luíza C. Garaffa, Cezar Reinbrecht, Mahdi Zahedi, Said Hamdioui, Mottaqiallah Taouil |
Exploiting PUF Variation to Detect Fault Injection Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 74-79, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Yannick Verbelen, Antonios Banos, Tom B. Scott 0001 |
Fault Tolerant Synchronous Multi-Channel Buck Converter for Nuclear Inspection Instruments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 148-153, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Ashton Snelgrove, Pierre-Emmanuel Gaillardon |
Programmable logic elements using multigate ambipolar transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 112-117, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Noura Ait Manssour, Vianney Lapôtre, Guy Gogniat, Arnaud Tisserand |
Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 26-31, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena Ioana Vatajelu |
Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 7-13, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | |
25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022 ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![IEEE, 978-1-6654-9431-1 The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale |
On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 172-177, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Annachiara Ruospo, Gabriele Gavarini, Ilaria Bragaglia, Marcello Traiola, Alberto Bosio, Ernesto Sánchez 0001 |
Selective Hardening of Critical Neurons in Deep Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 136-141, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Florian Huemer, Robert Najvirt, Andreas Steininger |
On SAT-Based Model Checking of Speed-Independent Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 100-105, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Vít Masek, Martin Novotný |
Versatile Hardware Framework for Elliptic Curve Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022, pp. 80-83, 2022, IEEE, 978-1-6654-9431-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
1 | Hassan Ebrahimi, Hans G. Kerkhoff |
Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 75-80, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Aleksa Damljanovic, Annachiara Ruospo, Ernesto Sánchez 0001, Giovanni Squillero |
A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 51-56, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Siang-Yun Lee, Heinz Riener, Giovanni De Micheli |
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 105-110, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Lukasz A. Kadlubowski, Piotr Kmon |
Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 137-140, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Alija Dervic, Saman Kohneh Poushi, Horst Zimmermann |
Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-μ m CMOS for reaching PDP saturation at 650 nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Bosio, Mayeul Cantan, Cédric Marchand 0002, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola |
Emerging Technologies: Challenges and Opportunities for Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 93-98, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik |
CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 127-132, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Alessandro Savino, Marcello Traiola, Stefano Di Carlo, Alberto Bosio |
Efficient Neural Network Approximation via Bayesian Reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 45-50, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | David Maljar, Michal Sovcík, Daniel Arbet, Viera Stopjaková |
Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 119-122, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Davide Appello, Paolo Bernardi, Andrea Calabrese, Stefano Littardi, Giorgio Pollaccia, Stefano Quer, Vincenzo Tancorre, Roberto Ugioli |
Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 69-74, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda |
On the Functional Test of Special Function Units in GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 81-86, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Roman Vrána, Jan Korenek |
Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 115-118, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Zdenek Vasícek |
Synthesis of approximate circuits for LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 17-22, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Mitko Veleski, Michael Hübner 0001, Milos Krstic, Rolf Kraemer |
Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 57-62, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Nurettin Bölücü, Suleyman Tosun |
Q-Learning-based Routing Algorithm for 3D Network-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 33-36, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Michal Sovcik, Viera Stopjaková |
EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 6-10, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Raghda El Shehaby, Andreas Steininger |
Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 63-68, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Malik Imran, Zain Ul Abideen 0002, Samuel Pagliarini |
An Open-source Library of Large Integer Polynomial Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 145-150, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, André Alberts, Franco Fummi |
Predictive Fault Grouping based on Faulty AC Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 11-16, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Olivier Sentieys, Silviu-Ioan Filip, David Briand, David Novo, Etienne Dupuis, Ian O'Connor, Alberto Bosio |
AdequateDL: Approximating Deep Learning Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 37-40, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Michal Orsák, Tomás Benes |
High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 151-156, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Muhammad Shafique 0001, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek (eds.) |
24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021 ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![IEEE, 978-1-6654-3595-6 The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Sánchez 0001, Luigi Dilillo |
A Model-Based Framework to Assess the Reliability of Safety-Critical Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 41-44, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Jianan Wen, Markus Ulbricht 0002, Eduardo Perez, Xin Fan 0003, Milos Krstic |
Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 29-32, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Pawel Skrzypiec, Robert Szczygiel |
Development of On-Chip Calibration for Hybrid Pixel Detectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 133-136, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Denis Dutey, Stephane Martin, Anne Merlande, Om Ranjan |
Prevention and Detection Methods of Systematic Failures in the Implementation of SoC Safety Mechanisms not Covered by Regular Functional Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 87-92, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Rolf Drechsler |
PolyAdd: Polynomial Formal Verification of Adder Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 99-104, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Zoran Stamenkovic, Hassen Aziza, Ernesto Sánchez 0001, Alberto Bosio |
Tutorial: Silicon Systems for Wireless LAN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 157-158, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Martin Skriver, Anders Stengaard Sørensen, Ulrik Pagh Schultz |
HEIST: A Hardware Signal Fault Injection Methodology Enabling Feasible Software Robustness Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 123-126, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Christoph Niemann 0002, Michael Rethfeldt, Dirk Timmermann |
Approximate Multipliers for Optimal Utilization of FPGA Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 23-28, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Vukan D. Damnjanovic, Marija L. Petrovic, Vladimir M. Milovanovic |
A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 141-144, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Josef Strnadel |
Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 111-114, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
1 | Petr Bardonek, Marcela Zachariásová |
Using Control Logic Drivers for Automated Generation of System-level Portable Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2020, Novi Sad, Serbia, April 22-24, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9938-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|