Search results for "IWSOC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	S. A. Moghaddam, Nasser Masoumi, Caro Lucas	A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Seungbeom Lee, Sin-Chong Park	Transaction Analysis of Multiprocessor Based Platform with Bus Matrix.	IWSOC	2005	DBLP DOI BibTeX RDF
1	S. M. Rezaul Hasan	A High Efficiency 3GHz 24-dBm CMOS Linear Power Amplifier for RF Application.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su	Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
1	James B. Kuo	Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Mona Safar, M. Watheq El-Kharashi, Ashraf Salem	An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Luca Larcher, Paolo Pavan, Alfonso Maurelli	Flash Memories for SoC: An Overview on System Constraints and Technology Issues, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Shih-Chang Hsia, Wen-Ching Lee	A Very Low-Power Flash A/D Converter Based on Cmos Inverter Circuit.	IWSOC	2005	DBLP DOI BibTeX RDF	CMOS inverter, flash, A/D converter
1	Moeed Israr, Tad A. Kwasniewski	Turbo Codes - Digital IC Design.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen	Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Jin Lee, Sin-Chong Park	Orthogonalized Communication Architecture for MP-SoC with Global Bus.	IWSOC	2005	DBLP DOI BibTeX RDF
1		Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada	IWSOC	2005	DBLP BibTeX RDF
1	Russell Klein, Tomasz Piekarz	Accelerating Functional Simulation for Processor Based Designs, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	N. Patrick Kelly, Ben W. Jones, Nestor A. Fesas, John M. Morton	Design of 802.11 Access Point Chipsets for Enterprise Applications, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Charles E. Berndt, Tad A. Kwasniewski	A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Payam Ghafari, Ehsan Mirhadi, Mohab Anis, Shawki Areibi, Mohamed I. Elmasry	A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets.	IWSOC	2005	DBLP DOI BibTeX RDF	Subthreshold Leakage Power, Sleep Time, Geometric Iterative Improvement, Genetic Algorithm, Partitioning, Segmented Trees
1	Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, Jahan B. Ghasemi	Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Ki-Bog Kim, Chi-Ho Lin	An Optimal ILP Model for Delay Time to Minimize Peak Power and Area.	IWSOC	2005	DBLP DOI BibTeX RDF	B&B, scheduling, Pipelined, ILP, area, peak-power, datapath
1	Scott E. Thompson	Strained Si and the Future Direction of CMOS, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois	A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Marco Mattavelli, Massimo Ravasi	High Level Extraction of SoC Architectural Information from Generic C Algorithmic Descriptions.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Yanjie Wang, M. Zamin Khan, Kris Iniewski	A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHz.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Mohab Anis, Mohamed H. Abu-Rahma	Leakage Current Variability in Nanometer Technologies, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	J. Derakhshandeh, Nasser Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot	A Precise Model for Leakage Power Estimation in VLSI Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski	PLL-Based Fractional-N Frequency Synthesizers.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Robert Bogdan Staszewski, Roman Staszewski, Poras T. Balsara	VHDL Simulation and Modeling of an All-Digital RF Transmitter.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Blair Schiffner, Jianhua Li, Laleh Behjat	A Multivalue Eigenvalue Based Circuit Partitioning Technique.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Nur Kurt-Karsilayan	Generic Modeling of Non-planar Dielectrics for 2 1/2D Parasitic Extraction.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Robert Grou-Szabo, Hany Ghattas, Yvon Savaria, Gabriela Nicolescu	Component-Based Methodology for Hardware Design of a Dataflow Processing Network.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Thomas Palkert	A Review of Current Standards Activities for High Speed Physical Layers, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Vladimir Stojanovic	High-Speed Serial Links: Design Trends and Challenges, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Sorin P. Voinigescu, Michael Gordon 0001, Chihou Lee, Terry Yao, Alain M. Mangan, Kenneth H. K. Yau	System-on-Chip Design beyond 50 GHz, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	A. N. M. Ehtesham Rafiq, M. Watheq El-Kharashi, Fayez Gebali	Systolic Array-Based String Matching Unit for Spam Blocking.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Yoon Huh, Peter Bendix, Kyungjin Min, Jau-Wen Chen, Ravindra Narayan, Larry D. Johnson, Steven H. Voldman	ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Bahar Khadem Hosseinieh, Nasser Masoumi	A Comprehensive Model for On-Chip Spiral Inductors.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Amine Bermak	Conversion Time Analysis of Time Domain Digital Pixel Sensor in Uniform and Non-Uniform Quantizers, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Johan van der Tang, Harm van Rumpt, Dieter Kasperkovitz	HW/SW Co-Design for SoC on Mobile Platforms, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Chul-hyung Ryu, Sung-Woong Ra	A Fast Full Search Equivalent Encoding Algorithm for Image Vector Quantization Based on the WHT and a LUT.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold	Digital RF Processing Techniques for SoC Radios, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	M. M. Tabriz, Nasser Masoumi	A New Topology for Power Control of High Efficiency Class-E Switched Mode Power Amplifier.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Pawoumodom L. Takouda, Miguel F. Anjos, Anthony Vannelli	Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Esam Khan, M. Watheq El-Kharashi, Fayez Gebali, Mostafa I. H. Abd-El-Barr	An FPGA Design of a Unified Hash Engine for IPSec Authentication.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Baodong Yu, Xuecheng Zou	The Software/Hardware Co-Debug Environment with Emulator.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Stephen Bates, Kris Iniewski	10 GBPS over Copper Lines - State of the Art in VLSI, invited.	IWSOC	2005	DBLP DOI BibTeX RDF	10GBASE-T, 10GBASE-X, Data Communications, LDPC
1	Juan Antonio Carballo	Open HW, Open Design SW, and the VC Ecosystem Dilemma.	IWSOC	2005	DBLP DOI BibTeX RDF	design, methodology, System, ROI, valuation, chip
1	Shaoqiang Bi, Warren J. Gross, Wei Wang 0003, Asim J. Al-Khalili, M. N. S. Swamy	An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Mohammad Hadi Izadi, Karim S. Karim	Noise Analysis of a CMOS Active Pixel Sensor for Tomographic Mammography.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Kenneth A. Townsend, James W. Haslett, Krzysztof Iniewski	Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Farid Boussaïd, Chen Shoushun, Amine Bermak	A Scalable Low Power Imager Architecture for Compound-Eye Vision Sensors.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Joshua K. Nakaska, James W. Haslett	A CMOS Quality Factor Enhanced Parallel Resonant LC-Tank with Independent Q and Frequency Tuning for RF Integrated Filters.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Sung-Rok Yoon, Sin-Chong Park	Simulation and Analysis of Network on Chip Architecture for Wireless Communication System.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Hyoungsoo Kim, Youngsik Hur, Moonkyun Maeng, Franklin Bien, Soumya Chandramouli, Edward Gebara, Joy Laskar	A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Hung Tien Bui, Yvon Savaria	A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.	IWSOC	2005	DBLP DOI BibTeX RDF
1	P. Samson, P. Sinha	Hardware Acceleration of Deadlock Avoidance and Detection in Real-Time Operating Systems.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Ihab Amer, Choudhury A. Rahman, Tamer Mohamed, Mohammed Sayed, Wael M. Badawy	A Hardware-Accelerated Framework with IP-Blocks for Application in MPEG-4.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Chia-Jung Chang, Ke-Horng Chen	Bidirectional Current-Mode Capacitor Multiplier in DC-DC Converter Compensation.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Paul Kempf	Enabling Technology for Analog Integration, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Sang-Ho Seo, Sin-Chong Park	Low Latency and Power Efficient VD Using Register Exchanged State-Mapping Algorithm.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Miro Milanovic, Mitja Truntic, Primoz Slibar	FPGA Implementation of Digital Controller for DC-DC Buck Converter.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Jung Ko, Vincent C. Gaudet, Robert Hang	A Tier 3 Software Defined AM Radio.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park	Instruction Based Testbench Architecture, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Azzouz Nezar, Michael Creighton	System on Chip: Challenges and Design for Manufacturing, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Haidar Harmanani, Bassem Karablieh	A Hybrid Distributed Test Generation Method Using Deterministic and Genetic Algorithms.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Zhonghai Lu, Axel Jantsch	Traffic Configuration for Evaluating Networks on Chips.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang	An Automatic Layout Generator for I/O Cells.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Paul E. Hasler, AiChen Low	Programmable Low Dropout Voltage Regulator.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Hung-Ch Lee, Kuo-Tai Chang, Ke-Horng Chen, Wen Tsao Chen	Power Saving of a Dynamic Width Controller for a Monolithic Current-Mode CMOS DC-DC Converter.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Yanjie Wang, Yanbin Wang, Garry Tarr, Kris Iniewski	A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH Extractor.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Tina Lindkvist	Additional Knowledge of Bus Invert Coding Schemes.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Robert Bogdan Staszewski, Sameh Rezeq, Chih-Ming Hung, Patrick Cruise, John L. Wallberg	Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude Conversion.	IWSOC	2005	DBLP DOI BibTeX RDF
1		Introduction.	IWSOC	2005	DBLP DOI BibTeX RDF
1	David N. Abramson, Jordan D. Gray, Shyam Subramanian, Paul E. Hasler	A Field-Programmable Analog Array Using Translinear Elements.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Christian Cojocaru	Low Power Bluetooth for Headset Applications, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Abhijit Ray, Thambipillai Srikanthan, Wu Jigang	Practical Techniques for Performance Estimation of Processors.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Paul E. Hasler	Low-Power Programmable Signal Processing, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Chun-Yueh Huang, Tsung-Tien Hou, Chi-Chieh Chuang, Hung-Yu Wang	Design of 12-bit 100-MHz Current-Steering DAC for SoC Applications.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Amir Khatibzadeh, Kaamran Raahemifar	A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Shih-Chang Hsia, Shih Wen Chou	A High-Performance Error Concealment Processor for Video Decoder.	IWSOC	2005	DBLP DOI BibTeX RDF	JPEG/MEPG, adaptive, interpolation, throughput, motion compensation, error concealment
1	Gyongsu Lee, Sin-Chong Park	Architecture for Multi-processor SoC Platform Using Dedicated Channels.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Haigang Yang, Hongguang Sun, Jinghong Han, Jinbao Wei, Zengjin Lin, Shanhong Xia, Hua Zhong	A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology.	IWSOC	2005	DBLP DOI BibTeX RDF	Micro Sensor System, ISFET, CMOS, SOC
1	Joachim Becker, Fabian Henrici, Yiannos Manoli	System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Artur Balasinski	DfM for SoC, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang	Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Ching-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng	A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Kenneth A. Townsend, James W. Haslett, Tommy Kwong-Kin Tsang, Mourad N. El-Gamal, Krzysztof Iniewski	Recent Advances and Future Trends in Low Power Wireless Systems for Medical Applications.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Jianhua Li, Laleh Behjat, Blair Schiffner	A Structure Based Clustering Algorithm with Applications to VLSI Physical Design.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Mostafa Borhani, Vafa Sedghi	An Acoustic Echo Canceller Chip.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Miao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang	Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Il-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park	Efficient Pattern-Based Emulation for IEEE 802.11a Baseband.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Daniel Wiklund, Dake Liu	Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip.	IWSOC	2005	DBLP DOI BibTeX RDF	basestation, scheduling, Network on chip, 3G, WCDMA
1	Syed Masood Ali, Rabin Raut, Mohamad Sawan	A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Lech Józwiak	Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Eric Tell, Anders Nilsson 0001, Dake Liu	A Low Area and Low Power Programmable Baseband Processor Architecture.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Paul E. Hasler	Floating-Gate Devices, Circuits, and Systems, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Choudhury A. Rahman, Wael M. Badawy	UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Earl E. Swartzlander Jr.	Three Dimensional System on Chip Technology, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Xiqun Zhu, Yuan Ma	Modular Architecture for System-on-Chip Design of Scalable MEMS Optical Switch Actuator Controller.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Meeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar	Power Reduction Technique Using Multi-vt Libraries.	IWSOC	2005	DBLP DOI BibTeX RDF	High-Vt, Low-Vt, DFT, ASIC, Leakage power, DSM
1	Bill Pontikakis, François R. Boyer, Yvon Savaria	Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Mohammad M. Ahmadi, Graham A. Jullien	A Very Low Power CMOS Potentiostat for Bioimplantable Applications.	IWSOC	2005	DBLP DOI BibTeX RDF

Publications at "IWSOC"( http://dblp.L3S.de/Venues/IWSOC )