Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Alan Hunter 0002, Andrew Piziali, Avi Ziv, Kelly Larson, Shankar Hemmady	Ensuring Functional Closure of a Multi-core SoC through Verification Planning, Implementation and Execution.	MTV	2008	DBLP DOI BibTeX RDF
12	Chia-Ling Lynn Chang, Charles H.-P. Wen	Mining Unreachable Cross-Timeframe State-Pairs for Bounded Sequential Equivalence Checking.	MTV	2008	DBLP DOI BibTeX RDF
12	Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu	Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	superscalar pipeline, non-blocking cache, synthesis flow, bit-sliced placement, crafted cell, performance evaluation, physical design, out-of-order execution, general-purpose processor
12	Arghya Sarkar, Samarjit Sengupta	A Low-Cost Fault-Tolerant Real, Reactive, and Apparent Power Measurement Technique Using Microprocessor.	IEEE Trans. Instrum. Meas.	2007	DBLP DOI BibTeX RDF
12	Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Alberto de la Mora Gálvez	Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs.	J. Univers. Comput. Sci.	2007	DBLP DOI BibTeX RDF
12	Brian W. Curran, Eric Fluhr, Jose Paredes, Leon J. Sigal, Joshua Friedrich, Yiu-Hing Chan, Charlie Hwang	Power-constrained high-frequency circuits for the IBM POWER6 microprocessor.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
12	Hye-Young McCreary, Martha A. Broyles, Michael S. Floyd, Andrew J. Geissler, Steven P. Hartman, Freeman L. Rawson III, Todd J. Rosedahl, Juan C. Rubio, Malcolm S. Ware	EnergyScale for IBM POWER6 microprocessor-based systems.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
12	Rex Berridge, Robert M. Averill III, Arnold E. Barish, Michael A. Bowen, Peter J. Camporese, Jack DiLullo, Peter E. Dudley, Joachim Keinert, David W. Lewis, Robert D. Morel, Thomas E. Rosser, Nicole S. Schwartz, Philip Shephard, Howard H. Smith, Dave Thomas, Phillip J. Restle, John R. Ripley, Stephen L. Runyon, Patrick M. Williams	IBM POWER6 microprocessor physical design and design methodology.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
12	Michael S. Floyd, Soraya Ghiasi, Tom W. Keller, Karthick Rajamani, Freeman L. Rawson III, Juan C. Rubio, Malcolm S. Ware	System power management support in the IBM POWER6 microprocessor.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
12	Nitin Navale, Erica Lundgren, Nicholas P. Carter	A magnetoelectronic register file cell for a self-checkpointing microprocessor.	Int. J. Circuit Theory Appl.	2007	DBLP DOI BibTeX RDF
12	Greg Stitt, Frank Vahid	A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms	CoRR	2007	DBLP BibTeX RDF
12	Giuseppe Notarangelo, Francesco Pappalardo 0002, Elena Salurso, Elio Guidetti	A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing.	J. Low Power Electron.	2007	DBLP DOI BibTeX RDF
12	Ken Ferens, Marcia R. Friesen, Sandra Ingram	Impact Assessment of a Microprocessor Animation on Student Learning and Motivation in Computer Engineering.	IEEE Trans. Educ.	2007	DBLP DOI BibTeX RDF
12	Thomas Hauser, Aravind Dasu, Arvind Sudarsanam, Seth Young	Performance of a LU decomposition on a multi-FPGA system compared to a low power commodity microprocessor system.	Scalable Comput. Pract. Exp.	2007	DBLP BibTeX RDF
12	Raymond J. Sung, Duncan G. Elliott	Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
12	Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (eds.)	Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA	MTV	2007	DBLP BibTeX RDF
12	Thuyen Le, Tilman Glökler, Jason Baumgartner	Formal verification of a pervasive interconnect bus system in a high-performance microprocessor.	DATE	2007	DBLP DOI BibTeX RDF
12	Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.	ETS	2007	DBLP DOI BibTeX RDF
12	Haihua Shen, Heng Zhang	An Accurate Analysis of Microprocessor Design Verification.	ATS	2007	DBLP DOI BibTeX RDF
12	Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid	Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System.	FPL	2007	DBLP DOI BibTeX RDF
12	Pavel Zaykov	MIMD implementation with PicoBlaze microprocessor using MPI functions.	CompSysTech	2007	DBLP DOI BibTeX RDF	MPI functions, PicoBlaze, FPGA, system-on-chip, VHDL, MIMD, parallel computer architecture, message passing system
12	Hiroaki Kokubo, Nobuo Hataoka, Akinobu Lee, Tatsuya Kawahara, Kiyohiro Shikano	Real-Time Continuous Speech Recognition System on SH-4A Microprocessor.	MMSP	2007	DBLP DOI BibTeX RDF
12	Thomas Baumann, Jörg Berthold, T. Niedermeier, Tim Schoenauer, J. Dienstuhl, Doris Schmitt-Landsiedel, Christian Pacha	Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement.	ESSCIRC	2007	DBLP DOI BibTeX RDF
12	Dirk Jansen, Nidal Fawaz, Daniel Bau, Marc Durrenberger	A Small High Performance Microprocessor Core Sirius for Embedded Low Power Designs, Demonstrated in a Medical Mass Application of an Electronic Pill(EPill®).	IESS	2007	DBLP DOI BibTeX RDF
12	Daniel Murray, James Burnette, Brian Campbell 0004, Mark Chung, Bruce Fernandes, Subhendra Ghosh, Rajat Goel, Greg Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, Fabian Klass, Fang Liu, Anup Mehta, Yamini Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, Sribalan Santhanam, Junji Sugisawa, Shyam Sundar 0003, Honkai John Tam, Ricky Wen, Eric Wu, Jung-Cheng Yeh, John Yong, Sanjay Zambare	A 2GHz, 7W (max) 64b PowerTM Microprocessor Core.	CICC	2007	DBLP DOI BibTeX RDF
12	Bryan Casper, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Mozhgan Mansuri	Future Microprocessor Interfaces: Analysis, Design and Optimization.	CICC	2007	DBLP DOI BibTeX RDF
12	Peter van Stralen, Andy D. Pimentel	Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration.	ESTIMedia	2007	DBLP DOI BibTeX RDF
12	Marc Tremblay	Transactional memory for a modern microprocessor.	PODC	2007	DBLP DOI BibTeX RDF
12	Norman K. James, Phillip J. Restle, Joshua Friedrich, Bill Huott, Bradley D. McCredie	Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor.	ISSCC	2007	DBLP DOI BibTeX RDF
12	Joshua Friedrich, Bradley D. McCredie, Norman K. James, Bill Huott, Brian W. Curran, Eric Fluhr, Gaurav Mittal, Eddie Chan, Yuen H. Chan, Donald W. Plass, Sam G. Chu, Hung Q. Le, Leo Clark, John R. Ripley, Scott A. Taylor, Jack DiLullo, Mary Yvonne Lanzerotti	Design of the Power6 Microprocessor.	ISSCC	2007	DBLP DOI BibTeX RDF
12	Alan J. Drake, Robert M. Senger, Harmander Deogun, Gary D. Carpenter, Soraya Ghiasi, Tuyet Nguyen, Norman K. James, Michael S. Floyd, Vikas Pokala	A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor.	ISSCC	2007	DBLP DOI BibTeX RDF
12	Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz	Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.	ICCD	2007	DBLP DOI BibTeX RDF
12	Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin	Lazy Error Detection for Microprocessor Functional Units.	DFT	2007	DBLP DOI BibTeX RDF
12	Da Wang, Xiaoxin Fan, Xiang Fu 0007, Hui Liu, Ke Wen, Rui Li, Huawei Li 0001, Yu Hu 0001, Xiaowei Li 0001	The design-for-testability features of a general purpose microprocessor.	ITC	2007	DBLP DOI BibTeX RDF
12	Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham	Efficient Microprocessor Verification using Antecedent Conditioned Slicing.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin	An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration.	DAC	2007	DBLP DOI BibTeX RDF
12	Deepak Mathaikutty	Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design.		2007	RDF
12	Subir K. Roy	Top Level SOC Interconnectivity Verification Using Formal Techniques.	MTV	2007	DBLP DOI BibTeX RDF
12	Marc Herbstritt, Vanessa Struve, Bernd Becker 0001	Application of Lifting in Partial Design Analysis.	MTV	2007	DBLP DOI BibTeX RDF
12	Selma Ikiz, Alper Sen 0001	Runtime Verification of k-Mutual Exclusion for SoCs.	MTV	2007	DBLP DOI BibTeX RDF
12	Dam Sunwoo, Hassan Al-Sukhni, Jim Holt, Derek Chiou	Early Models for System-Level Power Estimation.	MTV	2007	DBLP DOI BibTeX RDF
12	Tommy Bojan, Igor Frumkin, Robert Mauri	Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning.	MTV	2007	DBLP DOI BibTeX RDF
12	Wang-Dauh Tseng, Lung-Jen Lee	Reduction of Power Dissipation during Scan Testing by Test Vector Ordering.	MTV	2007	DBLP DOI BibTeX RDF
12	Mark H. Nodine	Automatic Testbench Generation for Rearchitected Designs.	MTV	2007	DBLP DOI BibTeX RDF
12	Scott Little, Alper Sen 0001, Chris J. Myers	Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits.	MTV	2007	DBLP DOI BibTeX RDF
12	Franco Fummi, Cristina Marconcini, Graziano Pravadelli, Ian G. Harris	A CLP-Based Functional ATPG for Extended FSMs.	MTV	2007	DBLP DOI BibTeX RDF
12	Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil	A Scalable Symbolic Simulator for Verilog RTL.	MTV	2007	DBLP DOI BibTeX RDF
12	Wei Qin, Asa Ben-Tzur, Boris Gutkovich	An ADL for Functional Specification of IA32.	MTV	2007	DBLP DOI BibTeX RDF
12	Gaurav Singh 0006, Sandeep K. Shukla	Model Checking Bluespec Specified Hardware Designs.	MTV	2007	DBLP DOI BibTeX RDF
12	Sandip Ray, Warren A. Hunt Jr.	Mechanized Certification of Secure Hardware Designs.	MTV	2007	DBLP DOI BibTeX RDF
12	W. Di Palma, Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	Automotive Microcontroller End-of-Line Test via Software-Based Methodologies.	MTV	2007	DBLP DOI BibTeX RDF
12	Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.	MTV	2007	DBLP DOI BibTeX RDF
12	Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar	Assertion-Based Modal Power Estimation.	MTV	2007	DBLP DOI BibTeX RDF
12	Eric S. Fetzer, David M. Dahle, Casey Little, Kevin Safford	The Parity protected, multithreaded register files on the 90-nm itanium microprocessor.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
12	Keng L. Wong, Tawfik Rahal-Arabi, Matthew Ma, Greg Taylor	Enhancing microprocessor immunity to power supply noise with clock-data compensation.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
12	Aurangzeb Khan, Philip Watson, George Kuo, Due Le, Trung-Kien Nguyen, Steven Yang, Peter Bennett 0002, Pokai Huang, Jaspal Gill, Chris Hawkins, John Goodenough 0001, Demin Wang, Irfan Ahmed, Peter Tran, Helder Mak, Oanh Kim, Frank Martin, Yimu Fan, David Ge, Joseph Kung, Vincent Shek	A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
12	Jason M. Hart, Kyung T. Lee, Dennis Chen, Lik Cheng, Chipai Chou, Anand Dixit, Dale Greenley, Gregory Gruber, Kenneth Ho, Jesse Hsu, Naveen G. Malur, John Wu	Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
12	Veselko Gustin, Patricio Bulic	Learning computer architecture concepts with the FPGA-based "Move" microprocessor.	Comput. Appl. Eng. Educ.	2006	DBLP DOI BibTeX RDF
12	Adriana Dumitras, George S. Moschytz	The First Microprocessor: An Interview with Marcian (Ted) Hoff, Jr.	IEEE Signal Process. Mag.	2006	DBLP DOI BibTeX RDF
12	Ravi Mahajan, Chia-Pin Chiu, Greg Chrysler	Cooling a Microprocessor Chip.	Proc. IEEE	2006	DBLP DOI BibTeX RDF
12	Phillip T. Meade, Luis Rabelo, Albert T. Jones	Applications of chaos and complexity theories to the technology adoption life cycle: case studies in the hard-drive, microprocessor, and server high-tech industries.	Int. J. Technol. Manag.	2006	DBLP DOI BibTeX RDF
12	V. Lalith Kumar, S. T. I. C. Garividi	Microprocessor relay for protection of electrical systems.	Ubiquity	2006	DBLP DOI BibTeX RDF
12	Aki Penttinen, Rafal P. Jastrzebski, Riku Pöllänen, Olli Pyrhönen	Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor.	DDECS	2006	DBLP DOI BibTeX RDF
12	Chris Rowen	The Reinvention of the Microprocessor.	ERSA	2006	DBLP BibTeX RDF
12	Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra (eds.)	Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA	MTV	2006	DBLP BibTeX RDF
12	Michael Cowell, Adam Postula	Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs.	DSD	2006	DBLP DOI BibTeX RDF
12	Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry	Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units.	MICRO	2006	DBLP DOI BibTeX RDF
12	René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno, Jose Alberto Vite-Frias, Arturo Garcia-Perez	8-bit CISC Microprocessor Core for Teaching Applications in the Digital Systems Laboratory.	ReConFig	2006	DBLP DOI BibTeX RDF
12	David Allen, David M. Halliday, Andy M. Tyrrell	A Hybrid Bio-inspired System: Hardware Spiking Neural Network Incorporating Hebbian Learning with Microprocessor Based Evolutionary Control Algorithm.	IEEE Congress on Evolutionary Computation	2006	DBLP DOI BibTeX RDF
12	Ajit Dingankar, Deepak Mathaikutty, Sreekumar V. Kodakara, Sandeep K. Shukla, David J. Lilja	MMV: Metamodeling Based Microprocessor Valiation Environment.	HLDVT	2006	DBLP DOI BibTeX RDF
12	Øyvind Strøm	Verification and validation of Atmel's new 32 bit AVR microprocessor.	MBMV	2006	DBLP BibTeX RDF
12	Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev	Applying architectural vulnerability Analysis to hard faults in the microprocessor.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	hard-fault tolerance, reliability, computer architecture
12	Hiroaki Kokubo, Hiroaki Hataoka, Akinobu Lee, Tatsuya Kawahara, Kiyohiro Shikano	Embedded Julius: Continuous Speech Recognition Software for Microprocessor.	MMSP	2006	DBLP DOI BibTeX RDF
12	Nagm Mohamed, Nazeih Botros, Wei Zhang 0002	The Impact of Cache Organization in Optimizing Microprocessor Power Consumption.	CDES	2006	DBLP BibTeX RDF
12	Xiafii Lu, Yingqiong Luo, Hailin Yang, Wu Wang	Design of Bio-fermentation Control System Based on the Embedded Microprocessor.	CASE	2006	DBLP DOI BibTeX RDF
12	T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani	SEU Mitigation Techniques for Microprocessor Control Logic.	EDCC	2006	DBLP DOI BibTeX RDF
12	Chih-Lyang Hwang, Li-Jui Chang	Internet-Based Fuzzy Decentralized Microprocessor Control for a Two-Dimensional Piezo-Driven System.	SMC	2006	DBLP DOI BibTeX RDF
12	Vishnu Yalala, Derek Brasili, David Carlson, Adam Hughes, Anil Jain, Tim Kiszely, Kolar Kodandapani, Anand Varadharajan, Thucydides Xanthopoulos	A 16-Core RISC Microprocessor with Network Extensions.	ISSCC	2006	DBLP DOI BibTeX RDF
12	Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Erwin B. Cohen, Craig Atherton	Power Distribution Measurements of the Dual Core PowerPCTM 970MP Microprocessor.	ISSCC	2006	DBLP DOI BibTeX RDF
12	Michael G. R. Thomson, Phillip J. Restle, Norman K. James	A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor.	ISSCC	2006	DBLP DOI BibTeX RDF
12	Michael Golden, Srikanth Arekapudi, Greg Dabney, Mike Haertel, Stephen Hale, Lowell Herlinger, Yongg Kim, Kevin McGrath, Vasant Palisetti, Monica Singh	A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support.	ISSCC	2006	DBLP DOI BibTeX RDF
12	Héctor Sánchez, Bill Johnstone, Doug Roberts, Om Mandhana, Brad Melnick, Muhsin Celik, Mike Baker, Jim Hayden, Byoung Min, John Edgerton, Bruce White	Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors.	ISSCC	2006	DBLP DOI BibTeX RDF
12	Nathan Sadler, Daniel J. Sorin	Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache.	ICCD	2006	DBLP DOI BibTeX RDF
12	Kiran Puttaswamy, Gabriel H. Loh	Thermal analysis of a 3D die-stacked high-performance microprocessor.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	3D technology, thermals, power density
12	Alvaro Luiz Fazenda 0001, Eduardo Hidenori Enari, Luiz Flavio Rodrigues, Jairo Panetta	Towards Production Code Effective Portability among Vector Machines and Microprocessor-Based Architectures.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
12	Abraham Jacobus Johannes Mouton, C. Smith, George E. Smith	Wireless Control and Communication to Motor Protection Relays by using an Embedded Microprocessor.	CCECE	2006	DBLP DOI BibTeX RDF
12	Teresa L. McLaurin	The Challenge of Testing the ARM CORTEX-A8TM Microprocessor Core.	ITC	2006	DBLP DOI BibTeX RDF
12	Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin	Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier.	ITC	2006	DBLP DOI BibTeX RDF
12	Ismet Bayraktaroglu, Jim Hunt, Daniel Watkins	Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues.	ITC	2006	DBLP DOI BibTeX RDF
12	P. J. Tan, Tung Le, Keng-Hian Ng, Prasad Mantri, James Westfall	Testing of UltraSPARC T1 Microprocessor and its Challenges.	ITC	2006	DBLP DOI BibTeX RDF
12	Nehir Sönmez, Arda Yurdakul	SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-Core.	SoC	2006	DBLP DOI BibTeX RDF
12	Claudio Brunelli, Jari Nurmi	Design And Verification of a VHDL Model of a Floating-Point Unit for a RISC Microprocessor.	SoC	2006	DBLP DOI BibTeX RDF
12	Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge	Reliability modeling and management in dynamic microprocessor-based systems.	DAC	2006	DBLP DOI BibTeX RDF	dynamic reliability management, oxide breakdown, thermal cycling, modeling, electromigration
12	Hyun Sung Kim, D. M. H. Walker	Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits.	MTV	2006	DBLP DOI BibTeX RDF
12		Acknowledgement.	MTV	2006	DBLP DOI BibTeX RDF
12	Hiren D. Patel, Sandeep K. Shukla	Deep vs. Shallow, Kernel vs. Language--What is Better for Heterogeneous Modeling in {SystemC}?.	MTV	2006	DBLP DOI BibTeX RDF
12	Noah Bamford, Rekha Bangalore, Eric Chapman, Hector Chavez, Rajeev Dasari, Yinfang Lin, Edgar Jimenez	Challenges in System on Chip Verification.	MTV	2006	DBLP DOI BibTeX RDF
12		Preface.	MTV	2006	DBLP DOI BibTeX RDF
12		Workshop Organizing Committee.	MTV	2006	DBLP DOI BibTeX RDF
12	József Sziray	Test Calculation for Logic and Delay Faults in Digital Circuits.	MTV	2006	DBLP DOI BibTeX RDF	Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic