Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Michael Eisenring, Marco Platzner |
Optimization of Run-Time Reconfigurable Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 565-574, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Tom Kean |
It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 575-584, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima |
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 665-674, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Uwe Hatnik, Jürgen Haufe, Peter Schwarz |
An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 826-829, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Selene Maya, M. Rocio Reynoso, César Torres-Huitzil, Miguel O. Arias-Estrada |
Compact Spiking Neural Network Implementation in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 270-276, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | A. Hilton, J. Hall |
On Applying Software Development Best Practice to FPFAs in Safety Critical Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 793-796, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Mark Redekopp, Andreas Dandalis |
A Parallel Pipelined SAT Solver for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 462-468, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann 0001, Ulrich Nageldinger |
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 389-399, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
Multiple-Wordlength Resource Binding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 646-655, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Tsugio Makimoto |
The Rising Wave of Field Programmability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 1-6, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk |
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 361-370, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Darko Stefanovic, Margaret Martonosi |
On Availability of Bit-Narrow Operations in General-Purpose Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 412-421, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Frank-Michael Renner, Jürgen Becker 0001, Manfred Glesner |
Field Programmable Communication Emulation and Optimization for Embedded System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 58-67, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
architecture-precise rapid prototyping, field programmable emulation, Hardware/software codesign, real-time embedded systems |
13 | Bogdan Matasaru, Tudor Jebelean |
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 810-813, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Christophe Bobda, Thomas Lehmann 0001 |
Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 759-768, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Rob McCready |
Real-Time Face Detection on a Configurable Hardware System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 157-162, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Hamish Fallside, Michael John Sebastian Smith |
Internet Connected FPL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 48-57, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Joerg Abke, Erich Barke |
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 191-200, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Juanjo Noguera, Rosa M. Badia |
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 842-845, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Stephen J. Melnikoff, Philip James-Roxby, Steven F. Quigley, Martin J. Russell |
Reconfigurable Computing for Speech Recognition: Preliminary Findings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 495-504, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Hideharu Amano, Yuichiro Shibata, Masaki Uno |
Reconfigurable Systems: New Activities in Asia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 585-594, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | G. Lías, María Dolores Valdés, Miguel A. Domínguez, María José Moure |
Implementing a Fieldbus Interface Using an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 175-180, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada |
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 805-809, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Christian Siemers |
Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 769-772, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Brandon Blodget |
Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 797-800, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Jihan Zhu, George J. Milne |
Implementing Kak Neural Networks on a Reconfigurable Computing Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 260-269, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Javier Ramírez 0001, Antonio García 0001, Pedro G. Fernández, Luis Parrilla 0001, Antonio Lloris-Ruíz |
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 342-351, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn |
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 595-604, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Valery Sklyarov |
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 718-728, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | John Marty Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici |
Performance Penalty for Fault Tolerance in Roving STARs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 545-554, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Adaptive Computing System, Fault Tolerance, FPGA |
13 | Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh |
FPGA Implementation of a Prototype WDM On-Line Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 773-776, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Sriram Govindarajan, Ranga Vemuri |
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 7-18, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi |
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 729-738, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Bernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van Meerbergen |
Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 695-706, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Pawel Tomaszewicz |
Self-Testing of Linear Segments in User-Programmed FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 169-174, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Alfred Blaickner, O. Nagy, Herbert Grünbacher |
Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 322-331, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
digital receiver, FPGA, synchronization, Wireless, hardware/software co-design, software radio |
13 | Jim Tørresen |
Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 230-239, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna |
A Self-Reconfigurable Gate Array Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 106-120, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Helena Krupnova, Gabriele Saucier |
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 68-77, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Tero Rissa, Jarkko Niittylahti |
A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 371-378, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Thomas Bartzick, Michael Henze, Jens Kickler, Kai Woska |
Design of a Fault Tolerant FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 151-156, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Jörn Gause, Peter Y. K. Cheung, Wayne Luk |
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 96-105, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | André Brinkmann, Dominik Langen, Ulrich Rückert 0001 |
A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 838-841, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Stephen J. Bellis, William P. Marnane |
A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 485-494, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Oliver Diessel, George J. Milne |
Behavioural Language Compilation with Virtual Hardware Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 707-717, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Chris Phillips |
Wireless Base Station Design Using a Reconfigurable Communications Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 846-848, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | David Robinson, Patrick Lysaght |
Verification of Dynamically Reconfigurable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 141-150, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Andrej Trost, Andrej Zemva, Baldomir Zajc |
Educational Programmable Hardware Prototyping and Verification System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 818-821, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Johan Ditmar, Kjell Torkelsson, Axel Jantsch |
A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 19-28, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | E. Cantó, Juan Manuel Moreno, Joan Cabestany, Ignacio Lacadena, Josep Maria Insenser |
Implementation of Virtual Circuits by Means of the FIPSOC Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 87-95, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier |
Area-Optimized Technology Mapping for Hybrid FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 181-190, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Jan M. Rabaey |
Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 277-285, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Andrzej Krasniewski |
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 675-684, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Guy Lecurieux Lafayette |
Programmable System Level Integration Brings System-on-Chip Design to the Desktop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 789-792, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Andreas C. Döring, Gunther Lustig |
Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 626-635, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Radhika S. Grover, Weijia Shang, Qiang Li |
A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 422-431, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Rolf Hoffmann, Bernd Ulmann, Klaus-Peter Völkmann, Stefan Waldschmidt |
A Stream Processor Architecture Based on the Configurable CEPRA-S. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 822-825, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Michel Renovell |
A Specific Test Methodology for Symmetric SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 300-311, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano |
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 475-484, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Jens Hildebrandt, Dirk Timmermann |
An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 777-780, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman |
A Placement Algorithm for FPGA Designs with Multiple I/O Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 211-220, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Christine Bauer 0002, Peter Zipf, Hans Wojtkowiak |
System Design with Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 250-259, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Abdellah Touhafi |
A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 469-474, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Marios Iliopoulos, Theodore Antonakopoulos 0001 |
Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 39-47, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Jean-Michel Raczinski, Stéphane Sladek |
The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 834-837, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Milan Vasilko, Graham Benyon-Tinker |
Automatic Temporal Floorplanning with Guaranteed Solution Feasibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 656-664, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Petr Pfeifer |
Multifunctional Programmable Single-Board CAN Monitoring Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 163-168, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Student Papers, FPL2000, programmable device, ALTERA, FLEX6000, EPF6016, SJA1000, PC/104, CAN |
13 | Alexander Glasmacher, Kai Woska |
Design and Implementation of an XC6216 FPGA Model in Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 449-455, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Jernej Andrejas, Andrej Trost |
Reusable DSP Functions in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 456-461, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Hagen Ploog, Mathias Schmalisch, Dirk Timmermann |
Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 505-514, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Holger Kropp, Carsten Reuter |
A Mapping Methodology for Code Trees onto LUT-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 221-229, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Milan Vasilko |
Design Visualisation for Dynamically Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 131-140, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube |
Formal Verification of a Reconfigurable Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 781-784, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
13 | Donald Cottrell |
Design Automation Technology Roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
The VLSI Handbook ![In: The VLSI Handbook., 1999, CRC Press, 978-0-8493-8593-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Juan Manuel Ahuactzin, Kamal K. Gupta |
The kinematic roadmap: a motion planning based global approach for inverse kinematics of redundant robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Robotics Autom. ![In: IEEE Trans. Robotics Autom. 15(4), pp. 653-669, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Kwan-Liu Ma, Frits H. Post |
Guest Editors' Introduction: Visualization Case Studies-Drawing a Roadmap for Future Visualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Computer Graphics and Applications ![In: IEEE Computer Graphics and Applications 19(5), pp. 48-49, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | S. Sathiya Keerthi, Chong Jin Ong, Eugene Huang, Elmer G. Gilbert |
EquiDistance Diagram: A New Roadmap Method for Path Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 1999 IEEE International Conference on Robotics and Automation, Marriott Hotel, Renaissance Center, Detroit, Michigan, USA, May 10-15, 1999, Proceedings, pp. 682-687, 1999, IEEE Robotics and Automation Society. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Steven M. LaValle, Jeffery H. Yakey, Lydia E. Kavraki |
A Probabilistic Roadmap Approach for Systems with Closed Kinematic Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 1999 IEEE International Conference on Robotics and Automation, Marriott Hotel, Renaissance Center, Detroit, Michigan, USA, May 10-15, 1999, Proceedings, pp. 1671-1676, 1999, IEEE Robotics and Automation Society. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Nancy M. Amato, Lucia K. Dale |
Probabilistic Roadmap Methods are Embarrassingly Parallel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 1999 IEEE International Conference on Robotics and Automation, Marriott Hotel, Renaissance Center, Detroit, Michigan, USA, May 10-15, 1999, Proceedings, pp. 688-694, 1999, IEEE Robotics and Automation Society. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Valérie Boor, Mark H. Overmars, A. Frank van der Stappen |
The Gaussian Sampling Strategy for Probabilistic Roadmap Planners. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 1999 IEEE International Conference on Robotics and Automation, Marriott Hotel, Renaissance Center, Detroit, Michigan, USA, May 10-15, 1999, Proceedings, pp. 1018-1023, 1999, IEEE Robotics and Automation Society. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Steven A. Wilmarth, Nancy M. Amato, Peter F. Stiller |
MAPRM: A Probabilistic Roadmap Planner with Sampling on the Medial Axis of the Free Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 1999 IEEE International Conference on Robotics and Automation, Marriott Hotel, Renaissance Center, Detroit, Michigan, USA, May 10-15, 1999, Proceedings, pp. 1024-1031, 1999, IEEE Robotics and Automation Society. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Leonidas J. Guibas, Christopher Holleman, Lydia E. Kavraki |
A probabilistic roadmap planner for flexible objects with a workspace medial-axis-based sampling approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: Proceedings 1999 IEEE/RSJ International Conference on Intelligent Robots and Systems. Human and Environment Friendly Robots with High Intelligence and Emotional Quotients, October 17-21,1999, Hyundai Hotel, Kyongju, Korea, pp. 254-259, 1999, IEEE, 0-7803-5184-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Pier Luca Lanzi, Rick L. Riolo |
A Roadmap to the Last Decade of Learning Classifier System Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Learning Classifier Systems ![In: Learning Classifier Systems, From Foundations to Applications, pp. 33-62, 1999, Springer, 3-540-67729-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Nicholas R. Jennings, Katia P. Sycara, Michael J. Wooldridge |
A Roadmap of Agent Research and Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Auton. Agents Multi Agent Syst. ![In: Auton. Agents Multi Agent Syst. 1(1), pp. 7-38, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Michael Christoffel, Sebastian Pulkowski, Bethina Schmitt, Peter C. Lockemann |
Electronic Market: The Roadmap for University Libraries and Members to Survive in the Information Jungle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Rec. ![In: SIGMOD Rec. 27(4), pp. 68-73, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Ronald N. Kostoff, Henry J. Eberhart, Darrell Ray Toothman |
Database Tomography for Technical Intelligence: A Roadmap of the Near-Earth Space Science and Technology Literature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Process. Manag. ![In: Inf. Process. Manag. 34(1), pp. 69-85, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Rodney Thayer, Naganand Doraswamy, Rob Glenn |
IP Security Document Roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RFC ![In: RFC 2411, pp. 1-11, November 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Nancy M. Amato, O. Burçhan Bayazit, Lucia K. Dale, Christopher Jones, Daniel Vallejo |
Choosing Good Distance Metrics and Local Planners for Probabilistic Roadmap Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: Proceedings of the IEEE International Conference on Robotics and Automation, ICRA-98, Leuven, Belgium, May 16-20, 1998, pp. 630-637, 1998, IEEE Computer Society, 0-7803-4301-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Yong Yu 0005, Kamal Gupta 0001 |
On sensor-based roadmap: a framework for motion planning for a manipulator arm in unknown environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: Proceedings 1998 IEEE/RSJ International Conference on Intelligent Robots and Systems. Innovations in Theory, Practice and Applications, October 13-17, 1998, Victoria, BC, Canada, pp. 1919-1924, 1998, IEEE, 0-7803-4465-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | William R. Ortner |
How real is the new SIA roadmap for mixed-signal test equipment? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1153, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Phil Nigh |
SIA Roadmap: test must not limit future technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1152, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Wayne M. Needham |
Just how real is the SIA roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1151, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
13 | Alistair McLean |
Update and repair of a roadmap after model error discovery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Robotics Auton. Syst. ![In: Robotics Auton. Syst. 21(1), pp. 51-67, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
13 | Charles R. Merrill |
An Attorney's Roadmap to the Digital Signature Guidelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Financial Cryptography ![In: Financial Cryptography, First International Conference, FC '97, Anguilla, British West Indies, February 24-28, 1997, Proceedings, pp. 291-298, 1997, Springer, 3-540-63594-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
13 | Juan Manuel Ahuactzin, Kamal Gupta 0001 |
A motion planning based approach for inverse kinematics of redundant robots: the kinematic roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: Proceedings of the 1997 IEEE International Conference on Robotics and Automation, Albuquerque, New Mexico, USA, April 20-25, 1997, pp. 3609-3614, 1997, IEEE, 0-7803-3612-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
13 | Louis Scheffer |
A roadmap of CAD tool changes for sub-micron interconnect problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997, pp. 104-109, 1997, ACM, 0-89791-927-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
13 | Glenn Warnock, Douglas Reid, Maike Miller |
Roadmap to ATM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WebNet ![In: Proceedings of WebNet 97 - World Conference on the WWW, Internet & Intranet, Toronto, Canada, November 1-5, 1997, 1997, AACE, 1-880094-27-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP BibTeX RDF |
|
13 | Didier Dubois, Luis Fariñas del Cerro, Andreas Herzig, Henri Prade |
Qualitative Relevance and Independence: A Roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCAI (1) ![In: Proceedings of the Fifteenth International Joint Conference on Artificial Intelligence, IJCAI 97, Nagoya, Japan, August 23-29, 1997, 2 Volumes, pp. 62-67, 1997, Morgan Kaufmann. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP BibTeX RDF |
|
13 | Robert Glück, Morten Heine Sørensen |
A Roadmap to Metacomputation by Supercompilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Dagstuhl Seminar on Partial Evaluation ![In: Partial Evaluation, International Seminar, Dagstuhl Castle, Germany, February 12-16, 1996, Selected Papers, pp. 137-160, 1996, Springer, 3-540-61580-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
13 | Nancy M. Amato, Yan Wu |
A randomized roadmap method for path and manipulation planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: Proceedings of the 1996 IEEE International Conference on Robotics and Automation, Minneapolis, Minnesota, USA, April 22-28, 1996, pp. 113-120, 1996, IEEE, 0-7803-2988-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|