Search results for "jitter"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Dongwoo Hong, Kwang-Ting (Tim) Cheng	Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links.	VTS	2008	DBLP DOI BibTeX RDF	Bang-Bang CDR, BER Estimation
28	Alexander G. Dimitrov, Tomás Gedeon	Effects of stimulus transformations on estimates of sensory neuron selectivity.	J. Comput. Neurosci.	2006	DBLP DOI BibTeX RDF	Stimulus transformation, Sensory systems, Dejitter, Neural coding
28	Roberto Mitsuake Hirayama, Regina Melo Silveira	An Environment for Test and Evaluation of Synchronism for Digital Video Transmission.	WebMedia	2006	DBLP DOI BibTeX RDF	digital video transmission, resynchronization of MPEG2 transport streams, quality of service, digital TV
28	Idris A. Rai, Guillaume Urvoy-Keller, Mary K. Vernon, Ernst W. Biersack	Performance analysis of LAS-based scheduling disciplines in a packet switched network.	SIGMETRICS	2004	DBLP DOI BibTeX RDF	FCFS and LAS models, LAS-based scheduling and models, simulations, scheduling, models validation, service differentiation
28	Tingzhou Yang, Zhao Chen, Dimitrios Makrakis, Abdelhakim Hafid	A Study of AF and EF Services Interaction.	ICOIN	2001	DBLP DOI BibTeX RDF
27	T. H. Szymanski	Scheduling and Channel Assignment of Backhaul Traffic in Infrastructure Wireless Mesh Networks with Near-Minimal Delay and Jitter.	ICDS	2010	DBLP DOI BibTeX RDF	backhaul, low-jitter, scheduling, quality of service, wireless mesh network, TDMA, OFDMA, crossbar, relay network, input-queue
27	Kunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe	High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique.	VLSI Design	2010	DBLP DOI BibTeX RDF	Clock and data recovery (CDR), CDR jitter, Phase
27	Ramen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao 0002, Eric A. M. Klumperink	Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product.	VLSI Design	2010	DBLP DOI BibTeX RDF	tapering factor, stage ratio, CMOS inverter, mismatch jitter, multiphase clock, low power, figure of merit
27	Fan Chao, Yi-tao Liang, Ai-hong Guan	Influence Analysis of Jitter on Image Quality of Remote Sensing Camera.	ESIAT (1)	2009	DBLP DOI BibTeX RDF	remote sensing camera, image quality, jitter, image motion
27	Zheng Liu, Hai Zhao, Peng Li, Jialiang Wang	An Optimization Model for IO Jitter in Device-Level RTOS.	ITNG	2009	DBLP DOI BibTeX RDF	IO jitter, device-level, RTOS, optimization model
27	Linda Yunlu Bai, Yongfeng Huang 0001, Guannan Hou, Bo Xiao	Covert Channels Based on Jitter Field of the RTCP Header.	IIH-MSP	2008	DBLP DOI BibTeX RDF	RTCP Header, Jitter Field, Information Hiding, Covert Channel
27	Mouna Benaissa, Vincent Lecuire, Francis Lepage, André Schaff	Efficient De-Jitter Control for Voice Applications over Wireless Ad Hoc Networks.	Telecommun. Syst.	2005	DBLP DOI BibTeX RDF	voice packets, wireless ad hoc network, AODV, jitter control, speech quality, playout delay
27	Cathy A. Fulton, San-qi Li	Delay jitter first-order and second-order statistical functions of general traffic on high-speed multimedia networks.	IEEE/ACM Trans. Netw.	1998	DBLP DOI BibTeX RDF	QBD analysis, cell delay variation, multimedia, jitter, probability density function, autocorrelation function
27	Aleksandr Yu. Privalov, Khosrow Sohraby	Per-stream jitter analysis in CBR ATM multiplexors.	IEEE/ACM Trans. Netw.	1998	DBLP DOI BibTeX RDF	cell delay variation, cell-based networks, periodic arrivals, ATM, jitter, asymptotic analysis, statistical multiplexing
27	Lindsay Kleeman	The Jitter Model for Metastability and Its Application to Redundant Synchronizers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	jitter model, redundant synchronizers, circuit noise, CMOS D-type flip-flop, bistable device, simulation, circuit analysis computing, flip-flops, SPICE, CMOS integrated circuits, integrated logic circuits, reliability analysis, metastability, timing model, circuit analysis
26	Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada	All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.	DDECS	2009	DBLP DOI BibTeX RDF
26	Huthaifa Al-Omari, Francis G. Wolff, Christos A. Papachristou, David R. McIntyre	Avoiding Delay Jitter in Cyber-Physical Systems Using One Way Delay Variations Model.	CSE (2)	2009	DBLP DOI BibTeX RDF
26	Yongquan Fan, Zeljko Zilic	Accelerating jitter tolerance qualification for high speed serial interfaces.	ISQED	2009	DBLP DOI BibTeX RDF
26	Stefan Tertinek, Alexey Teplinsky, Orla Feely	Phase jitter dynamics of first-order digital phase-locked loops with frequency-modulated input.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Jeff Mueller, Resve A. Saleh	Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance.	VLSI Design	2008	DBLP DOI BibTeX RDF
26	Francesco Palmieri 0001, Gianmarco Romano, Elettra Venosa	A jitter model for OFDM systems.	CISS	2008	DBLP DOI BibTeX RDF
26	Richard H. R. Hahnloser	Cross-intensity functions and the estimate of spike-time jitter.	Biol. Cybern.	2007	DBLP DOI BibTeX RDF
26	Enrique Barajas, R. Cosculluela, D. Coutinho, Diego Mateo, José Luis González 0001, I. Cairò, S. Banda, M. Ikeda	Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems.	DATE	2007	DBLP DOI BibTeX RDF
26	Rafik Henia, Razvan Racu, Rolf Ernst	Improved Output Jitter Calculation for Compositional Performance Analysis of Distributed Systems.	IPDPS	2007	DBLP DOI BibTeX RDF
26	Stephen R. Gulliver, Gheorghita Ghinea	The Perceptual Influence of Multimedia Delay and Jitter.	ICME	2007	DBLP DOI BibTeX RDF
26	Philip M. Chopp, Anas A. Hamoui	Discrete-Time Modeling of Clock Jitter in Continuous-Time Delta Sigma Modulators.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Xiang Gao 0002, Eric A. M. Klumperink, Bram Nauta	Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Vijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin K. Mishra, Abhijit Abhyankar	A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL.	VLSI Design	2007	DBLP DOI BibTeX RDF
26	Henry H. Y. Chan, Zeljko Zilic	Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops.	DAC	2007	DBLP DOI BibTeX RDF
26	Teera Phatrapornnant, Michael J. Pont	Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	scheduling, Low power design, real-time systems and embedded systems
26	Nikos V. Kokkalis, P. Takis Mathiopoulos, George K. Karagiannidis, Christos S. Koukourlis	Performance analysis of M-ary PPM TH-UWB systems in the presence of MUI and timing jitter.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
26	Mitsuhiro Tanihata, Takao Waho	A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter.	ISMVL	2006	DBLP DOI BibTeX RDF
26	Hashem Zare-Hoseini, Izzet Kale	Continuous time delta sigma modulators with reduced clock jitter sensitivity.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang	Self-sampled vernier delay line for built-in clock jitter measurement.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Friedel Gerfers, Maurits Ortmanns, P. Schmitz	A transistor-based clock jitter insensitive DAC architecture.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Lu Ping, Ye Fan 0001, Junyan Ren	A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Linga Reddy Cenkeramaddi, Trond Ytterdal	Jitter analysis of general charge sampling amplifiers.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl, Martin Clara, Luis Hernández 0003, Daniel Gruber	Clock jitter compensation for current steering DACs.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Luis Hernández 0003, Susana Patón, Andreas Wiesbauer	Spectral shaping of clock jitter errors for continuous time sigma-delta modulators.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Paolo Ferrari, Alessandra Flammini, Daniele Marioli, Andrea Taroni, Francesco Venturini	Experimental analysis to estimate jitter in PROFINET IO Class 1 networks.	ETFA	2006	DBLP DOI BibTeX RDF
26	Javier Aracil 0001, José Alberto Hernández 0001, Kyriakos Vlachos, Emmanouel A. Varvarigos	Jitter-based analysis and discussion of burst assembly algorithms.	BROADNETS	2006	DBLP DOI BibTeX RDF
26	Chia-Yu Yao, Chun-Te Hsu, Chin-Chih Yeh	The Analysis of Phase-jitter Variance in the Third-order CPPLL Frequency Synthesizer.	APCCAS	2006	DBLP DOI BibTeX RDF
26	Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang	On-chip accumulated jitter measurement for phase-locked loops.	ASP-DAC	2005	DBLP DOI BibTeX RDF
26	Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury	Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise.	ASP-DAC	2005	DBLP DOI BibTeX RDF
26	Jeff Long, Michael C. Horsch	A Bayesian Model to Smooth Telepointer Jitter.	Canadian AI	2005	DBLP DOI BibTeX RDF
26	Anthony Chan Carusone	Jitter equalization for binary baseband communication.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
26	Kai Shi 0001, Yan Wang 0009, Erchin Serpedin	On the design of a digital blind feedforward, nearly jitter-free timing-recovery scheme for linear modulations.	IEEE Trans. Commun.	2004	DBLP DOI BibTeX RDF
26	Marcel A. Kossel, Martin L. Schmatz	Jitter Measurements of High-Speed Serial Links.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
26	Ajith S. Wakwella, Udantha R. Abeyratne, Yohsuke Kinouchi	Automatic segmentation and pitch/jitter tracking of sleep disturbed breathing sounds.	ICARCV	2004	DBLP DOI BibTeX RDF
26	Christo Angelov, Jesper Berthing	A Jitter-Free Kernel for Hard Real-Time Systems.	ICESS	2004	DBLP DOI BibTeX RDF
26	Moshe Ben-Ezra, Assaf Zomet, Shree K. Nayar	Jitter Camera: High Resolution Video from a Low Resolution Detector.	CVPR (2)	2004	DBLP DOI BibTeX RDF
26	Jui-Jer Huang, Jiun-Lang Huang	An Infrastructure IP for On-Chip Clock Jitter Measurement.	ICCD	2004	DBLP DOI BibTeX RDF
26	Chengxin Liu, John A. McNeill	Jitter in oscillators with 1/f noise sources.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
26	Bryan Nelson, Mani Soma	On-chip calibration technique for delay line based BIST jitter measurement.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
26	Yi-Ran Sun, Svante Signell	Effects of noise and jitter on algorithms for bandpass sampling in radio receivers.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
26	José Manuel Cazeaux, Martin Omaña 0001, Cecilia Metra	Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop.	IOLTS	2004	DBLP DOI BibTeX RDF
26	Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry C. Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz	Experimental Results for High-Speed Jitter Measurement Technique.	ITC	2004	DBLP DOI BibTeX RDF
26	Tony Pialis, Khoman Phang	Analysis of timing jitter in ring oscillators due to power supply noise.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
26	Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli	Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
26	Sami Karvonen, Thomas A. D. Riley, Juha Kostamovaara	On the effects of timing jitter in charge sampling.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
26	Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen	Minimizing Inter-Clock Coupling Jitter.	ISQED	2003	DBLP DOI BibTeX RDF
26	Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz	CMOS Built-In Test Architecture for High-Speed Jitter Measurement.	ITC	2003	DBLP DOI BibTeX RDF
26	Ola Redell, Martin Törngren	Calculating Exact Worst Case Response Times for Static Priority Scheduled Tasks with Offsets and Jitter.	IEEE Real Time Technology and Applications Symposium	2002	DBLP DOI BibTeX RDF
26	Thomas Nolte, Hans Hansson, Christer Norström	Minimizing CAN Response-Time Jitter by Message Manipulation.	IEEE Real Time Technology and Applications Symposium	2002	DBLP DOI BibTeX RDF
26	Konstantinos Doris, Arthur H. M. van Roermund, Domine Leenaerts	A general analysis on the timing jitter in D/A converters.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
26	Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha	Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division.	VTS	2002	DBLP DOI BibTeX RDF
26	Mike P. Li, Jan B. Wilstrup	On the Accuracy of Jitter Separation from Bit Error Rate Function.	ITC	2002	DBLP DOI BibTeX RDF
26	Jens-Uwe Klöcking, Christian Maihöfer, Kurt Rothermel	Reducing Multicast Inter-receiver Delay Jitter - A Server Based Approach.	ICN (1)	2001	DBLP DOI BibTeX RDF
26	Abdelohahab Djemouai, Mohamad Sawan	Fast-locking low-jitter integrated CMOS phase-locked loop.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
26	Keith A. Jenkins, James P. Eckhardt	Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
26	Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney	A New Approach for Computation of Timing Jitter in Phase Locked Loops.	DATE	2000	DBLP DOI BibTeX RDF
26	Sanjeev Kumar Maheshwari, R. S. Krishanan, G. S. Visweswaran	Jitter Estimation Methodology for Clock Chips.	VLSI Design	2000	DBLP DOI BibTeX RDF
26	Alexey Teplinsky, Orla Feely	Phase-jitter dynamics in second-order DPLLs with irrational and integer input frequencies.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
26	Dorin Emil Calbaza, Yvon Savaria	Jitter model of direct digital synthesis clock generators.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
26	Kwei-Jay Lin, Ansgar Herkert	Jitter Control in Time-Triggered Systems.	HICSS (1)	1996	DBLP DOI BibTeX RDF
24	Anshul Verma, Bishnu Prasad Das	A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter.	VLSID	2024	DBLP DOI BibTeX RDF
24	Shahram Modanlou, Gholamreza Ardeshir, Mohammad Gholami	A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
24	Zhao Zhang 0004, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu 0021, Yong Chen, Nanjian Wu, Liyuan Liu	A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.	ISSCC	2023	DBLP DOI BibTeX RDF
24	Yixi Li, Zhao Zhang 0004, Yong Chen 0005, Xinyu Shen, Zhao Zhang, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM.	A-SSCC	2023	DBLP DOI BibTeX RDF
24	Yongjo Kim, Taekwang Jang, SeongHwan Cho	A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor.	A-SSCC	2023	DBLP DOI BibTeX RDF
24	Simone Zini, Alex Gomez-Villa, Marco Buzzelli, Bartlomiej Twardowski, Andrew D. Bagdanov, Joost van de Weijer 0001	Planckian Jitter: countering the color-crippling effects of color jitter on self-supervised training.	ICLR	2023	DBLP BibTeX RDF
24	Yu Duan, Chi-Hang Chan, Yan Zhu 0001, Rui Paulo Martins	Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
24	Özgenç Subasi	Control and filtering methods for causes and reduction of jitter formation on optical beam: Various applications in optical space communication (Optik hüzme üzerinde jitter oluşumunun nedenleri ve azaltılmasına yönelik kontrol ve filtreleme yöntemleri: Optik uzay iletişiminde çeşitli uygulamalar)		2022	RDF
24	Nan Ren, Zaiming Fu, Dandan Zhou, Dexuan Kong, Shulin Tian	PointNet-Based Jitter Decomposition on Point Cloud of Jitter Histogram.	ISCAS	2021	DBLP DOI BibTeX RDF
24	Eulalia Balestrieri, Luca De Vito, Francesco Lamonaca, Francesco Picariello, Sergio Rapuano, Ioan Tudosa	The jitter measurement ways: The jitter decomposition.	IEEE Instrum. Meas. Mag.	2020	DBLP DOI BibTeX RDF
24	Dongjun Park, Jongsun Kim	A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
24	Jaehong Jung, Sangdon Jung, Kyungmin Lee, Jun-Hee Jung, Seungjin Kim, Byungki Han, Seunghyun Oh, Jongwoo Lee	A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
24	Elie Noumon Allini	Characterisation, evaluation and use of clock jitter as a source of randomness in data security. (Caractérisation, évaluation et utilisation du jitter d'horloge comme source d'aléa dans la sécurité des données).		2020	RDF
24	Eulalia Balestrieri, Francesco Picariello, Sergio Rapuano, Ioan Tudosa	The jitter measurement ways: The jitter graphs.	IEEE Instrum. Meas. Mag.	2019	DBLP DOI BibTeX RDF
24	Xiaofeng Yang 0004, Chi-Hang Chan, Yan Zhu 0001, Rui Paulo Martins	A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT.	ISSCC	2019	DBLP DOI BibTeX RDF
24	Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi	On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
24	Yen-Long Lee, Yu-Po Cheng, Soon-Jyh Chang, Hsin-Wen Ting	A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs.	IEEE Des. Test	2018	DBLP DOI BibTeX RDF
24	Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi	Jitter injection for on-chip jitter measurement in PI-based CDRs.	CICC	2017	DBLP DOI BibTeX RDF
24	Shravan K. Chaganti, Li Xu, Degang Chen 0001	A low-cost method for separation and accurate estimation of ADC noise, aperture jitter, and clock jitter.	VTS	2017	DBLP DOI BibTeX RDF
24	Masahiro Ishida, Kiyotaka Ichiyama	A jitter separation and BER estimation method for asymmetric total jitter distributions.	ITC	2017	DBLP DOI BibTeX RDF
24	Yuki Ozawa, Takuya Arafune, Nobukazu Tsukiji, Haruo Kobayashi 0001, Ryoji Shiota	Study of jitter generators for high-speed I/O interface jitter tolerance testing.	ISPACS	2017	DBLP DOI BibTeX RDF
24	Shuta Masuda, Satoshi Saikatsu, Michitaka Yoshino, Akira Yasuda	A delta-sigma DAC with feedforward jitter-shaper reducing jitter noise.	MIXDES	2017	DBLP DOI BibTeX RDF
24	Mohammad Gholami	Total Jitter of Delay-Locked Loops Due to Four Main Jitter Sources.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
24	Lukas Drzewietzki, Christoph Weber, Stefan Breuer	Stability criteria of a tapered InAs/InGaAs quantum dot laser based on pulse amplitude jitter and timing jitter investigations.	ICTON	2016	DBLP DOI BibTeX RDF
24	Madhu Babu Sikha, R. Manivasakan	On the rate-jitter performance of jitter-buffer in TDMoPSN: study using queueing models with a state-dependent service.	Photonic Netw. Commun.	2015	DBLP DOI BibTeX RDF