Search results for "switches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Ming Hao, Mark A. Heinrich	Active I/O Switches in System Area Networks.	HPCA	2003	DBLP DOI BibTeX RDF
23	Eryk Laskowski, Marek Tudruj	Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches.	FPL	2003	DBLP DOI BibTeX RDF
23	Mei Yang, Si-Qing Zheng	Pipelined Maximal Size Matching Scheduling Algorithms for CIOQ Switches..	ISCC	2003	DBLP DOI BibTeX RDF
23	Sang-Ho Lee, Dong Ryeol Shin	A Simple Pipelined Scheduling for Input-Queued Switches.	ISCIS	2003	DBLP DOI BibTeX RDF
23	Sudeep Pasricha, Alexander V. Veidenbaum	Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches.	ICCD	2003	DBLP DOI BibTeX RDF
23	Eryk Laskowski	Program Structuring Heuristics for Parallel Systems Based on Multiple Crossbar Switches.	PPAM	2003	DBLP DOI BibTeX RDF
23	Bor-Ren Lin, Tsung-Yu Yang, Yung-Chuan Lee	Three-phase high-power-factor rectifier with three AC power switches.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
23	Tetsuya Kobayashi, Luonan Chen, Kazuyuki Aihara	Design of Genetic Switches with Only Positive Feedback Loops.	CSB	2002	DBLP DOI BibTeX RDF	monotone dynamical system, stability, delay, switch, genetic network
23	Magnus Jonsson	Optical Interconnection Technology in Switches, Routers and Optical Cross Connects.	ICPP Workshops	2001	DBLP DOI BibTeX RDF
23	Kåre Tais Christensen	Design and optimization of CMOS switches for switched tuning of LC resonators.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
23	Olav Lysne	Deadlock Avoidance for Switches Based on Wormhole Networks.	ICPP	1999	DBLP DOI BibTeX RDF	Inter-switch deadlocks, Interconnect networks, Wormhole routing, Deadlock avoidance, Switch fabric
23	Guogen Zhang, William G. Bulgren, Victor L. Wallace	A Performance Model of Space-Division ATM Switches with Input and Output Queueing.	HICSS (1)	1996	DBLP DOI BibTeX RDF
23	Karen Anne Cochrane, Chau Nguyen, Yidan Cao, Noemi M. E. Roestel, Lee Jones, Audrey Girouard	Adaptive Soft Switches: Co-Designing Fabric Adaptive Switches with Occupational Therapists for Children and Adolescents with Acquired Brain Injury.	TEI	2023	DBLP DOI BibTeX RDF
23	Robert Stala, Maciej Chojowski, Zbigniew Waradzyn, Andrzej Mondzik, Szymon Folmer, Adam Penczek, Aleksander Skala, Stanislaw Pirog	High-Gain Switched-Capacitor DC-DC Converter With Low Count of Switches and Low Voltage Stress of Switches.	IEEE Access	2021	DBLP DOI BibTeX RDF
23	Gubbi Vani HarshaRani, S. Moza, Naren Ramakrishnan, Upinder S. Bhalla	SWITCHES: Searchable Web Interface for Topologies of CHEmical Switches.	Bioinform.	2021	DBLP DOI BibTeX RDF
23	Guanyu Li, Menghao Zhang, Cheng Guo, Han Bao 0011, Mingwe Xu, Hongxin Hu	Switches are Scanners Too!: A Fast and Scalable In-Network Scanner with Programmable Switches.	HotNets	2021	DBLP DOI BibTeX RDF
23	S. A. Ahamed Ibrahim, P. Anbalagan, Mohamed Ali Jagabar Sathik	A New Asymmetric and Cascaded Switched Diode Multilevel Inverter Topology for Reduced Switches, DC Source and Blocked Voltage on Switches.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
23	Changying Wu, Zhou Yang, Yusheng Li, Yuan Zhang, Yevhen Yashchyshyn	Methodology to Reduce the Number of Switches in Frequency Reconfigurable Antennas With Massive Switches.	IEEE Access	2018	DBLP DOI BibTeX RDF
23	Petar K. Pepeljugoski, Nicolas Dupuis, Benjamin G. Lee	Scalability of optical circuit switches using 2×2 Mach-Zehnder switches as a building block.	OFC	2016	DBLP BibTeX RDF
23	David A. Sanders, Martin Langner, Giles Tewkesbury	Improving wheelchair-driving using a sensor system to control wheelchair-veer and variable-switches as an alternative to digital-switches or joysticks.	Ind. Robot	2010	DBLP DOI BibTeX RDF
23	Gert Schley, Martin Radetzki, Adán Kohler	Degradability Enabled Routing for Network-on-Chip Switches (Routingverfahren zur Unterstützung der Degradierbarkeit von Network-on-Chip Switches).	it Inf. Technol.	2010	DBLP DOI BibTeX RDF
23	Claus Bauer	Packet scheduling in input-queued switches with a speedup of less than two and scheduling algorithms for switches with a configuration overhead.	Comput. Commun.	2005	DBLP DOI BibTeX RDF
23	Peifang Zhou, Oliver W. W. Yang	Design and analysis of per-flow queueing switches and VC-merge switches based on per-VC queueing architecture.	Comput. Commun.	2000	DBLP DOI BibTeX RDF
23	D. Manjunath, Biplab Sikdar 0001	Variable Length Packet Switches: Delay Analysis of Crossbar Switches under Poisson and Self Similar Traffic.	INFOCOM	2000	DBLP DOI BibTeX RDF
23	Soung C. Liew, Tony T. Lee	SKEL: A Fundamental Property Desirable in ATM Switches for Simple Traffic Management - Illustrations with Generic Output-Buffered and Input-Buffered Switches.	Perform. Evaluation	1996	DBLP DOI BibTeX RDF
21	Hamed F. Dadgour, Muhammad Mustafa Hussain, Kaustav Banerjee	A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs.	ISLPED	2010	DBLP DOI BibTeX RDF	Boolean logic minimization, energy-efficient electronics, laterally-actuated NEMS, nanoelectromechanical switches, XOR gates
21	Hamed F. Dadgour, Muhammad Mustafa Hussain, Casey Smith, Kaustav Banerjee	Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS.	DAC	2010	DBLP DOI BibTeX RDF	energy-efficient electronics, laterally-actuated NEMS, nano-electro-mechanical switches, steep-subthreshold switch, logic design, process variation
21	Jonathan S. Turner	Strong performance guarantees for asynchronous buffered crossbar scheduler.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	asynchronous crossbars, crossbar schedulers, routers, switches, performance guarantees
21	Ilias Iliadis, Cyriel Minkenberg	Performance of a speculative transmission scheme for scheduling-latency reduction.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	electrooptic switches, scheduling, modeling, packet switching, arbiters
21	Soung-Yue Liew, Andrew Khin Huat Tan, Elok Robert Tee	A Time Slotted Model for All-Optical Variable-Length Packet Switching without Packet Alignment.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	All optical switches, Slotted switching, Packet alignment, variable Length, Model, Algorithms
21	Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff	Optimizing general purpose compiler optimization.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	back-end optimization, compiler switches, compiler tuning, statistical analysis
21	Ravi R. Iyer 0001, Laxmi N. Bhuyan	Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures
21	Hea-Sook Park, Sung-Jin Moon, Man-Sik Park, Boseob Kwon, Kwang-Suk Song	Design of inter processor communication controller using ATM switch and analysis of its optimal message length considering retransmission.	RTCSA	1997	DBLP DOI BibTeX RDF	inter processor communication controller, optimal message length, distributed large-scale multiprocessors, ATM adaptation layer, message error rate, message retransmission rate, asynchronous transfer mode, ATM switch, asynchronous transfer mode switches
21	Pil Joong Kim, Yeon Lee, Woon-Sik Kim, Kwangil Lee, Sang-Ha Kim 0001	A simulation study of interoperative methods for congestion control over TCP/AT.	ICPADS	1997	DBLP DOI BibTeX RDF	interoperative methods, TCP/ATM, ATM rate-based flow controls, interoperative method, SIMNET, performance, congestion control, resource management, transport protocols, ATM switches, simulation study, buffer requirement, NIST, cell losses
21	Chengzhi Li, Riccardo Bettati, Wei Zhao 0001	Static priority scheduling for ATM networks.	RTSS	1997	DBLP DOI BibTeX RDF	dynamic priority scheduling, delay computation, priority assignment problems, potential cyclic dependency, unstable network, delay sensitive applications, worst case end to end delays, priority assignment methods, asynchronous transfer mode, ATM networks, numerical method, ATM switches, packet delays, arbitrary topology, delay constraints, priority assignment, traffic scheduling, static priority scheduling, computing error
21	Young-Wook Cha, Jong-Oh Kim, Kyou-Ho Lee, Ki Jun Han	Multiaccess ATM Network for Residential and Small Business Subscribers.	LCN	1996	DBLP DOI BibTeX RDF	OAM reference model, small business subscribers, residential subscribers, shared medium-based multiaccess technology, switch port granularity, multiaccess ATM customer network, asynchronous transfer mode, switches, network architecture, connection management, connection control
21	Nen-Fu Huang, Chi-An Su, Chieh-Wen Cheng, Chuan-Pwu Wang, Jer-Han Fang, Yi-Jang Wu	The Design and Implementation of a Multicast Real-Time Multimedia Protocol.	LCN	1996	DBLP DOI BibTeX RDF	multicast real-time multimedia protocol, performance contract, multicast function, interconnected ATM switches, QoS guaranteed protocol, quality of service, delay, admission control, transport protocols, group communications, communication networks, bandwidth, multimedia communications, multimedia applications, packet scheduling, routers, high-speed network, resource reservation, data transmission, telecommunication channels, FDDI networks, delay jitter, jitter control
21	Bradley C. Kuszmaul	The RACE network architecture.	IPPS	1995	DBLP DOI BibTeX RDF	RACE network architecture, high-performance parallel interconnection network, 6-port switches, preemptable circuit switched strategy, self-regulating circuit, output delay, performance evaluation, real-time systems, parallel architectures, mesh, real-time constraints, Clos network, fat-tree, parallel computer system
21	Sabine R. Öhring, Maximilian Ibel, Sajal K. Das 0001, Mohan Kumar	On generalized fat trees.	IPPS	1995	DBLP DOI BibTeX RDF	generalized fat trees, multiprocesser interconnection networks, connection machine architecture, pruned butterflies, fat tree based architecture, inner nodes, leaf processors, recursive scalability, maximal fault-tolerance, logarithmic diameter bisection scalability, fault tolerant self-routing, reliability, parallel architectures, fault tolerant computing, broadcasting, hypercubes, multiprocessor interconnection networks, trees, meshes, communication complexity, symmetry, routers, network routing, switches, rings, pyramids, tori, CM-5
21	Young-Keun Park, Gyungho Lee	ATM cell scheduling with queue length-based priority scheme.	ICCCN	1995	DBLP DOI BibTeX RDF	ATM cell scheduling, queue length based priority scheme, nonblocking switch, optimal input bypass queueing method, switch throughput maximisation, cell delay variations, delay variance, cell loss rate, neural network, asynchronous transfer mode, asynchronous transfer mode, ATM switches, buffer size, B-ISDN, FIFO queueing, nonuniform traffic, head-of-line blocking, input queues, cell loss probabilities
21	Latha A. Kant, William H. Sanders	Loss process analysis of the knockout switch using stochastic activity networks.	ICCCN	1995	DBLP DOI BibTeX RDF	loss process analysis, knockout switch, fast packet switches, consecutive cell losses, tagged port, telecommunication switch design, quality of service, performance, asynchronous transfer mode, asynchronous transfer mode, Markov processes, ATM networks, bursty traffic, B-ISDN, stochastic activity networks, cell loss probability
21	Fukiko Hidano	Signalling on ATM testbeds: an example.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	telecommunication signalling, telecommunication equipment testing, high-speed links, high-speed switches, ATM testbeds, XUNET testbed, vic, real-time systems, multimedia, protocols, asynchronous transfer mode, multimedia communication, real-time applications, high-speed networking, videoconferencing, signalling, teleconferencing, quality of service guarantees, ISDN, ISDN, virtual circuits, signalling protocols
21	Thomas Scholz, Michael Schäfers 0003	An improved dynamic register array concept for high-performance RISC processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	dynamic register array concept, high-performance RISC processors, processor registers, Multi Windows, Threaded Windows, dynamic register array, dynamic register allocation, general purpose registers, fast context switches, short interrupt latency, exception routines, real time systems, data structures, data structures, interrupts, storage allocation, external memory, registers, reduced instruction set computing
21	Sangho Ha, Sangyong Han, Heunghwan Kim	Partitioning a lenient parallel language into sequential threads.	HICSS (2)	1995	DBLP DOI BibTeX RDF	lenient parallel language, language partitioning, sequential threads, multithreaded architecture performance, large-scale parallel system, split-phase memory operations, fast context switching, multithreaded code quality, enhanced thread formation scheme, Id/sup -/, long latency instructions, multiple switches, generalized switch-and-merge, thread merging, redundant arc elimination, thread precedence relations, control instructions, DAVRID multithreaded architecture, simulation, graph theory, parallel architectures, graph partitioning, switching, merging, parallel languages, large-scale systems, program control structures, branch instructions
21	Bassem A. Alhalabi, Magdy A. Bayoumi	A scalable analog architecture for neural networks with on-chip learning and refreshing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	analogue storage, scalable analog architecture, on-chip learning, on-chip refreshing, analog storage, analog functional blocks, analog pass switches, system versatility, learning speed, local analog synaptic updating scheme, unbounded scalability, neural networks, learning (artificial intelligence), neural chips, analogue processing circuits
21	Dinesh Bhatia, James Haralambides	Resource requirements for field programmable interconnection chips.	VLSI Design	1995	DBLP DOI BibTeX RDF	field programmable interconnection chips, n-permutation graph, network property, routing delays, programmable switches, routing paths, specific I/O permutations, user-configured interconnection, VLSI, VLSI, graph theory, network routing, permutation networks, integrated circuit interconnections, Benes network
21	Seung-Woo Seo, Paul R. Prucnal	Transparent optical networks for high-performance distributed computing .	FTDCS	1995	DBLP DOI BibTeX RDF	transparent optical networks, optical time-division multiplexing, multi-terahertz bandwidth, electro-optic conversion, low-loss photonic switches, optical data processing unit, ultra-fast optical networks, wavelength-division multiplexing, time division multiplexing, optical fibre LAN, high-performance distributed computing, switch controller
21	Ronald D. Fellman, Robert Grygiel, Isaac Chu	The effect of preemptive queuing in a priority-based real-time network.	ICECCS	1995	DBLP DOI BibTeX RDF	preemptive queuing, priority-based real-time network, real-time multiprocessor system, interprocessor communications network entrance, data buffering, simulations, performance evaluation, real-time systems, virtual machines, multiprocessor interconnection networks, queueing theory, packet switching, packet switches, performance improvement
21	Chao-Ju Hou, Ching-Chih Han, Wun-Chun Chau	Priority-based high-speed switch scheduling for ATM networks.	LCN	1995	DBLP DOI BibTeX RDF	iterated switching networks, priority-based high-speed switch scheduling, AN2 switch, parallel iterative matching algorithm, maximal input-output matching, priority lists, input/output pairs, probability analysis, switch size, high QoS requirements, simulation, scheduling, parallel algorithms, computational complexity, asynchronous transfer mode, probability, local area networks, iterative methods, time complexity, ATM networks, iterations, switches, high-performance distributed computing
21	Randolph G. Foldvik, David Meyer	Moving towards ATM: LAN/WAN evolution and experimentation at the University of Oregon.	LCN	1995	DBLP DOI BibTeX RDF	WAN evolution, LAN evolution, Oregon University, US WEST, technical ATM equipment trial, ATM services, ATM connectivity, high-end desktop workstations, high-end routers, customer-owned ATM switches, public ATM services, legacy LANs, ATM switched virtual circuits, ATM permanent virtual circuits, local networking capabilities, WAN experimentation, LAN experimentation, protocols, asynchronous transfer mode, ATM, local area networks, wide area networks, educational technology, telecommunication network routing, workstations, IP networking, LAN interconnection, educational computing, optical fibre LAN
21	Russell J. Clark 0001, Ronald R. Hutchins	Deploying ATM in a data network: an analysis of SVC requirements.	LCN	1995	DBLP DOI BibTeX RDF	telecommunication traffic recording, telecommunication switching, campus data networks, SVC requirements, connectionless network layer protocols, connection-oriented service, call setups, concurrent SVCs, large campus networks, circuit-based network, networking requirements, college campus, IP traffic logs, ATM deployment scenarios, circuit replacement algorithms, SVC setup rates, hold times, switched virtual circuits, asynchronous transfer mode, ATM, local area networks, IP, educational technology, ATM switches, educational computing, data network
21	C. S. Yang, L. P. Zu, Y. N. Wu	A Reconfigurable Modular Fault-Tolerant Hypercube Architecture.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	reconfigurable modular fault-tolerant hypercube, modular hypercube, spare-sharing links, ring connection, local spares, FTM, switch failures, modular reconfiguration, reliability, parallel architectures, fault tolerant computing, reconfigurable architectures, hypercube networks, switches, system recovery, links, nodes, system reliability, link failures, fault-tolerant design, faulty nodes, hypercube system, hypercube architecture
21	M. Sultan Alam, Rami G. Melhem	An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	modular spare allocation scheme, fault tolerant binary hypercubes, fault tolerant basicblocks, primary nodes, spare nodes, hardware switches, fault tolerant computing, multiprocessing systems, hypercube networks
21	Philip J. Bernhard, Daniel J. Rosenkrantz	Using the Dual Path Property of Omega Networks to Obtain Conflict-Free Message Routing.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	source processors, disjoint network routes, bidirectional network links, bidirectionalnetwork switches, dual path, conflict-free message routing, communication conflicts, destination processors, circuit switchingmode, conflict-free message transmission, message switching, algorithm, parallel algorithms, omega networks, multiprocessorinterconnection networks, message patterns
18	Mohammad Alizadeh, Albert G. Greenberg, David A. Maltz, Jitendra Padhye, Parveen Patel, Balaji Prabhakar, Sudipta Sengupta, Murari Sridharan	Data center TCP (DCTCP).	SIGCOMM	2010	DBLP DOI BibTeX RDF	TCP, ECN, data center network
18	Guohui Wang, David G. Andersen, Michael Kaminsky, Konstantina Papagiannaki, T. S. Eugene Ng, Michael Kozuch, Michael P. Ryan	c-Through: part-time optics in data centers.	SIGCOMM	2010	DBLP DOI BibTeX RDF	optical circuit switching, hybrid network, data center networking
18	Martín Casado, Michael J. Freedman, Justin Pettit, Jianying Luo, Natasha Gude, Nick McKeown, Scott Shenker	Rethinking enterprise network control.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	security, architecture, network, management
18	Priya Mahadevan, Puneet Sharma, Sujata Banerjee, Parthasarathy Ranganathan	A Power Benchmarking Framework for Network Devices.	Networking	2009	DBLP DOI BibTeX RDF	Network energy management, Benchmarking
18	Yury Audzevich, Levente Bodrog, Yoram Ofek, Miklós Telek	Packet Loss Analysis of Load-Balancing Switch with ON/OFF Input Processes.	EPEW	2009	DBLP DOI BibTeX RDF
18	Nick McKeown, Thomas E. Anderson, Hari Balakrishnan, Guru M. Parulkar, Larry L. Peterson, Jennifer Rexford, Scott Shenker, Jonathan S. Turner	OpenFlow: enabling innovation in campus networks.	Comput. Commun. Rev.	2008	DBLP DOI BibTeX RDF	ethernet switch, flow-based, virtualization
18	Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen	Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, systems on chips, networks on chip, interconnection, Application specific
18	Ali Rajabi, Aresh Dadlani, Farhad Hormozdiari, Ahmad Khonsari, Ahmad Kianrad, Hassan Seyed Razi	Analysis of the Impact of Wavelength Converters on Contention Resolution in Optical Burst Switching.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF
18	Fan Yan, Kai-Hau Yeung	The development of novel switching devices by using embedded microprocessing system running linux.	IPDPS	2008	DBLP DOI BibTeX RDF
18	Lotfi Mhamdi	A Partially Buffered Crossbar packet switching architecture and its scheduling.	ISCC	2008	DBLP DOI BibTeX RDF
18	Xiaoliang Wang 0001, Xiaohong Jiang 0001, Susumu Horiguchi	Maintaining Packet Order in Reservation-Based Shared-Memory Optical Packet Switch.	AINA	2008	DBLP DOI BibTeX RDF	Shared-Memory Optical Packet, Maintaining Packet Order
18	Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi	Impact of topology and link aggregation on a PC cluster with Ethernet.	CLUSTER	2008	DBLP DOI BibTeX RDF
18	Rongsen He, José G. Delgado-Frias	Fault Tolerant Interleaved Switching Fabrics For Scalable High-Performance Routers.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Interleaved switching fabrics, RAIF (Redundant Array of Independent Fabrics), I-Cubeout network, multistage interconnection network (MIN)
18	Farhad Hormozdiari, Ali Rajabi, Ahmad Khonsari	Mathematical Analysis of Delay Line to Wavelength Allocation Algorithmsin Optical Networks.	MASCOTS	2007	DBLP DOI BibTeX RDF
18	Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi	Using the inter- and intra-switch regularity in NoC switch testing.	DATE	2007	DBLP DOI BibTeX RDF
18	Cyriel Minkenberg, Mitchell Gusat	Speculative Flow Control for High-Radix Datacenter Interconnect Routers.	IPDPS	2007	DBLP DOI BibTeX RDF
18	Joachim Hillebrand, Mehrnoush Rahmani, Richard Bogenberger, Eckehard G. Steinbach	Coexistence of Time-Triggered and Event-Triggered Traffic in Switched Full-Duplex Ethernet Networks.	SIES	2007	DBLP DOI BibTeX RDF
18	Asha Andrade, Ungzu Mun, Dong Hwan Chung, Alexander E. Mohr	Hybrid Host/Network Topologies for Massive Storage Clusters.	MSST	2007	DBLP DOI BibTeX RDF
18	Tiago Fioreze, Remco van de Meent, Aiko Pras	An Architecture for the Self-management of Lambda-Connections in Hybrid Networks.	EUNICE	2007	DBLP DOI BibTeX RDF
18	Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min	Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs.	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Hamed F. Dadgour, Kaustav Banerjee	Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications.	DAC	2007	DBLP DOI BibTeX RDF
18	Xiaoliang Wang 0001, Xiaohong Jiang 0001, Susumu Horiguchi	CBX-1 Switch: An Effective Load Balanced Switch.	PDCAT	2007	DBLP DOI BibTeX RDF
18	Hongbing Fan, Yu-Liang Wu, Ray Chak-Chung Cheung, Jiping Liu	Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	reconfigurable interconnection network, switch block, hyperuniversal, FPGA, universal, switch box
18	Kushal Datta, Arindam Mukherjee 0001, Arun Ravindran	Automated design flow for diode-based nanofabrics.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Automatic synmthesis, optimization
18	Eryk Laskowski, Marek Tudruj	Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources.	DSD	2006	DBLP DOI BibTeX RDF
18	Biju K. Raveendran, Sundar Balasubramaniam, K. Durga Prasad, S. Gurunarayanan 0001	A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
18	Wilson Eberle, Yan-Fei Liu, Paresh C. Sen	A Simple Large Signal Model for Isolated DC-DC Converters.	CCECE	2006	DBLP DOI BibTeX RDF
18	Akbar Ghaffar Pour Rahbar, Mushi Jin, Choudhury A. Al Sayeed, Oliver W. W. Yang	Aposn Performance Under the Man and Wan Environments.	CCECE	2006	DBLP DOI BibTeX RDF
18	Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume	Energy-efficient FPGA interconnect architecture design (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
18	Sameer Kumar 0001, Craig B. Stunkel, Laxmikant V. Kalé	Improved Point-to-Point and Collective Communication Performance with Output-Queued High-Radix Routers.	HiPC	2005	DBLP DOI BibTeX RDF
18	Alvaro Munoz, Sanjeev Kumar	Effect of Unbalanced Bursty Traffic on Memory-Sharing Schemes for Internet Switching Architecture.	ICN (1)	2005	DBLP DOI BibTeX RDF	Unbalanced bursty Traffic, Memory-Sharing Schemes, Shared Memory, Packet Switch
18	Alessandro Bissacco	Modeling and Learning Contact Dynamics in Human Motion.	CVPR (1)	2005	DBLP DOI BibTeX RDF
18	Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin	Exploring technology alternatives for nano-scale FPGA interconnects.	DAC	2005	DBLP DOI BibTeX RDF	FPGA, interconnect, nanotechnology, nanoelectronics
18	Nagendra J. Kumar, Siddhartha Shivshankar, Alexander G. Dean	Asynchronous software thread integration for efficient software.	LCTES	2004	DBLP DOI BibTeX RDF	J1850, asynchronous software thread integration, software-implemented communication protocol controllers, hardware to software migration, fine-grain concurrency
18	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	FPGA	2004	DBLP DOI BibTeX RDF
18	Erland Nilsson, Johnny Öberg	Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS
18	Fei Li 0003, Yan Lin 0001, Lei He 0001	Vdd programmability to reduce FPGA interconnect power.	ICCAD	2004	DBLP DOI BibTeX RDF
18	Roman Bednarik, Markku Tukiainen	Visual attention tracking during program debugging.	NordiCHI	2004	DBLP DOI BibTeX RDF	visual attention, psychology of programming, eye-movement tracking
18	Kang Xi, Shin'ichi Arakawa, Masayuki Murata 0001	Virtual Fully Connected WDM Network: Architecture, Scheduling and Performance Evaluation.	BROADNETS	2004	DBLP DOI BibTeX RDF
18	Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch	Load Distribution with the Proximity Congestion Awareness in a Network on Chip.	DATE	2003	DBLP DOI BibTeX RDF
18	Pieter J. Mosterman	Hybrid dynamic systems: mode transition behavior in hybrid dynamic systems.	WSC	2003	DBLP DOI BibTeX RDF
18	Geir Horn, Olav Lysne, Tor Skeie	A Criterion for Cost Optimal Construction of Irregular Networks.	IPDPS	2003	DBLP DOI BibTeX RDF
18	Kei Eguchi, Hongbing Zhu, Fumio Ueno, Toru Tabata	Design of a step-up/step-down SC DC-DC converter with series-connected capacitors.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
18	Paul-Peter Sotiriadis	Information storage capacity of crossbar switching networks.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	nanotube, network, memory, capacity, information, storage, nanotechnology, switching, device, crossbar, nanowire
18	Kwang-Hyun Cho, Jong-Ho Cha, Olaf Wolkenhauer	How to Synthesize an Optimized Genetic-Switching System? A System-Theoretic Approach Based on SQP.	CMSB	2003	DBLP DOI BibTeX RDF
18	Pablo Molinero-Fernández, Nick McKeown	The performance of circuit switching in the internet.	Comput. Commun. Rev.	2002	DBLP DOI BibTeX RDF