Search results for "macros"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	George T. Dellert Jr.	A use of macros in translation of symbolic assembly language of one computer to another.	Commun. ACM	1965	DBLP DOI BibTeX RDF
11	Jerzy Tyszkiewicz	Spreadsheet as a relational database engine.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	performance, relational databases, sql, relational algebra, spreadsheets
11	Jason Cong, Guojie Luo	An analytical placer for mixed-size 3D placement.	ISPD	2010	DBLP DOI BibTeX RDF	placement, 3D integration, analytical method
11	Minsik Cho, Haoxing Ren, Hua Xiang 0001, Ruchir Puri	History-based VLSI legalization using network flow.	DAC	2010	DBLP DOI BibTeX RDF	VLSI, placement, network flow, legalization
11	Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun	Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.	DAC	2010	DBLP DOI BibTeX RDF	optimization, design space exploration, SRAM, virtual prototype, iterative design
11	Swapna R. Dontharaju, Shen Chih Tung, James T. Cain, Leonid Mats, Marlin H. Mickle, Alex K. Jones	A design automation and power estimation flow for RFID systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power, RFID, prototyping, design automation
11	Yoann Padioleau	Parsing C/C++ Code without Pre-processing.	CC	2009	DBLP DOI BibTeX RDF
11	Reinhard von Hanxleden	SyncCharts in C: a proposal for light-weight, deterministic concurrency.	EMSOFT	2009	DBLP DOI BibTeX RDF	SyncCharts, reactive processing, statecharts, multi-threading, model-based design, esterel, synchronous programming
11	Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich	The opportunity cost of low power design: a case study in circuit tuning.	ISLPED	2009	DBLP DOI BibTeX RDF	low power design, productivity, circuit tuning
11	Akif Sultan, John Faricelli, Sushant Suryagandh, Hans vanMeer, Kaveri Mathur, James Pattison, Sean Hannon, Greg Constant, Kalyana Kumar, Kevin Carrejo, Joe Meier, Rasit Onur Topaloglu, Darin Chan, Uwe Hahn, Thorsten Knopp, Victor Andrade, Bill Gardiol, Steve Hejl, David Wu, James Buller, Larry Bair, Ali Icel, Yuri Apanovich	CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design.	ISQED	2009	DBLP DOI BibTeX RDF
11	Yoann Padioleau, Lin Tan 0001, Yuanyuan Zhou 0001	Listening to programmers - Taxonomies and characteristics of comments in operating system code.	ICSE	2009	DBLP DOI BibTeX RDF
11	Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu	Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala	Efficient Analog/RF Layout Closure with Compaction Based Legalization.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Jackey Z. Yan, Natarajan Viswanathan, Chris Chu	Handling complexities in modern large-scale mixed-size placement.	DAC	2009	DBLP DOI BibTeX RDF	incremental placement, mixed-size design, floorplanning
11	Peter Novák 0001, Wojciech Jamroga	Code patterns for agent-oriented programming.	AAMAS (1)	2009	DBLP BibTeX RDF	ai, description level: methodologies and languages, focus: agent programming languages, inspiration source: robotics, temporal logic, agent-oriented programming, code patterns
11	Xiaofeng Wu 0001, Vassilios A. Chouliaras, José L. Núñez-Yáñez, Roger M. Goodall	A Novel Delta Sigma Control System Processor and Its VLSI Implementation.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Jason Cong, Guojie Luo, Eric Radke	Highly Efficient Gradient Computation for Density-Constrained Analytical Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Ulrich Brenner, Markus Struzyna, Jens Vygen	BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Michael Kohlhase	Using as a Semantic Markup Format.	Math. Comput. Sci.	2008	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000). 68U15
11	Philippe Lagadec	OpenDocument and Open XML security (OpenOffice.org and MS Office 2007).	J. Comput. Virol.	2008	DBLP DOI BibTeX RDF
11	Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll	ASIP-eFPGA Architecture for Multioperable GNSS Receivers.	SAMOS	2008	DBLP DOI BibTeX RDF	arithmetic oriented eFPGA, multioperable GNSS, ASIP
11	Jiun-Hung Chen, Daniel S. Weld	Recovering from errors during programming by demonstration.	IUI	2008	DBLP DOI BibTeX RDF
11	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Parallel fault backtracing for calculation of fault coverage.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	Adrian Dozsa, Tudor Gîrba, Radu Marinescu 0001	How Lisp Systems Look Different.	CSMR	2008	DBLP DOI BibTeX RDF
11	Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang	Constraint graph-based macro placement for modern mixed-size circuit designs.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Vamsi Boppana, Rahoul Varma, S. Balajee	Implementing the Best Processor Cores.	VLSI Design	2008	DBLP DOI BibTeX RDF
11	Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu	Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	superscalar pipeline, non-blocking cache, synthesis flow, bit-sliced placement, crafted cell, performance evaluation, physical design, out-of-order execution, general-purpose processor
11	Jarrod A. Roy, Igor L. Markov	ECO-System: Embracing the Change in Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	William Thies, Vikram Chandrasekhar, Saman P. Amarasinghe	A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs.	MICRO	2007	DBLP DOI BibTeX RDF
11	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs.	ETS	2007	DBLP DOI BibTeX RDF
11	Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Jarrod A. Roy, Igor L. Markov	ECO-system: Embracing the Change in Placement.	ASP-DAC	2007	DBLP DOI BibTeX RDF
11	Gregor Kiczales	Making the Code Look Like the Design - Aspects and Other Recent Work.	ICPC	2007	DBLP DOI BibTeX RDF
11	Stefan Raaijmakers, Stephan Wong	Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro.	FPL	2007	DBLP DOI BibTeX RDF
11	Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley	Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.	FPL	2007	DBLP DOI BibTeX RDF
11	Christian Brown, Chris McDonald	Visualizing berkeley socket calls in students' programs.	ITiCSE	2007	DBLP DOI BibTeX RDF	courseware, internetworking, systems programming
11	Tuan Hao Hoang, Robert I. McKay, Daryl Essam, Nguyen Xuan Hoai	Developmental Evaluation in Genetic Programming: A Position Paper.	FBIT	2007	DBLP DOI BibTeX RDF
11	Christelle Melo de Lima, Christian Gautier	A Markovian Approach for the Segmentation of Chimpanzee Genome.	BIRD	2007	DBLP DOI BibTeX RDF	isochore modelling, Hidden Markov model, DNA sequence
11	Simone Medardoni, Davide Bertozzi, Enrico Macii	Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	RTL synthesis, leakage-aware, power management, selection strategy
11	Christopher Scaffidi, Allen Cypher, Sebastian G. Elbaum, Andhy Koesnandar, Brad A. Myers	Scenario-Based Requirements for Web Macro Tools.	VL/HCC	2007	DBLP DOI BibTeX RDF
11	Gregg Rothermel	Helping End-User Programmers "Engineer" Software: an Opportunity for Empirical Researchers.	ESEM	2007	DBLP DOI BibTeX RDF
11	Kalyanmoy Deb, Shamik Chaudhuri	I-MODE: An Interactive Multi-objective Optimization and Decision-Making Using Evolutionary Methods.	EMO	2007	DBLP DOI BibTeX RDF
11	Ruben Gamboa, John R. Cowles	Implementing a cost-aware evaluator for ACL2 expressions.	ACL2	2006	DBLP DOI BibTeX RDF	ACL2 evaluator, function cost, evaluators
11	Bettina Berendt, Kai Dingel, Christoph Hanser	Intelligent Bibliography Creation and Markup for Authors: A Step Towards Interoperable Digital Libraries.	ECDL	2006	DBLP DOI BibTeX RDF
11	Alexey Ershov, Andrey Naraikin, Sergey Maidanov	Quad and correctly rounded double precision math functions: portable and optimized for Intel architectures.	SAC	2006	DBLP DOI BibTeX RDF	correct rounding, elementaly functions, quad precision, IEEE 754
11	Christian Buckl, Alois C. Knoll, Gerhard Schrott	Model-Based Development of Fault-Tolerant Embedded Software.	ISoLA	2006	DBLP DOI BibTeX RDF
11	Haakon Dybdahl, Marius Grannæs, Lasse Natvig	Cache Write-Back Schemes for Embedded Destructive-Read DRAM.	ARCS	2006	DBLP DOI BibTeX RDF
11	Jason Cong, Min Xie 0004	A robust detailed placement for mixed-size IC designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Matthew Flatt, Robert Bruce Findler, Matthias Felleisen	Scheme with Classes, Mixins, and Traits.	APLAS	2006	DBLP DOI BibTeX RDF
11	Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang	NTUplace2: a hybrid placer using partitioning and analytical techniques.	ISPD	2006	DBLP DOI BibTeX RDF	placement, physical design, legalization
11	Gi-Joon Nam	ISPD 2006 Placement Contest: Benchmark Suite and Results.	ISPD	2006	DBLP DOI BibTeX RDF
11	Maik Boden, Steffen Rülke, Jürgen Becker 0001	A high-level target-precise model for designing reconfigurable HW tasks.	IPDPS	2006	DBLP DOI BibTeX RDF
11	Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle	A Field Programmable RFID Tag and Associated Design Flow.	FCCM	2006	DBLP DOI BibTeX RDF
11	Daniel Ignatoff, Gregory H. Cooper, Shriram Krishnamurthi	Crossing State Lines: Adapting Object-Oriented Frameworks to Functional Reactive Languages.	FLOPS	2006	DBLP DOI BibTeX RDF
11	Jake J. Abbott, Allison M. Okamura	Pseudo-admittance Bilateral Telemanipulation with Guidance Virtual Fixtures.	HAPTICS	2006	DBLP DOI BibTeX RDF	virtual fixtures, virtual mechanisms, admittance control, rate control, teleoperation, force control, telemanipulation
11	Akashi Satoh	High-speed hardware architectures for authenticated encryption mode GCM.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Laurent Michel, Andrew See, Pascal Van Hentenryck	High-Level Nondeterministic Abstractions in.	CP	2006	DBLP DOI BibTeX RDF
11	Gabriella Dodero, Katia Lupi, Erika Piffero	Comparing macro development for personal productivity tools: an experience in validating accessibility of Talking Books. (PDF / PS)	OSS	2006	DBLP DOI BibTeX RDF
11	Richard Carlsson, Mickaël Rémond	EUnit: a lightweight unit testing framework for Erlang.	Erlang Workshop	2006	DBLP DOI BibTeX RDF	frameworks, unit testing, Erlang, agile methods
11	Matthew Jacobs, E. Christopher Lewis	SMART C: A Semantic Macro Replacement Translator for C.	SCAM	2006	DBLP DOI BibTeX RDF
11	Bin Yao, William Mielke, Steve Kennedy, Rick Buskens	C Macro Handling in Automated Source Code Transformation Systems.	ICSM	2006	DBLP DOI BibTeX RDF
11	Uwe Aßmann, Jendrik Johannes, Jakob Henriksson, Ilie Savga	Composition of Rule Sets and Ontologies.	Reasoning Web	2006	DBLP DOI BibTeX RDF
11	Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle	An automated, reconfigurable, low-power RFID tag.	DAC	2006	DBLP DOI BibTeX RDF
11	Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara	Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	11 fan-out of four, 11FO4, Synergistic Processor Element, private memory, streaming processing, Cell processor, multimedia processing, scratch pad memory
11	Weiwu Hu, Fuxin Zhang, Zusong Li	Microarchitecture of the Godson-2 Processor.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming
11	Hisashige Ando, Nestoras Tzartzanis, William W. Walker	A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Howard Chen 0001, Louis Hsu	Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System.	PATMOS	2005	DBLP DOI BibTeX RDF
11	Jurjen Westra, Patrick Groeneveld	Towards Integration of Quadratic Placement and Pin Assignment.	ISVLSI	2005	DBLP DOI BibTeX RDF
11	Daniel Thull, Roberto Sannino	Performance Considerations for an Embedded Implementation of OMA DRM 2.	DATE	2005	DBLP DOI BibTeX RDF
11	Naoyuki Tamura	Calc/Cream: OpenOffice Spreadsheet Front-End for Constraint Programming.	INAP	2005	DBLP DOI BibTeX RDF
11	Ben Salzberg, Trevor M. Murphy	LaTeX: when word fails you.	SIGUCCS	2005	DBLP DOI BibTeX RDF	word processing, LaTeX, typesetting, TeX
11	Michael Hübner 0001, Katarina Paulsson, Jürgen Becker 0001	Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.	IPDPS	2005	DBLP DOI BibTeX RDF
11	Andres Upegui, Eduardo Sanchez	Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs.	ICES	2005	DBLP DOI BibTeX RDF
11	Ryan Culpepper, Scott Owens, Matthew Flatt	Syntactic Abstraction in Component Interfaces.	GPCE	2005	DBLP DOI BibTeX RDF
11	Aishwarya Dubey	P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop.	ISQED	2005	DBLP DOI BibTeX RDF	P/G (Power/Ground) pad placement, current sink, package resistance, package inductance, IR drop
11	Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen	A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	ASIP-application specific instruction set processor, low power, multiprocessor, heterogeneous, scalable architecture, audio signal processing
11	Srinivasan Murali, Giovanni De Micheli	Bandwidth-Constrained Mapping of Cores onto NoC Architectures.	DATE	2004	DBLP DOI BibTeX RDF	routing, Systems on Chips, mapping, Networks on Chips, bandwidth, cores
11	Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli	×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.	DATE	2004	DBLP DOI BibTeX RDF	Systems on Chips, Networks on Chips, SystemC, application-specific, latency-insensitive design
11	Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai	A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications.	DATE	2004	DBLP DOI BibTeX RDF
11	Jeremy J. Carroll, Patrick Stickler	RDF triples in XML.	WWW (Alternate Track Papers & Posters)	2004	DBLP DOI BibTeX RDF	XML, semantic web, RDF
11	Xiaoping Tang, Martin D. F. Wong	Tradeoff routing resource, runtime and quality in buffered routing.	ASP-DAC	2004	DBLP DOI BibTeX RDF
11	James Laird	A Calculus of Coroutines.	ICALP	2004	DBLP DOI BibTeX RDF
11	Mario Latendresse	Rewrite Systems for Symbolic Evaluation of C-like Preprocessing.	CSMR	2004	DBLP DOI BibTeX RDF
11	Enrico Macii	RTL power estimation and optimization.	SBCCI	2004	DBLP DOI BibTeX RDF
11	Adronis Niyonkuru, Hans Christoph Zeidler	Designing a Runtime Reconfigurable Processor for General Purpose Applications.	IPDPS	2004	DBLP DOI BibTeX RDF
11	István Zólyomi, Zoltán Porkoláb	Towards a General Template Introspection Library.	GPCE	2004	DBLP DOI BibTeX RDF
11	Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz	Experimental measurement of a novel power gating structure with intermediate power saving mode.	ISLPED	2004	DBLP DOI BibTeX RDF	system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
11	Michael Toomim, Andrew Begel, Susan L. Graham	Managing Duplicated Code with Linked Editing.	VL/HCC	2004	DBLP DOI BibTeX RDF
11	Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda	A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification.	ISQED	2004	DBLP DOI BibTeX RDF
11	Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu	34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System.	ITC	2004	DBLP DOI BibTeX RDF
11	Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi	Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI.	ITC	2004	DBLP DOI BibTeX RDF
11	Rajiv V. Joshi, K. Kroell, Ching-Te Chuang	A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI.	VLSI Design	2004	DBLP DOI BibTeX RDF
11	Srinivasan Murali, Giovanni De Micheli	SUNMAP: a tool for automatic topology selection and generation for NoCs.	DAC	2004	DBLP DOI BibTeX RDF	systems on chip, mapping, networks on chip, topology, SystemC
11	Kevin W. McCullen	Phase correct routing for alternating phase shift masks.	DAC	2004	DBLP DOI BibTeX RDF	resolution enhancement techniques (RET), routing, layout, lithography
11	Kyung-Saeng Kim, Kwyro Lee	Low-power and area-efficient FIR filter implementation suitable for multiple taps.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
11	Diomidis Spinellis	Global Analysis and Transformations in Preprocessed Languages.	IEEE Trans. Software Eng.	2003	DBLP DOI BibTeX RDF	reverse engineering, C++, C, Refactoring, renaming, preprocessor, program families
11	Eric Baelen	Using Excel as a front end to APL+Win.	ACM SIGAPL APL Quote Quad	2003	DBLP DOI BibTeX RDF
11	Olav Beckmann, Alastair Houghton, Michael R. Mellor, Paul H. J. Kelly	Runtime Code Generation in C++ as a Foundation for Domain-Specific Optimisation.	Domain-Specific Program Generation	2003	DBLP DOI BibTeX RDF
11	Eric E. Allen, Jonathan Bannet, Robert Cartwright	A first-class approach to genericity.	OOPSLA	2003	DBLP DOI BibTeX RDF
11	Wonjoon Choi, Kia Bazargan	Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration.	DATE	2003	DBLP DOI BibTeX RDF	floorplacement, global placement, area migration, Design, Algorithms, simulated annealing, Management, Floorplanning, network flow, hierarchical, Placement and routing