Search results for "roadmap"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Michael Eisenring, Marco Platzner	Optimization of Run-Time Reconfigurable Embedded Systems.	FPL	2000	DBLP DOI BibTeX RDF
13	Tom Kean	It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures.	FPL	2000	DBLP DOI BibTeX RDF
13	Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima	A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology.	FPL	2000	DBLP DOI BibTeX RDF
13	Uwe Hatnik, Jürgen Haufe, Peter Schwarz	An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware.	FPL	2000	DBLP DOI BibTeX RDF
13	Selene Maya, M. Rocio Reynoso, César Torres-Huitzil, Miguel O. Arias-Estrada	Compact Spiking Neural Network Implementation in FPGA.	FPL	2000	DBLP DOI BibTeX RDF
13	A. Hilton, J. Hall	On Applying Software Development Best Practice to FPFAs in Safety Critical Systems.	FPL	2000	DBLP DOI BibTeX RDF
13	Mark Redekopp, Andreas Dandalis	A Parallel Pipelined SAT Solver for FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann 0001, Ulrich Nageldinger	Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.	FPL	2000	DBLP DOI BibTeX RDF
13	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	Multiple-Wordlength Resource Binding.	FPL	2000	DBLP DOI BibTeX RDF
13	Tsugio Makimoto	The Rising Wave of Field Programmability.	FPL	2000	DBLP DOI BibTeX RDF
13	Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk	A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems.	FPL	2000	DBLP DOI BibTeX RDF
13	Darko Stefanovic, Margaret Martonosi	On Availability of Bit-Narrow Operations in General-Purpose Applications.	FPL	2000	DBLP DOI BibTeX RDF
13	Frank-Michael Renner, Jürgen Becker 0001, Manfred Glesner	Field Programmable Communication Emulation and Optimization for Embedded System Design.	FPL	2000	DBLP DOI BibTeX RDF	architecture-precise rapid prototyping, field programmable emulation, Hardware/software codesign, real-time embedded systems
13	Bogdan Matasaru, Tudor Jebelean	FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers.	FPL	2000	DBLP DOI BibTeX RDF
13	Christophe Bobda, Thomas Lehmann 0001	Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction.	FPL	2000	DBLP DOI BibTeX RDF
13	Rob McCready	Real-Time Face Detection on a Configurable Hardware System.	FPL	2000	DBLP DOI BibTeX RDF
13	Hamish Fallside, Michael John Sebastian Smith	Internet Connected FPL.	FPL	2000	DBLP DOI BibTeX RDF
13	Joerg Abke, Erich Barke	CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Juanjo Noguera, Rosa M. Badia	Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers.	FPL	2000	DBLP DOI BibTeX RDF
13	Stephen J. Melnikoff, Philip James-Roxby, Steven F. Quigley, Martin J. Russell	Reconfigurable Computing for Speech Recognition: Preliminary Findings.	FPL	2000	DBLP DOI BibTeX RDF
13	Hideharu Amano, Yuichiro Shibata, Masaki Uno	Reconfigurable Systems: New Activities in Asia.	FPL	2000	DBLP DOI BibTeX RDF
13	G. Lías, María Dolores Valdés, Miguel A. Domínguez, María José Moure	Implementing a Fieldbus Interface Using an FPGA.	FPL	2000	DBLP DOI BibTeX RDF
13	Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada	An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture.	FPL	2000	DBLP DOI BibTeX RDF
13	Christian Siemers	Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling.	FPL	2000	DBLP DOI BibTeX RDF
13	Brandon Blodget	Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration.	FPL	2000	DBLP DOI BibTeX RDF
13	Jihan Zhu, George J. Milne	Implementing Kak Neural Networks on a Reconfigurable Computing Platform.	FPL	2000	DBLP DOI BibTeX RDF
13	Javier Ramírez 0001, Antonio García 0001, Pedro G. Fernández, Luis Parrilla 0001, Antonio Lloris-Ruíz	Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.	FPL	2000	DBLP DOI BibTeX RDF
13	Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn	StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox.	FPL	2000	DBLP DOI BibTeX RDF
13	Valery Sklyarov	Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	John Marty Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici	Performance Penalty for Fault Tolerance in Roving STARs.	FPL	2000	DBLP DOI BibTeX RDF	Adaptive Computing System, Fault Tolerance, FPGA
13	Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh	FPGA Implementation of a Prototype WDM On-Line Scheduler.	FPL	2000	DBLP DOI BibTeX RDF
13	Sriram Govindarajan, Ranga Vemuri	Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS.	FPL	2000	DBLP DOI BibTeX RDF
13	Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi	Evaluation of Accelerator Designs for Subgraph Isomorphism Problem.	FPL	2000	DBLP DOI BibTeX RDF
13	Bernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van Meerbergen	Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis.	FPL	2000	DBLP DOI BibTeX RDF
13	Pawel Tomaszewicz	Self-Testing of Linear Segments in User-Programmed FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Alfred Blaickner, O. Nagy, Herbert Grünbacher	Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic.	FPL	2000	DBLP DOI BibTeX RDF	digital receiver, FPGA, synchronization, Wireless, hardware/software co-design, software radio
13	Jim Tørresen	Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications.	FPL	2000	DBLP DOI BibTeX RDF
13	Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna	A Self-Reconfigurable Gate Array Architecture.	FPL	2000	DBLP DOI BibTeX RDF
13	Helena Krupnova, Gabriele Saucier	FPGA-Based Emulation: Industrial and Custom Prototyping Solutions.	FPL	2000	DBLP DOI BibTeX RDF
13	Tero Rissa, Jarkko Niittylahti	A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs.	FPL	2000	DBLP DOI BibTeX RDF
13	Thomas Bartzick, Michael Henze, Jens Kickler, Kai Woska	Design of a Fault Tolerant FPGA.	FPL	2000	DBLP DOI BibTeX RDF
13	Jörn Gause, Peter Y. K. Cheung, Wayne Luk	Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT.	FPL	2000	DBLP DOI BibTeX RDF
13	André Brinkmann, Dominik Langen, Ulrich Rückert 0001	A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor.	FPL	2000	DBLP DOI BibTeX RDF
13	Stephen J. Bellis, William P. Marnane	A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System.	FPL	2000	DBLP DOI BibTeX RDF
13	Oliver Diessel, George J. Milne	Behavioural Language Compilation with Virtual Hardware Management.	FPL	2000	DBLP DOI BibTeX RDF
13	Chris Phillips	Wireless Base Station Design Using a Reconfigurable Communications Processor.	FPL	2000	DBLP DOI BibTeX RDF
13	David Robinson, Patrick Lysaght	Verification of Dynamically Reconfigurable Logic.	FPL	2000	DBLP DOI BibTeX RDF
13	Andrej Trost, Andrej Zemva, Baldomir Zajc	Educational Programmable Hardware Prototyping and Verification System.	FPL	2000	DBLP DOI BibTeX RDF
13	Johan Ditmar, Kjell Torkelsson, Axel Jantsch	A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization.	FPL	2000	DBLP DOI BibTeX RDF
13	E. Cantó, Juan Manuel Moreno, Joan Cabestany, Ignacio Lacadena, Josep Maria Insenser	Implementation of Virtual Circuits by Means of the FIPSOC Devices.	FPL	2000	DBLP DOI BibTeX RDF
13	Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier	Area-Optimized Technology Mapping for Hybrid FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Jan M. Rabaey	Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?	FPL	2000	DBLP DOI BibTeX RDF
13	Andrzej Krasniewski	Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Guy Lecurieux Lafayette	Programmable System Level Integration Brings System-on-Chip Design to the Desktop.	FPL	2000	DBLP DOI BibTeX RDF
13	Andreas C. Döring, Gunther Lustig	Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory.	FPL	2000	DBLP DOI BibTeX RDF
13	Radhika S. Grover, Weijia Shang, Qiang Li	A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers.	FPL	2000	DBLP DOI BibTeX RDF
13	Rolf Hoffmann, Bernd Ulmann, Klaus-Peter Völkmann, Stefan Waldschmidt	A Stream Processor Architecture Based on the Configurable CEPRA-S.	FPL	2000	DBLP DOI BibTeX RDF
13	Michel Renovell	A Specific Test Methodology for Symmetric SRAM-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano	A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.	FPL	2000	DBLP DOI BibTeX RDF
13	Jens Hildebrandt, Dirk Timmermann	An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems.	FPL	2000	DBLP DOI BibTeX RDF
13	Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman	A Placement Algorithm for FPGA Designs with Multiple I/O Standards.	FPL	2000	DBLP DOI BibTeX RDF
13	Christine Bauer 0002, Peter Zipf, Hans Wojtkowiak	System Design with Genetic Algorithms.	FPL	2000	DBLP DOI BibTeX RDF
13	Abdellah Touhafi	A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller.	FPL	2000	DBLP DOI BibTeX RDF
13	Marios Iliopoulos, Theodore Antonakopoulos 0001	Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits.	FPL	2000	DBLP DOI BibTeX RDF
13	Jean-Michel Raczinski, Stéphane Sladek	The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing.	FPL	2000	DBLP DOI BibTeX RDF
13	Milan Vasilko, Graham Benyon-Tinker	Automatic Temporal Floorplanning with Guaranteed Solution Feasibility.	FPL	2000	DBLP DOI BibTeX RDF
13	Petr Pfeifer	Multifunctional Programmable Single-Board CAN Monitoring Module.	FPL	2000	DBLP DOI BibTeX RDF	Student Papers, FPL2000, programmable device, ALTERA, FLEX6000, EPF6016, SJA1000, PC/104, CAN
13	Alexander Glasmacher, Kai Woska	Design and Implementation of an XC6216 FPGA Model in Verilog.	FPL	2000	DBLP DOI BibTeX RDF
13	Jernej Andrejas, Andrej Trost	Reusable DSP Functions in FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Hagen Ploog, Mathias Schmalisch, Dirk Timmermann	Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic.	FPL	2000	DBLP DOI BibTeX RDF
13	Holger Kropp, Carsten Reuter	A Mapping Methodology for Code Trees onto LUT-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	Milan Vasilko	Design Visualisation for Dynamically Reconfigurable Systems.	FPL	2000	DBLP DOI BibTeX RDF
13	Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube	Formal Verification of a Reconfigurable Microprocessor.	FPL	2000	DBLP DOI BibTeX RDF
13	Donald Cottrell	Design Automation Technology Roadmap.	The VLSI Handbook	1999	DBLP DOI BibTeX RDF
13	Juan Manuel Ahuactzin, Kamal K. Gupta	The kinematic roadmap: a motion planning based global approach for inverse kinematics of redundant robots.	IEEE Trans. Robotics Autom.	1999	DBLP DOI BibTeX RDF
13	Kwan-Liu Ma, Frits H. Post	Guest Editors' Introduction: Visualization Case Studies-Drawing a Roadmap for Future Visualization.	IEEE Computer Graphics and Applications	1999	DBLP DOI BibTeX RDF
13	S. Sathiya Keerthi, Chong Jin Ong, Eugene Huang, Elmer G. Gilbert	EquiDistance Diagram: A New Roadmap Method for Path Planning.	ICRA	1999	DBLP DOI BibTeX RDF
13	Steven M. LaValle, Jeffery H. Yakey, Lydia E. Kavraki	A Probabilistic Roadmap Approach for Systems with Closed Kinematic Chains.	ICRA	1999	DBLP DOI BibTeX RDF
13	Nancy M. Amato, Lucia K. Dale	Probabilistic Roadmap Methods are Embarrassingly Parallel.	ICRA	1999	DBLP DOI BibTeX RDF
13	Valérie Boor, Mark H. Overmars, A. Frank van der Stappen	The Gaussian Sampling Strategy for Probabilistic Roadmap Planners.	ICRA	1999	DBLP DOI BibTeX RDF
13	Steven A. Wilmarth, Nancy M. Amato, Peter F. Stiller	MAPRM: A Probabilistic Roadmap Planner with Sampling on the Medial Axis of the Free Space.	ICRA	1999	DBLP DOI BibTeX RDF
13	Leonidas J. Guibas, Christopher Holleman, Lydia E. Kavraki	A probabilistic roadmap planner for flexible objects with a workspace medial-axis-based sampling approach.	IROS	1999	DBLP DOI BibTeX RDF
13	Pier Luca Lanzi, Rick L. Riolo	A Roadmap to the Last Decade of Learning Classifier System Research.	Learning Classifier Systems	1999	DBLP DOI BibTeX RDF
13	Nicholas R. Jennings, Katia P. Sycara, Michael J. Wooldridge	A Roadmap of Agent Research and Development.	Auton. Agents Multi Agent Syst.	1998	DBLP DOI BibTeX RDF
13	Michael Christoffel, Sebastian Pulkowski, Bethina Schmitt, Peter C. Lockemann	Electronic Market: The Roadmap for University Libraries and Members to Survive in the Information Jungle.	SIGMOD Rec.	1998	DBLP DOI BibTeX RDF
13	Ronald N. Kostoff, Henry J. Eberhart, Darrell Ray Toothman	Database Tomography for Technical Intelligence: A Roadmap of the Near-Earth Space Science and Technology Literature.	Inf. Process. Manag.	1998	DBLP DOI BibTeX RDF
13	Rodney Thayer, Naganand Doraswamy, Rob Glenn	IP Security Document Roadmap.	RFC	1998	DBLP DOI BibTeX RDF
13	Nancy M. Amato, O. Burçhan Bayazit, Lucia K. Dale, Christopher Jones, Daniel Vallejo	Choosing Good Distance Metrics and Local Planners for Probabilistic Roadmap Methods.	ICRA	1998	DBLP DOI BibTeX RDF
13	Yong Yu 0005, Kamal Gupta 0001	On sensor-based roadmap: a framework for motion planning for a manipulator arm in unknown environments.	IROS	1998	DBLP DOI BibTeX RDF
13	William R. Ortner	How real is the new SIA roadmap for mixed-signal test equipment?	ITC	1998	DBLP DOI BibTeX RDF
13	Phil Nigh	SIA Roadmap: test must not limit future technologies.	ITC	1998	DBLP DOI BibTeX RDF
13	Wayne M. Needham	Just how real is the SIA roadmap.	ITC	1998	DBLP DOI BibTeX RDF
13	Alistair McLean	Update and repair of a roadmap after model error discovery.	Robotics Auton. Syst.	1997	DBLP DOI BibTeX RDF
13	Charles R. Merrill	An Attorney's Roadmap to the Digital Signature Guidelines.	Financial Cryptography	1997	DBLP DOI BibTeX RDF
13	Juan Manuel Ahuactzin, Kamal Gupta 0001	A motion planning based approach for inverse kinematics of redundant robots: the kinematic roadmap.	ICRA	1997	DBLP DOI BibTeX RDF
13	Louis Scheffer	A roadmap of CAD tool changes for sub-micron interconnect problems.	ISPD	1997	DBLP DOI BibTeX RDF
13	Glenn Warnock, Douglas Reid, Maike Miller	Roadmap to ATM.	WebNet	1997	DBLP BibTeX RDF
13	Didier Dubois, Luis Fariñas del Cerro, Andreas Herzig, Henri Prade	Qualitative Relevance and Independence: A Roadmap.	IJCAI (1)	1997	DBLP BibTeX RDF
13	Robert Glück, Morten Heine Sørensen	A Roadmap to Metacomputation by Supercompilation.	Dagstuhl Seminar on Partial Evaluation	1996	DBLP DOI BibTeX RDF
13	Nancy M. Amato, Yan Wu	A randomized roadmap method for path and manipulation planning.	ICRA	1996	DBLP DOI BibTeX RDF