Search results for "methodology"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Choon Seong Leem, Nam Joo Jeon, Jong Hwa Choi, Hyoun Gyu Shin	A Business Model (BM) Development Methodology in Ubiquitous Computing Environments.	ICCSA (4)	2005	DBLP DOI BibTeX RDF
13	Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen	On A Software-Based Self-Test Methodology and Its Application.	VTS	2005	DBLP DOI BibTeX RDF
13	Anna E. Bobkowska	A Methodology of Visual Modeling Language Evaluation.	SOFSEM	2005	DBLP DOI BibTeX RDF
13	V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi	Design methodology for IC manufacturability based on regular logic-bricks.	DAC	2005	DBLP DOI BibTeX RDF	regularity, manufacturability, integrated circuits, RET
13	Brian Marick	Methodology work is ontology work.	ACM SIGPLAN Notices	2004	DBLP DOI BibTeX RDF
13	Eva González-Parada, José Manuel Cano-García, Antonio Díaz Estrella	A new methodology for representation of TCP performance in multiconnection environments.	Comput. Commun. Rev.	2004	DBLP DOI BibTeX RDF
13	Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.	SAMOS	2004	DBLP DOI BibTeX RDF
13	Anastasius Gavras, Mariano Belaunde, Luís Ferreira Pires, João Paulo A. Almeida	Towards an MDA-Based Development Methodology.	EWSA	2004	DBLP DOI BibTeX RDF
13	Konstantinos Kotis, George A. Vouros, Jerónimo Padilla Alonso	HCOME: A Tool-Supported Methodology for Engineering Living Ontologies.	SWDB	2004	DBLP DOI BibTeX RDF
13	Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi	An Interconnect Channel Design Methodology for High Performance Integrated Circuits.	DATE	2004	DBLP DOI BibTeX RDF
13	Ibrahim M. Elfadel, Alina Deutsch, Gerard V. Kopcsay, Bradley Rubin, Howard H. Smith	A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses.	DATE	2004	DBLP DOI BibTeX RDF
13	Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori	Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis.	DATE	2004	DBLP DOI BibTeX RDF
13	Nico Bannow, Karsten Haug	Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications.	DATE	2004	DBLP DOI BibTeX RDF
13	Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl	A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.	DATE	2004	DBLP DOI BibTeX RDF
13	Daniel Karlsson, Petru Eles, Zebo Peng	A Formal Verification Methodology for IP-based Designs.	DSD	2004	DBLP DOI BibTeX RDF
13	Giuseppe De Nicola, Pasquale di Tommaso, Rosaria Esposito, Francesco Flammini, Antonio Orazzo	A Hybrid Testing Methodology for Railway Control Systems.	SAFECOMP	2004	DBLP DOI BibTeX RDF
13	Noriyuki Miura, Naoki Kato, Tadahiro Kuroda	Practical methodology of post-layout gate sizing for 15% more power saving.	ASP-DAC	2004	DBLP DOI BibTeX RDF
13	Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang	A Low-Cost Diagnosis Methodology for Pipelined A/D Converters.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
13	Jawad Khan, Ranga Vemuri	An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms.	FPL	2004	DBLP DOI BibTeX RDF
13	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	A Structured Methodology for System-on-an-FPGA Design.	FPL	2004	DBLP DOI BibTeX RDF
13	Jingzhao Ou, Viktor K. Prasanna	A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms.	FPL	2004	DBLP DOI BibTeX RDF
13	Frank Hannig, Hritam Dutta, Jürgen Teich	Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology.	IPDPS	2004	DBLP DOI BibTeX RDF
13	Zachary K. Baker, Viktor K. Prasanna	A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
13	María Engracia Gómez, José Flich, Pedro López 0001, Antonio Robles, José Duato, Nils Agne Nordbotten, Olav Lysne, Tor Skeie	An Effective Fault-Tolerant Routing Methodology for Direct Networks.	ICPP	2004	DBLP DOI BibTeX RDF
13	Voravud Santiraveewan, Yongyuth Permpoontanalarp	A Graph-based Methodology for Analyzing IP Spoofing Attack.	AINA (2)	2004	DBLP DOI BibTeX RDF	IP spoofing and Formal Method for Network Security, Network Security, Firewalls
13	Trung H. Bui, Martin Rajman, Miroslav Melichar	Rapid Dialogue Prototyping Methodology.	TSD	2004	DBLP DOI BibTeX RDF
13	Ioannis A. Vetsikas, Bart Selman	A Methodology and Equilibria for the Design Tradeoffs of Autonomous Trading Agents.	AAMAS	2004	DBLP DOI BibTeX RDF
13	Francis Eng Hock Tay, Jinxiang Gu	A methodology for evolutionary product design.	Eng. Comput.	2003	DBLP DOI BibTeX RDF	Function-form mapping, Product Information management, Function, Evolutionary design, Product family, Form
13	Cesare Alippi, Andrea Galbusera, Marco Stellini	An application-level synthesis methodology for multidimensional embedded processing systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
13	Yonghee Im, Kaushik Roy 0001	LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits.	ISVLSI	2003	DBLP DOI BibTeX RDF
13	Osvaldo Cairó, Julio César Alvarez	The KAMET II Methodology: A Modern Approach for Building Diagnosis-Specialized Knowledge-Based Systems.	ISMIS	2003	DBLP DOI BibTeX RDF
13	François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat	A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL.	FPGA	2003	DBLP DOI BibTeX RDF	AES RIJNDAEL, high encryption rates, FPGA, cryptography, reconfigurable hardware
13	Wai Hong Ho, Timothy Mark Pinkston	A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns.	HPCA	2003	DBLP DOI BibTeX RDF	Low-Contention Communication, Network Partitioning, Communication Model, On-chip Interconnects, Irregular Topology
13	Andrew Burton-Jones, Veda C. Storey, Vijayan Sugumaran, Sandeep Purao	A Heuristic-Based Methodology for Semantic Augmentation of User Queries on the Web.	ER	2003	DBLP DOI BibTeX RDF
13	Junho Shim, Seungjin Lee 0002, Chisu Wu	A Unified Approach for Software Policy Modeling: Incorporating Implementation into a Modeling Methodology.	ER	2003	DBLP DOI BibTeX RDF
13	Mário P. Véstias, Horácio C. Neto	DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures.	SBCCI	2003	DBLP DOI BibTeX RDF
13	Yiausyu Earl Tsai, Hewijin Christine Jiau, Kuo-Feng Ssu	Scenario Architecture - A Methodology to Build a Global View of OO Software System.	COMPSAC	2003	DBLP DOI BibTeX RDF
13	Dickson K. W. Chiu, Shing-Chi Cheung, Ho-fung Leung	A Three-Tier View-Based Methodology for Adapting Human-Agent Collaboration Systems.	CAiSE	2003	DBLP DOI BibTeX RDF
13	Flor A. Castillo, Ken A. Marshall, James L. Green, Arthur K. Kordon	A Methodology for Combining Symbolic Regression and Design of Experiments to Improve Empirical Model Building.	GECCO	2003	DBLP DOI BibTeX RDF
13	José María Gomis, Margarita Valor, Francisco Albert, Manuel Contero	Intregated System and Methodology for Supporting Textile and Tile Pattern Design.	Smart Graphics	2003	DBLP DOI BibTeX RDF
13	Ludovic Tambour, Nacer-Eddine Zergainoh, Pascal Urard, Henri Michel, Ahmed Amine Jerraya	An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
13	Mun-Young Choi, JongSeon Lim, Kyung-Soo Joo	Developing a Unified Design Methodology Based on Extended Entity-Relationship Model for XML.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
13	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
13	Yonghee Im, Kaushik Roy 0001	A logic-aware layout methodology to enhance the noise immunity of domino circuits.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
13	Eric Sanchis	Designing new Agent Based Applications Architectures with the AGP Methodology.	WETICE	2003	DBLP DOI BibTeX RDF
13	Azeddien M. Sllame	Design Space Exploration Methodology for High-Performance System-on-a-Chip Hardware Cores.	IWSOC	2003	DBLP DOI BibTeX RDF
13	David Goren, Michael Zelikson, Rachel Gordin, Israel A. Wagner, Anastasia Barger, Alon Amir, Betty Livshitz, Anatoly Sherman, Youri Tretiakov, Robert A. Groves, J. Park, Donald L. Jordan, Sue E. Strang, Raminderpal Singh, Carl E. Dickey, David L. Harame	On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices.	DAC	2003	DBLP DOI BibTeX RDF	modeling, interconnect, vlsi
13	Sabyasachi Das, Sunil P. Khatri	An efficient and regular routing methodology for datapath designsusing net regularity extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
13	Clement T. Yu, King-Lup Liu, Weiyi Meng, Zonghuan Wu, Naphtali Rishe	A Methodology to Retrieve Text Documents from Multiple Databases.	IEEE Trans. Knowl. Data Eng.	2002	DBLP DOI BibTeX RDF	resource discovery, Distributed information retrieval, metasearch, database selection
13	Hitoshi Nagasaki, Motoei Azuma	A Methodology for Assessing User's Skill Grade to Implement Adaptive User Interface Systems.	IEEE ICCI	2002	DBLP DOI BibTeX RDF
13	Vijay Murthi, David Levine, Behrooz A. Shirazi, Jeff Marquis	A Tool Based Methodology for Development of Automatically Scalable and Reusable Parallel Code.	MASCOTS	2002	DBLP DOI BibTeX RDF
13	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Effective Software Self-Test Methodology for Processor Cores.	DATE	2002	DBLP DOI BibTeX RDF
13	Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda, Ralf Seepold, Natividad Martínez Madrid	A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects.	DATE	2002	DBLP DOI BibTeX RDF
13	Chanwit Kaewkasi, Wanchai Rivepiboon	WWM: A Practical Methodology for Web Application Modeling.	COMPSAC	2002	DBLP DOI BibTeX RDF
13	Dick Mays, Richard J. LeBlanc	The cyclefree methodology: a simple approach to building reliable, robust, real-time systems.	ICSE	2002	DBLP DOI BibTeX RDF
13	Tom L. Roberts Jr., Michael L. Gibson, R. Kelly Rainer Jr., Kent T. Fields	Response to 'Comments on Factors that Impact the Implementation of a Systems Development Methodology'.	IEEE Trans. Software Eng.	2001	DBLP DOI BibTeX RDF
13	Vincenzo Galdi, Lucio Ippolito, Antonio Piccolo, Alfredo Vaccaro	A genetic-based methodology for hybrid electric vehicles sizing.	Soft Comput.	2001	DBLP DOI BibTeX RDF	Hybrid electric vehicles, Powertrain sizing, Genetic optimisation, Genetic algorithms
13	Huo Yan Chen, T. H. Tse, Tsong Yueh Chen	TACCLE: a methodology for object-oriented software testing at the class and cluster levels.	ACM Trans. Softw. Eng. Methodol.	2001	DBLP DOI BibTeX RDF	contact specifications, software testing, object-oriented programming, message passing, algebraic specifications
13	Paolo Atzeni, Paolo Merialdo, Giuseppe Sindoni	Web Site Evaluation: Methodology and Case Study.	ER (Workshops)	2001	DBLP DOI BibTeX RDF
13	Gregor Engels, Jochen Malte Küster, Reiko Heckel, Luuk Groenewegen	A methodology for specifying and analyzing consistency of object-oriented behavioral models.	ESEC / SIGSOFT FSE	2001	DBLP DOI BibTeX RDF	behavioral consistency, UML, UML, CSP, object-oriented modeling
13	Milan Vasilko, Lukas Machácek, Marek Matej, Piotr Stepien, Steve Holloway	A Rapid Prototyping Methodology and Platform for Seamless Communication Systems.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
13	Nuno F. Paulino, João Goes, Adolfo Steiger-Garção	Design methodology for optimization of analog building blocks using genetic algorithms.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
13	Sultan M. Al-Harbi, Sandeep K. Gupta 0001	An Efficient Methodology for Generating Optimal and Uniform March Tests.	VTS	2001	DBLP DOI BibTeX RDF
13	Min-Hsuan Fan, Chua-Huang Huang, Yeh-Ching Chung, Jen-Shiuh Liu, Jei-Zhii Lee	A Programming Methodology for Designing Parallel Prefix Algorithms.	ICPP	2001	DBLP DOI BibTeX RDF
13	Yongyuth Permpoontanalarp, Chaiwat Rujimethabhas	A Unified Methodology for Verification and Synthesis of Firewall Configurations.	ICICS	2001	DBLP DOI BibTeX RDF
13	Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil	Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	supply current test, I DD, I DDX monitor, analog test, structural test, mixed-signal test, current monitor
13	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	A Buffer-Oriented Methodology for Microarchitecture Validation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	processor validation, superscalar microarchitecture, design validation
13	Giovanna Di Marzo Serugendo	A Formal Development and Validation Methodology Applied to Agent-Based Systems.	Agents Workshop on Infrastructure for Multi-Agent Systems	2000	DBLP DOI BibTeX RDF
13	José Carlos Sancho, Antonio Robles, José Duato	A New Methodology to Computer Deadlock-Free Routing Tables for Irregular Networks.	CANPC	2000	DBLP DOI BibTeX RDF
13	Yin-Chao Huang, Chung-Len Lee 0001, Jun-Weir Lin, Jwu E. Chen, Chauchin Su	A methodology for fault model development for hierarchical linear systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	closed loop systems, hierarchical linear systems, transfer function model, open-loop, element faults, benchmark state-variable filter, AC fault model, state variable filter, fault diagnosis, fault model, fault simulation, modules, Monte Carlo methods, Monte Carlo simulation, transfer functions, computation time, operational amplifiers, operational amplifiers, closed loop, analogue circuits
13	Michel Renovell	A Specific Test Methodology for Symmetric SRAM-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
13	H. Gonda Neddermeijer, Gerrit J. van Oortmarssen, Nanda Piersma, Rommert Dekker	A framework for Response Surface Methodology for simulation optimization.	WSC	2000	DBLP DOI BibTeX RDF
13	Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim	Genetic Algorithm-Based Methodology for Pattern Recognition Hardware.	ICES	2000	DBLP DOI BibTeX RDF
13	Michael Cogswell, Don Pearl, James Sage, Alan Troidl	An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design.	ICCD	2000	DBLP DOI BibTeX RDF
13	Mely Chen Chi, Shih-Hsu Huang	A Reliable Clock Tree Design Methodology for ASIC Designs.	ISQED	2000	DBLP DOI BibTeX RDF	Clock tree design, Clock tree synthesis
13	Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger	A Methodology for Large-Scale Hardware Verification.	FMCAD	2000	DBLP DOI BibTeX RDF
13	Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara	Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
13	Arun N. Lokanathan, Jay B. Brockman	A methodology for concurrent process-circuit optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
13	Tapas Kanungo, Robert M. Haralick	An Automatic Closed-Loop Methodology for Generating Character Groundtruth for Scanned Documents.	IEEE Trans. Pattern Anal. Mach. Intell.	1999	DBLP DOI BibTeX RDF	Automatic real groundtruth, performance evaluation, OCR, image registration, document image analysis, image warping, geometric transformations
13	Bhaskar D. Rao, Kenneth Kreutz-Delgado	An affine scaling methodology for best basis selection.	IEEE Trans. Signal Process.	1999	DBLP DOI BibTeX RDF
13	Luciana Bordoni, Attilio Colagrossi	A Multimedia Personalized Fruition of Figurative Artistic Heritage by a GIS-Based Methodology.	ICMCS, Vol. 2	1999	DBLP DOI BibTeX RDF	Cultural heritage Multimedia application, Multimedia software engineering tools, Art and Multimedia
13	Joseph C. Bernier, Gregg D. Croft, W. R. Young	A process independent ESD design methodology.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
13	Kenneth Francken, Georges G. E. Gielen	Methodology for analog technology porting including performance tuning.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
13	Cristiana Bolchini, Luigi Pomante, Donatella Sciuto, Fabio Salice	A Synthesis Methodology Aimed at Improving the Quality of TSC Devices.	DFT	1999	DBLP DOI BibTeX RDF	observability, logic synthesis, totally self-checking circuits
13	Sven Wuytack, Jean-Philippe Diguet, Francky Catthoor, Hugo De Man	Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
13	Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta 0001	A timing-driven design and validation methodology for embedded real-time systems.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	period assignment, period derivation, rate assignment, rate derivation, timing-driven codesign, requirements analysis, timing analysis, system-level design, performance verification
13	Ferdinando Lucidi, Hessel P. Idzenga, Spyrogiannis Batistatos	Development of TINA-Like Systems: The DOLEMEN Methodology.	IS&N	1998	DBLP DOI BibTeX RDF
13	Heeseok Lee, Choongseok Lee, Cheonsoo Yoo	A Scenario-Based Object-Oriented Methodology for Developing Hypermedia Information Systems.	HICSS (2)	1998	DBLP DOI BibTeX RDF
13	Prab Varma, Sandeep Bhatia	A structured test re-use methodology for core-based system chips.	ITC	1998	DBLP DOI BibTeX RDF
13	Yuan-Chieh Hsu, Sandeep K. Gupta 0001	A new path-oriented effect-cause methodology to diagnose delay failures.	ITC	1998	DBLP DOI BibTeX RDF
13	Makoto Sugihara, Hiroshi Date, Hiroto Yasuura	A novel test methodology for core-based system LSIs and a testing time minimization problem.	ITC	1998	DBLP DOI BibTeX RDF
13	Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv	User Defined Coverage - A Tool Supported Methodology for Design Verification.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
13	Samit Chaudhuri, S. A. Blthye, Robert A. Walker 0001	A solution methodology for exact design space exploration in a three-dimensional design space.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
13	Larry Scanlan, Wing Lee, Mike Vahey, Mike McCollough	RASSP Methodology Evaluation and Lessons Learned Developing IRST Signal Processor.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
13	Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps.	ICCAD	1997	DBLP DOI BibTeX RDF	behavioral signal path, incremental modeling, small-signal, sequential design space pruning, minimax optimization
13	Robert L. Kelsey, Roger T. Hartley, Robert B. Webster	An Object-Based Methodology for Knowledge Representation in SGML.	ICTAI	1997	DBLP DOI BibTeX RDF	knowledge representation SGML multiple perspectives
13	José Luis Neves, Eby G. Friedman	Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
13	Seong-Whan Lee, Dong-June Lee, Hee-Seon Park	A New Methodology for Gray-Scale Character Segmentation and Recognition.	IEEE Trans. Pattern Anal. Mach. Intell.	1996	DBLP DOI BibTeX RDF	Character segmentation and recognition, topographic feature, multistage graph search, recognition-based segmentation, gray-scale character recognition
13	Curtis A. Carver, Richard A. Howard, William D. Lane	A methodology for active, student-controlled learning: motivating our weakest students.	SIGCSE	1996	DBLP DOI BibTeX RDF
13	Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker 0001	An exact methodology for scheduling in a 3D design space.	ISSS	1995	DBLP DOI BibTeX RDF	2D design space, 3D design space, 3D scheduling problem, Voyager design space exploration system, candidate clock lengths, clock length, globally optimal solution, schedule length, three dimensional scheduling, three-dimensional design space, two dimensional design space, scheduling, optimisation, high level synthesis, search problems, clocks, tight bounds, network synthesis, search space pruning