Search results for "AES"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Mooseop Kim, Jaecheol Ryou 0001, YongJe Choi, Sungik Jun	Low Power AES Hardware Architecture for Radio Frequency Identification.	IWSEC	2006	DBLP DOI BibTeX RDF
47	Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu	A configurable AES processor for enhanced security.	ASP-DAC	2005	DBLP DOI BibTeX RDF
47	Johannes Blömer, Jorge Guajardo, Volker Krummel	Provably Secure Masking of AES.	Selected Areas in Cryptography	2004	DBLP DOI BibTeX RDF
47	Norbert Pramstaller, Johannes Wolkerstorfer	A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays.	FPL	2004	DBLP DOI BibTeX RDF
47	Valeri F. Tomashau, Tom Kean	Validation of an Advanced Encryption Standard (AES) IP Core.	FCCM	2004	DBLP DOI BibTeX RDF
47	Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo	An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm.	FPL	2003	DBLP DOI BibTeX RDF
47	Nazar Abbas Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez	Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core.	FPL	2003	DBLP DOI BibTeX RDF
47	Beomsik Song, Jennifer Seberry	Further Observations on the Structure of the AES Algorithm.	FSE	2003	DBLP DOI BibTeX RDF	Cyclic Properties, SubBytes transformation, ShiftRows transformation, MixColumns transformation, Maximal period
47	Akashi Satoh, Sumio Morioka	Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia.	CHES	2003	DBLP DOI BibTeX RDF
45	Andrew Moss, Dan Page	Bridging the gap between symbolic and efficient AES implementations.	PEPM	2010	DBLP DOI BibTeX RDF	cao, memoisation, vectorisation, aes
45	David Canright, Dag Arne Osvik	A More Compact AES.	Selected Areas in Cryptography	2009	DBLP DOI BibTeX RDF	tower field, composite Galois field, bitslice, AES
45	Kazuo Sakiyama, Tatsuya Yagi, Kazuo Ohta	Fault Analysis Attack against an AES Prototype Chip Using RSL.	CT-RSA	2009	DBLP DOI BibTeX RDF	Random Switching Logic, Clock-based Attack, AES, Fault Analysis
45	Emilia Käsper, Peter Schwabe	Faster and Timing-Attack Resistant AES-GCM.	CHES	2009	DBLP DOI BibTeX RDF	Galois/Counter mode, cache-timing attacks, AES, fast implementations
45	David Canright, Lejla Batina	A Very Compact "Perfectly Masked" S-Box for AES.	ACNS	2008	DBLP DOI BibTeX RDF	composite Galois field, AES, DPA, S-box, masking
45	Daniel J. Bernstein, Peter Schwabe	New AES Software Speed Records.	INDOCRYPT	2008	DBLP DOI BibTeX RDF	AES, software implementation
45	Andrey Bogdanov	Multiple-Differential Side-Channel Collision Attacks on AES.	CHES	2008	DBLP DOI BibTeX RDF	multiple-differential collision attacks, AES, collision detection, side-channel attacks, DPA
45	Johannes Blömer, Volker Krummel	Analysis of Countermeasures Against Access Driven Cache Attacks on AES.	Selected Areas in Cryptography	2007	DBLP DOI BibTeX RDF	AES, countermeasures, threat model, random permutations, cache attacks
45	Onur Aciiçmez, Werner Schindler, Çetin Kaya Koç	Cache Based Remote Timing Attack on the AES.	CT-RSA	2007	DBLP DOI BibTeX RDF	Remote Attack, AES, Timing Analysis, Side Channel Analysis, Cache Attack
45	Alex Biryukov, Andrey Bogdanov, Dmitry Khovratovich, Timo Kasper	Collision Attacks on AES-Based MAC: Alpha-MAC.	CHES	2007	DBLP DOI BibTeX RDF	Alpha-MAC, selective forgery, MAC, AES, side-channel attack, message authentication codes, collision attack
45	Michael Neve, Jean-Pierre Seifert, Zhenghong Wang	A refined look at Bernstein's AES side-channel analysis.	AsiaCCS	2006	DBLP DOI BibTeX RDF	cache-state analysis, s-box tables, AES, computer security, timing analysis, side-channel analysis, information leakage
45	Dag Arne Osvik, Adi Shamir, Eran Tromer	Cache Attacks and Countermeasures: The Case of AES.	CT-RSA	2006	DBLP DOI BibTeX RDF	cache, cryptanalysis, AES, side-channel attack, memory access
45	Onur Aciiçmez, Çetin Kaya Koç	Trace-Driven Cache Attacks on AES (Short Paper).	ICICS	2006	DBLP DOI BibTeX RDF	trace-driven attacks, AES, Side-channel Analysis, cache attacks
45	Kubilay Atasu, Luca Breveglieri, Marco Macchetti	Efficient AES implementations for ARM based platforms.	SAC	2004	DBLP DOI BibTeX RDF	ARM microprocessor, AES, cache memories, code optimisation
45	An Yu, David S. Brée	A Clock-less Implementation of the AES Resists to Power and Timing Attacks.	ITCC (2)	2004	DBLP DOI BibTeX RDF	clock-less circuits, AES, timing attacks, cryptosystems, power attacks
45	Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat	Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications.	ITCC (2)	2004	DBLP DOI BibTeX RDF	compact encryption/decryption implementation, FPGA, Cryptography, AES, DES
44	Mansoor Ahmed Khan, Ahmad Raza Cheema, Aamir Hasan 0001	Improved Nonce Construction Scheme for AES CCMP to Evade Initial Counter Prediction.	SNPD	2008	DBLP DOI BibTeX RDF	AES CCMP, Initial Counter, Key Length, TMTO, Integrity, Encryption, Confidentiality, Nonce, IEEE 802.11i
44	Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli	Multi-gigabit GCM-AES Architecture Optimized for FPGAs.	CHES	2007	DBLP DOI BibTeX RDF	Galois/Counter Mode (GCM), hybrid multiplier, Field Programmable Gate Array (FPGA), Very Large Scale Integration (VLSI), Advanced Encryption Standard (AES), high throughput, digit-serial multiplier, bit-parallel multiplier
44	Tim Good, Mohammed Benaissa	AES on FPGA from the Fastest to the Smallest.	CHES	2005	DBLP DOI BibTeX RDF	low area, Application Specific Instruction Processor (ASIP), Field Programmable Gate Array (FPGA), pipelined, Advanced Encryption Standard (AES), finite field, high throughput, design exploration
44	Stefan Mangard, Manfred Josef Aigner, Sandra Dominikus	A Highly Regular and Scalable AES Hardware Architecture.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	IP module, scalability, VLSI, Advanced Encryption Standard (AES), regularity, hardware architecture
44	Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger	An ASIC Implementation of the AES SBoxes.	CT-RSA	2002	DBLP DOI BibTeX RDF	standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic
43	Vivaksha J. Jariwala, Devesh C. Jinwala	A taxonomy of security attacks on the advanced encryption standard.	ICIS	2009	DBLP DOI BibTeX RDF	advanced encryption standard, attacks, cipher
41	Nicolas T. Courtois, Gregory V. Bard	Algebraic Cryptanalysis of the Data Encryption Standard.	IMACC	2007	DBLP DOI BibTeX RDF	s5DES, solving overdefined and sparse systems of multivariate equations, ElimLin algorithm, Gröbner bases, logical cryptanalysis, block ciphers, AES, DES, SAT solvers, algebraic cryptanalysis
41	Batbold Toiruul, KyungOh Lee, HyunJun Lee, YoungHan Lee, Yoon Young Park	Mutual-Authentication Mechanism for RFID Systems.	MSN	2006	DBLP DOI BibTeX RDF	RFID, AES, cryptograph
41	An Braeken, Christopher Wolf, Bart Preneel	Normality of Vectorial Functions.	IMACC	2005	DBLP DOI BibTeX RDF	propagation characteristics, APN, algorithm, Cryptography, AES, normality, S-box
40	Chong Hee Kim	Differential Fault Analysis against AES-192 and AES-256 with Minimal Faults.	FDTC	2010	DBLP DOI BibTeX RDF	AES, Fault attack, DFA, Differential Fault Analysis
39	John Worley, Bill Worley, Tom Christian, Christopher Worley	AES Finalists on PA-RISC and IA-64: Implementations & Performance.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Nicholas Weaver, John Wawrzynek	A Comparison of the AES Candidates Amenability to FPGA Implementation.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Kazumaro Aoki, Helger Lipmaa	Fast Implementations of AES Candidates.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Jim Dray	NIST Performance Analysis of the Final Round JavaTM AES Candidates.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Don B. Johnson	AES and Future Resiliency: More Thoughts and Questions.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Ronald L. Rivest, Matthew J. B. Robshaw, Yiqun Lisa Yin	RC6 as the AES.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Richard Weiss 0001, Nathan L. Binkert	A Comparison of AES Candidates on the Alpha 21264.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Kris Gaj, Pawel Chodowiec	Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Adam J. Elbirt, W. Yip, B. Chetwynd, Christof Paar	An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Bruce Schneier, John Kelsey, Doug Whiting, David A. Wagner 0001, Niels Ferguson	Comments on Twofish as an AES Candidate.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Joan Daemen, Vincent Rijmen	Rijndael for AES.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Fumihiko Sano, Masanobu Koike, Shin-ichi Kawamura, Masue Shiba	Performance Evaluation of AES Finalists on the High-End Smart Card.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Andreas Sterbenz, Peter Lipp	Performance of the AES Candidate Algorithms in Java.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Tetsuya Ichikawa, Tomomi Kasuya, Mitsuru Matsui	Hardware Evaluation of the AES Finalists.	AES Candidate Conference	2000	DBLP BibTeX RDF
39	Bruce Schneier, Doug Whiting	A Performance Comparison of the Five AES Finalists.	AES Candidate Conference	2000	DBLP BibTeX RDF
38	Jun Wu, Yong-Bin Kim, Minsu Choi	Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	substitution box, substitution box (S-box), differential power/noise analysis, power/noise measurement, security, advanced encryption standard, advanced encryption standard, side-channel attacks (SCA), null convention logic
38	Raphael Weber, Achim Rettberg	Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture.	ARC	2009	DBLP DOI BibTeX RDF
38	Jesús Lázaro 0001, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga	AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications.	ARC	2009	DBLP DOI BibTeX RDF
38	Xu Guo 0001, Zhimin Chen 0002, Patrick Schaumont	Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors.	SAMOS	2008	DBLP DOI BibTeX RDF
38	Saar Drimer, Tim Güneysu, Christof Paar	DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
38	Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda	Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems.	IWSEC	2008	DBLP DOI BibTeX RDF
38	John Goodwin, Peter R. Wilson	Advanced Encryption Standard (AES) implementation with increased DPA resistance and low overhead.	ISCAS	2008	DBLP DOI BibTeX RDF
38	Andres Garcia, Mladen Berekovic, Tom Vander Aa	Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor.	ASAP	2008	DBLP DOI BibTeX RDF
38	Monjur Alam, Sonai Ray, Debdeep Mukhopadhyay, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta 0001	An area optimized reconfigurable encryptor for AES-Rijndael.	DATE	2007	DBLP DOI BibTeX RDF
38	Stefan Tillich, Martin Feldhofer, Johann Großschädl	Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box.	SAMOS	2006	DBLP DOI BibTeX RDF
38	Joan Daemen, Vincent Rijmen	Understanding Two-Round Differentials in AES.	SCN	2006	DBLP DOI BibTeX RDF
38	Chester Rebeiro, A. David Selvakumar, A. S. L. Devi	Bitslice Implementation of AES.	CANS	2006	DBLP DOI BibTeX RDF
38	Stefan Tillich, Johann Großschädl	Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors.	CHES	2006	DBLP DOI BibTeX RDF	embedded RISC processor, SPARC V8 architecture, Advanced Encryption Standard, instruction set extensions, efficient implementation
38	Yu-Jung Huang, Yang-Shih Lin, Kuang-Yu Hung, Kuo-Chen Lin	Efficient Implementation of AES IP.	APCCAS	2006	DBLP DOI BibTeX RDF
38	Stefan Tillich, Johann Großschädl, Alexander Szekely	An Instruction Set Extension for Fast and Memory-Efficient AES Implementation.	Communications and Multimedia Security	2005	DBLP DOI BibTeX RDF	32-bit implementation, cache-based side-channel analysis, Advanced Encryption Standard, S-box, instruction set extensions
38	Stefan Tillich, Johann Großschädl	Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography.	ICCSA (2)	2005	DBLP DOI BibTeX RDF	32-bit implementation, software acceleration, Advanced Encryption Standard, Rijndael, instruction set extensions
38	Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald	Successfully Attacking Masked AES Hardware Implementations.	CHES	2005	DBLP DOI BibTeX RDF
38	David Canright	A Very Compact S-Box for AES.	CHES	2005	DBLP DOI BibTeX RDF
38	Alireza Hodjat, Ingrid Verbauwhede	Minimum Area Cost for a 30 to 70 Gbits/s AES Processor.	ISVLSI	2004	DBLP DOI BibTeX RDF
38	Joseph Zambreno, David Nguyen, Alok N. Choudhary	Exploring Area/Delay Tradeoffs in an AES FPGA Implementation.	FPL	2004	DBLP DOI BibTeX RDF
38	Akashi Satoh, Sumio Morioka	Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES.	ISC	2003	DBLP DOI BibTeX RDF
38	James Irwin, Dan Page	Using Media Processors for Low-Memory AES Implementation.	ASAP	2003	DBLP DOI BibTeX RDF
38	Stanley Chow, Philip A. Eisen, Harold Johnson, Paul C. van Oorschot	White-Box Cryptography and an AES Implementation.	Selected Areas in Cryptography	2002	DBLP DOI BibTeX RDF
37	Noémie Floissac, Yann L'Hyver	From AES-128 to AES-192 and AES-256, How to Adapt Differential Fault Analysis Attacks on Key Expansion.	FDTC	2011	DBLP DOI BibTeX RDF
37	Noémie Floissac, Yann L'Hyver	From AES-128 to AES-192 and AES-256, How to Adapt Differential Fault Analysis Attacks.	IACR Cryptol. ePrint Arch.	2010	DBLP BibTeX RDF
36	Owen Harrison, John Waldron	AES Encryption Implementation and Analysis on Commodity Graphics Processing Units.	CHES	2007	DBLP DOI BibTeX RDF	GPU, AES, Hardware Accelerated, Graphics Processor
36	Joshua Jaffe	A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter.	CHES	2007	DBLP DOI BibTeX RDF	HO-DPA, AES, DPA, power analysis, SPA, counter mode
36	Hua Li, Jianzhou Li	A High Performance Sub-Pipelined Architecture for AES.	ICCD	2005	DBLP DOI BibTeX RDF	sub-pipelined architecture, FPGA, cryptography, AES
36	Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin	A 2 Gb/s balanced AES crypto-chip implementation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	AES, rijndael, ASIC implementation
36	Kai Schramm, Christof Paar	IT Security Project: Implementation of the Advanced Encryption Standard (AES) on a Smart Card.	ITCC (1)	2004	DBLP DOI BibTeX RDF	RISC architecture, smart cards, AES, side channel attacks
36	Nicolas Sklavos 0001, Odysseas G. Koufopavlou	Architectures and VLSI Implementations of the AES-Proposal Rijndael.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	secret key ciphers, security, AES, Rijndael, pipelining architectures
35	Lejla Batina, Benedikt Gierlichs, Kerstin Lemke-Rust	Comparative Evaluation of Rank Correlation Based DPA on an AES Prototype Chip.	ISC	2008	DBLP DOI BibTeX RDF	Differential side-channel analysis, AES hardware, Stochastic model, DPA, Rank correlation, Template attacks
35	M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre	AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis.	DELTA	2008	DBLP DOI BibTeX RDF	AES core, BIST, secure systems
35	Shin-Yi Lin, Chih-Tsun Huang	A High-Throughput Low-Power AES Cipher for Network Applications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, low-power AES cipher, two-stage pipeline, CCM mode, design-for-test circuitry, 4.27 Gbits/s, 333 MHz, 40.9 mW, CMOS technology, network applications
35	François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat	A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL.	FPGA	2003	DBLP DOI BibTeX RDF	AES RIJNDAEL, high encryption rates, FPGA, cryptography, reconfigurable hardware
34	Mehran Mozaffari Kermani, Arash Reyhani-Masoleh	A low-cost S-box for the Advanced Encryption Standard using normal basis.	EIT	2009	DBLP DOI BibTeX RDF
34	Hiroshi Kudou, Shunn-ichiro Nakayama, Atsushi Watanabe, Tomoyuki Nagase, Yoshio Yoshioka	A Reconfigurable-Permutation Algorithm for M_S-Box.	ARES	2009	DBLP DOI BibTeX RDF
34	Gordon Meiser, Thomas Eisenbarth 0001, Kerstin Lemke-Rust, Christof Paar	Efficient implementation of eSTREAM ciphers on 8-bit AVR microcontrollers.	SIES	2008	DBLP DOI BibTeX RDF
34	Anna Slobodová	Formal Verification of Hardware Support for Advanced Encryption Standard.	FMCAD	2008	DBLP DOI BibTeX RDF
34	Martin Feldhofer, Christian Rechberger	A Case Against Currently Used Hash Functions in RFID Protocols.	OTM Workshops (1)	2006	DBLP DOI BibTeX RDF
34	Adam Matthews	A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard.	ISQED	2006	DBLP DOI BibTeX RDF
34	Nadia Nedjah, Luiza de Macedo Mourelle	A Versatile Pipelined Hardware Implementation for Encryption and Decryption Using Advanced Encryption Standard.	VECPAR	2006	DBLP DOI BibTeX RDF
34	Refik Sever, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar, Burak Okcan	A High Speed FPGA Implementation of the Rijndael Algorithm.	DSD	2004	DBLP DOI BibTeX RDF
34	Pierre Dusart, Gilles Letourneux, Olivier Vivolo	Differential Fault Analysis on A.E.S.	ACNS	2003	DBLP DOI BibTeX RDF
32	Xuewang Zhang, Linlin Wang	Key Technologies for Security Enhancing of Payment Gateway.	ISECS	2008	DBLP DOI BibTeX RDF	payment gateway, security enhancing, fusion-based solution for SSL and SET protocols, secure hash algorithm, AES
32	Andrey Bogdanov, Ilya Kizhvatov, Andrei Pyshkin	Algebraic Methods in Side-Channel Collision Attacks and Practical Collision Detection.	INDOCRYPT	2008	DBLP DOI BibTeX RDF	multiple-differential collision attacks, ternary voting, AES, Side-channel attacks, DPA, collision attacks, algebraic cryptanalysis
32	Zong Wang, Tughrul Arslan, Ahmet T. Erdogan	Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture.	DELTA	2008	DBLP DOI BibTeX RDF	Hardware Encryption, RICA, AES, RC4
32	Michael Hutter, Stefan Mangard, Martin Feldhofer	Power and EM Attacks on Passive 13.56 MHz RFID Devices.	CHES	2007	DBLP DOI BibTeX RDF	EM Attacks, RFID, AES, Side-Channel Attacks, DPA, Power Analysis, DEMA
32	Emmanuel Prouff, Christophe Giraud 0001, Sébastien Aumônier	Provably Secure S-Box Implementation Based on Fourier Transform.	CHES	2006	DBLP DOI BibTeX RDF	Provably Secure Countermeasure, Symmetric Cryptosystems, FOX, AES, Differential Power Analysis, Fourier Transform, S-Box
32	Debra L. Cook, John Ioannidis, Angelos D. Keromytis, Jake Luck	CryptoGraphics: Secret Key Cryptography Using Graphics Cards.	CT-RSA	2005	DBLP DOI BibTeX RDF	Graphics Processing Unit, Stream Ciphers, Block Ciphers, AES