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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 319 occurrences of 228 keywords
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Results
Found 105 publication records. Showing 105 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | José Monteiro 0001, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh |
Optimization of combinational and sequential logic circuits for low power using precomputation. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle |
1 | Scott Hauck, Gaetano Borriello |
An evaluation of bipartitioning techniques. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
bipartitioning techniques, VLSI, logic CAD, integrated circuit design, circuit CAD, logic partitioning, logic partitioning, VLSI CAD |
1 | Andreas G. Andreou, Kwabena A. Boahen |
A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
silicon retina, analog VLSI focal plane processor, phototransduction, local gain control, single chip system, vertebrate distal retina, ultra low power dissipation, n-well double metal double poly digital oriented CMOS technology, current-mode subthreshold CMOS, 48000 pixel, computer vision, VLSI, edge detection, CMOS integrated circuits, image sensors, contrast, edge enhancement, CMOS imager, focal planes, area efficiency, 1.2 micron |
1 | Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng |
Automatic synthesis of gate-level timed circuits with choice. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates |
1 | Michael Bolotski, Thomas Simon, Carlin Vieri, Rajeevan Amirtharajah, Thomas F. Knight Jr. |
Abacus: a 1024 processor 8 ns SIMD array. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
bit-slice computers, Abacus, SIMD array, reconfigurable bit-parallel array, system-level design issues, real-time early vision processing, bit-slice processing element, 8 ns, real-time systems, computer vision, VLSI, parallel architectures, reconfigurable architectures, microarchitecture, VLSI implementation, communication primitives |
Displaying result #101 - #105 of 105 (100 per page; Change: ) Pages: [ <<][ 1][ 2] |
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