Search results for "ASICs"

Hits ?▲	Authors	Title	Venue	Year	Link
20	Ian Gibson, Chris Amies	Practical concurrent ASIC and system design and verification.	ED&TC	1997	DBLP DOI BibTeX RDF
20	Ivan C. Kraljic, Georges Quénot, Bertrand Y. Zavidovique	From real-time emulation to ASIC integration for image processing applications.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
20	Mani B. Srivastava, Robert W. Brodersen	System level hardware module generation.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
19	Goeran Jerke	Physical Design Challenges for Automotive ASICs.	ISPD	2024	DBLP DOI BibTeX RDF
19	Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula	A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
19	Joël Lindegger, Damla Senol Cali, Mohammed Alser, Juan Gómez-Luna, Nika Mansouri-Ghiasi, Onur Mutlu	Scrooge: a fast and memory-frugal genomic sequence aligner for CPUs, GPUs, and ASICs.	Bioinform.	2023	DBLP DOI BibTeX RDF
19	Javier Campos, Zhen Dong, Javier M. Duarte, Amir Gholami, Michael W. Mahoney, Jovan Mitrevski, Nhan Tran	End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICs.	CoRR	2023	DBLP DOI BibTeX RDF
19	Yan Zou, Tian Pan 0001, Lu Lu, Zhiqiang Li, Kehan Yao, Tao Huang, Yunjie Liu	P4RSS: Load-Aware Intra-Server Load Balancing with Programmable Switching ASICs.	ICC	2023	DBLP DOI BibTeX RDF
19	Wei Jiang, Hao Jiang 0010, Jing Wu 0016, Pengcheng Zhou	Accelerating Network Coding with Programmable Switch ASICs.	ICC	2023	DBLP DOI BibTeX RDF
19	Jinghui Jiang, Zhenpei Huang, Qiao Xiang, Lu Tang 0004, Jiwu Shu	Poster: P4-DPLL: Accelerating SAT Solving Using Switching ASICs.	SIGCOMM	2023	DBLP DOI BibTeX RDF
19	Rashid Karim, Marco Grassi, Piero Malcovati	1st-Order Error-Feedback Sampling-Rate Reconfigurable Noise-Shaping SAR ADC for Multi-Channel CMOS Front-End ASICs for Space Applications.	NEWCAS	2023	DBLP DOI BibTeX RDF
19	David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman	Low power cryogenic RF ASICs for quantum computing.	CICC	2023	DBLP DOI BibTeX RDF
19	Zhenpei Huang, Xiwen Fan, Jinghui Jiang, Mingyuan Song, Lu Tang 0004, Qiao Xiang, Jiwu Shu	Accelerating SAT Solving Using Switching ASICs.	ICPADS	2023	DBLP DOI BibTeX RDF
19	Junfeng Liu, Liwei Ni, Xingquan Li, Min Zhou, Lei Chen, Xing Li, Qinghua Zhao, Shuai Ma 0001	AiMap: Learning to Improve Technology Mapping for ASICs via Delay Prediction.	ICCD	2023	DBLP DOI BibTeX RDF
19	Joël Lindegger, Damla Senol Cali, Mohammed Alser, Juan Gómez-Luna, Nika Mansouri-Ghiasi, Onur Mutlu	Scrooge: A Fast and Memory-Frugal Genomic Sequence Aligner for CPUs, GPUs, and ASICs.	CoRR	2022	DBLP DOI BibTeX RDF
19	David Watkins-Valls	Scrypt Mining with ASICs.	CoRR	2022	DBLP DOI BibTeX RDF
19	Alexander Barkalov 0001, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz, Elzbieta Kawecka	Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs		2022	DOI RDF
19	Jinghui Jiang, Zhenpei Huang, Qiao Xiang, Lu Tang 0004, Jiwu Shu	P4-DPLL: accelerating SAT solving using switching ASICs.	FFSPIN@SIGCOMM	2022	DBLP DOI BibTeX RDF
19	Christos Georgakidis, Stavros Simoglou, Christos P. Sotiriou	RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening.	DFT	2022	DBLP DOI BibTeX RDF
19	Sandeep Miryala, Md. Adnan Zaman, Sandeep Mittal, Yihui Ren 0001, Grzegorz Deptuch, Gabriella Carini, Sioan Zohar, Shinjae Yoo, Jack Fried, Jin Huang, Srinivas Katkoori	Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications.	ISQED	2022	DBLP DOI BibTeX RDF
19	Sandeep Miryala, Gabriella Carini, Grzegorz Deptuch, Jin Huang, Srinivas Katkoori, Piotr Maj, Soumyajit Mandal, Yihui Ren 0001, Md. Adnan Zaman	Design and Challenges of Edge Computing ASICs on Front-End Electronics.	ISQED	2022	DBLP DOI BibTeX RDF
19	Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon	Improving LUT-based optimization for ASICs.	DAC	2022	DBLP DOI BibTeX RDF
19	Michael Mattioli	FPGAs in Client Compute Hardware: Despite certain challenges, FPGAs provide security and performance benefits over ASICs.	ACM Queue	2021	DBLP DOI BibTeX RDF
19	Diksha Moolchandani, Anshul Kumar, Smruti R. Sarangi	Accelerating CNN Inference on ASICs: A Survey.	J. Syst. Archit.	2021	DBLP DOI BibTeX RDF
19	Sebastian Strempfer, Kazutomo Yoshii, Mike Hammer, Dawid Bycul, Antonino Miceli	Designing a Streaming Data Coalescing Architecture for Scientific Detector ASICs with Variable Data Velocity.	XLOOP@SC	2021	DBLP DOI BibTeX RDF
19	Enric M. Calvo, Philippe Renevey, Mathieu Lemay, Andrea Bonetti, Marc Pons Solé, Régis Cattenoz, Stéphane Emery, Ricard Delgado-Gonzalo	Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs.	EMBC	2021	DBLP DOI BibTeX RDF
19	Andrea Floridia, Ernesto Sánchez 0001	A JTAG-based Fault Emulation Platform for Dependability Analyses of Processor-based ASICs.	LASCAS	2021	DBLP DOI BibTeX RDF
19	Shicheng Wang, Menghao Zhang, Guanyu Li, Chang Liu, Ying Liu, Xuya Jia, Mingwei Xu	Making Multi-String Pattern Matching Scalable and Cost-Efficient with Programmable Switching ASICs.	INFOCOM	2021	DBLP DOI BibTeX RDF
19	Chetan Deshpande, Ritesh Garg, Gajanan Jedhe, Gaurang Narvekar, Sushil Kumar	A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry Update Capability for Data Center ASICs.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
19	Chaya Ganesh, Claudio Orlandi, Daniel Tschudi, Aviv Zohar	Virtual ASICs: Generalized Proof-of-Stake Mining in Cryptocurrencies.	DPM/CBT@ESORICS	2021	DBLP DOI BibTeX RDF
19	Jinuk Kim, Muhammad Ibtesam, Dooyoung Kim, Jihun Jung, Sungju Park	CAN-Based Aging Monitoring Technique for Automotive ASICs With Efficient Soft Error Resilience.	IEEE Access	2020	DBLP DOI BibTeX RDF
19	Aseem Sayal, Paras Ajay, Mark W. McDermott, S. V. Sreenivasan, Jaydeep P. Kulkarni	M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
19	Aviv Yaish, Aviv Zohar	Pricing ASICs for Cryptocurrency Mining.	CoRR	2020	DBLP BibTeX RDF
19	Pengfei Xu 0011, Xiaofan Zhang 0001, Cong Hao, Yang Zhao 0013, Yongan Zhang, Yue Wang 0036, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin	AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs.	CoRR	2020	DBLP BibTeX RDF
19	Chaya Ganesh, Claudio Orlandi, Daniel Tschudi, Aviv Zohar	Virtual ASICs: Generalized Proof-of-Stake Mining in Cryptocurrencies.	IACR Cryptol. ePrint Arch.	2020	DBLP BibTeX RDF
19	Pengfei Xu 0011, Xiaofan Zhang 0001, Cong Hao, Yang Zhao 0013, Yongan Zhang, Yue Wang 0036, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin	AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs.	FPGA	2020	DBLP DOI BibTeX RDF
19	Jiaqi Gao, Ennan Zhai, Hongqiang Harry Liu, Rui Miao, Yu Zhou 0008, Bingchuan Tian, Chen Sun 0005, Dennis Cai, Ming Zhang 0005, Minlan Yu	Lyra: A Cross-Platform Language and Compiler for Data Plane Programming on Heterogeneous ASICs.	SIGCOMM	2020	DBLP DOI BibTeX RDF
19	Jianyu Zhao, Ayman Mohamed, Jens Anders	An Active CMOS NMR Field Probe with Custom Transceiver and ΣΔ Modulator ASICs and an Optical Link.	ISCAS	2020	DBLP DOI BibTeX RDF
19	Lars Brusberg, Aramais R. Zakharian, Sükrü Ekin Kocabas, Jason R. Grenier, Chad C. Terwilliger, Alan F. Evans	Optoelectronic Glass Substrates for Co-Packaging of Optics and ASICs.	OFC	2020	DBLP BibTeX RDF
19	Shuhe Wang, Chen Sun 0005, Zili Meng, Minhu Wang, Jiamin Cao, Mingwei Xu, Jun Bi, Qun Huang 0001, Masoud Moshref, Tong Yang 0003, Hongxin Hu, Gong Zhang 0001	Martini: Bridging the Gap between Network Measurement and Control Using Switching ASICs.	ICNP	2020	DBLP DOI BibTeX RDF
19	Gaëlle Lefort, Laurence Liaubet, Cécile Canlet, Patrick Tardivel, Marie-Christine Père, Hélène Quesnel, Alain Paris, Nathalie Iannuccelli, Nathalie Vialaneix, Rémi Servien	ASICS: an R package for a whole analysis workflow of 1D 1H NMR spectra.	Bioinform.	2019	DBLP DOI BibTeX RDF
19	Mohamed Chentouf, Soukaina Mourssi, Zine El Abidine Alaoui Ismaili	Power aware setup timing optimization in physical design of ASICs.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
19	Thorben Moos	Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2019	DBLP DOI BibTeX RDF
19	Simona Cometti, Giovanni Mazza	New ASICs for the Very Front-End Card Upgrade of the CMS ECAL Barrel at the HL-LHC.	PRIME	2019	DBLP DOI BibTeX RDF
19	Massimo Gandola, Marco Grassi, Filippo Mele, Giuseppe Bertuccio, Piero Malcovati	Mixed-Signal ASICs for X- and γ-Ray Spectroscopy in Space Applications.	ICECS	2019	DBLP DOI BibTeX RDF
19	Albert Magyar, David Biancolin, John Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanovic	Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes.	ICCAD	2019	DBLP DOI BibTeX RDF
19	Yehya Nasser, Carlo Sau, Jean-Christophe Prévotet, Tiziana Fanni, Francesca Palumbo, Maryline Hélard, Luigi Raffo	NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology.	CF	2019	DBLP DOI BibTeX RDF
19	Pravein Govindan Kannan, Raj Joshi, Mun Choon Chan	Precise Time-synchronization in the Data-Plane using Programmable Switching ASICs.	SOSR	2019	DBLP DOI BibTeX RDF
19	Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang	Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs.	VLSI-DAT	2019	DBLP DOI BibTeX RDF
19	Yu-Kuen Lai, Ku-Yeh Shih, Po-Yu Huang, Ho-Ping Lee, Yu-Jau Lin, Te-Lung Liu, Jim Hao Chen	Sketch-based Entropy Estimation for Network Traffic Analysis using Programmable Data Plane ASICs.	ANCS	2019	DBLP DOI BibTeX RDF
19	Aidin Amirkhani	Design of analog ASICs for X-ray detectors.		2019	RDF
19	Massimo Gandola	Low-noise, Low-power Front-End ASICs for high-resolution X and Gamma ray spectroscopy for radiation semiconductor detector.		2019	RDF
19	Caiwen Ding, Ao Ren, Geng Yuan, Xiaolong Ma, Jiayu Li, Ning Liu 0007, Bo Yuan 0001, Yanzhi Wang	Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.	CoRR	2018	DBLP BibTeX RDF
19	Yu Wu 0007, Dai Jiang, Andy Bardill, Serena De Gelidi, Richard H. Bayford, Andreas Demosthenous	A High Frame Rate Wearable EIT System Using Active Electrode ASICs for Lung Respiration and Heart Rate Monitoring.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
19	Alessandro Caratelli, Simone Scarfi, Davide Ceresa, Kostas Kloukinas, Yusuf Leblebici	System Level simulation framework for the ASICs development of a novel particle physics detector.	PRIME	2018	DBLP DOI BibTeX RDF
19	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
19	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.	FPL	2018	DBLP DOI BibTeX RDF
19	Jiasong Bai, Jun Bi, Menghao Zhang, Guanyu Li	Filtering Spoofed IP Traffic Using Switching ASICs.	SIGCOMM Posters and Demos	2018	DBLP DOI BibTeX RDF
19	Yusuke Kitada, Jun Fujiwara, Nobumasa Hattori, Kensuke Kanda, Takayuki Fujita, Kazusuke Maenaka	Integration of MPU and ASICs for Low-Power Human Monitoring System.	SMC	2018	DBLP DOI BibTeX RDF
19	Aljoscha Kirchner, Jan-Hendrik Oetjens, Oliver Bringmann 0001	Using SysML for Modelling and Code Generation for Smart Sensor ASICs.	FDL	2018	DBLP DOI BibTeX RDF
19	Zhiyuan Yang 0001, Ankur Srivastava 0001	Value-driven Synthesis for Neural Network ASICs.	ISLPED	2018	DBLP DOI BibTeX RDF
19	Theo Jepsen, Masoud Moshref, Antonio Carzaniga, Nate Foster, Robert Soulé	Packet Subscriptions for Programmable ASICs.	HotNets	2018	DBLP DOI BibTeX RDF
19	Caiwen Ding, Ao Ren, Geng Yuan, Xiaolong Ma, Jiayu Li, Ning Liu 0007, Bo Yuan 0001, Yanzhi Wang	Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.	ACM Great Lakes Symposium on VLSI	2018	DBLP DOI BibTeX RDF
19	P. Gkountoumis	Prototype board development for the validation of the VMM ASICs for the new small wheel ATLAS upgrade project.	MOCAST	2018	DBLP DOI BibTeX RDF
19	Junying Chai	Power Management Circuits for Front-End ASICs Employed in High Energy Physics Applications.		2018	RDF
19	Colin Boyd, Cas Cremers, Michèle Feltz, Kenneth G. Paterson, Bertram Poettering, Douglas Stebila	ASICS: authenticated key exchange security incorporating certification systems.	Int. J. Inf. Sec.	2017	DBLP DOI BibTeX RDF
19	Anees Ullah, Ernesto Sánchez 0001, Luca Sterpone, Luis Andrés Cardona, Carles Ferrer 0001	An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
19	Jeongkeun Lee, Rui Miao, Changhoon Kim, Minlan Yu, Hongyi Zeng	Stateful Layer-4 Load Balancing in Switching ASICs.	SIGCOMM Posters and Demos	2017	DBLP DOI BibTeX RDF
19	Rui Miao, Hongyi Zeng, Changhoon Kim, Jeongkeun Lee, Minlan Yu	SilkRoad: Making Stateful Layer-4 Load Balancing Fast and Cheap Using Switching ASICs.	SIGCOMM	2017	DBLP DOI BibTeX RDF
19	Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt	Fault injection methodology for single event effects on clock-gated ASICs.	LATS	2017	DBLP DOI BibTeX RDF
19	Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula	Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
19	Xiao Liu 0001, Zhulin Zong, Dai Jiang, Bachir Bougaila, Nick Donaldson, Andreas Demosthenous	Advances in Scalable Implantable Systems for Neurostimulation Using Networked ASICs.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
19	Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto	Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.	TrustED@CCS	2016	DBLP DOI BibTeX RDF
19	Marco Bekooij	From dataflow analysis basics to the programming of ASICs.	SCOPES	2016	DBLP DOI BibTeX RDF
19	Keisuke Inoue	ECC module optimization for storage transient error-tolerant ASICs.	ICECS	2016	DBLP DOI BibTeX RDF
19	Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto	Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs.	CANDAR	2016	DBLP DOI BibTeX RDF
19	Riad S. Wahby, Max Howald, Siddharth Garg, Abhi Shelat, Michael Walfish	Verifiable ASICs.	IEEE Symposium on Security and Privacy	2016	DBLP DOI BibTeX RDF
19	Andreas Hartel	Implementation and characterization of mixed-signal neuromorphic ASICs.		2016	RDF
19	Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh, Naoya Torii	A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs.	J. Cryptogr. Eng.	2015	DBLP DOI BibTeX RDF
19	Riad S. Wahby, Max Howald, Siddharth Garg, Abhi Shelat, Michael Walfish	Verifiable ASICs.	IACR Cryptol. ePrint Arch.	2015	DBLP BibTeX RDF
19	Zoya Dyka, Christian Wittke, Peter Langendörfer	Clockwise Randomization of the Observable Behaviour of Crypto ASICs to Counter Side Channel Attacks.	DSD	2015	DBLP DOI BibTeX RDF
19	Natale Demaria	Recent ASICs developments in 65nm CMOS technology for high energy physics experiments.	ICECS	2015	DBLP DOI BibTeX RDF
19	Mahdi Ahangarianabhari, Giuseppe Bertuccio, Stefano Caccia, Marco Grassi, Daniele Macera, Piero Malcovati	From StarX32 to VEGA: Low-power and low-noise mixed-signal ASICs for X-ray detectors in space and medical applications.	ICECS	2015	DBLP DOI BibTeX RDF
19	Macarena C. Martínez-Rodríguez, Piedad Brox, Erica Tena, Antonio J. Acosta 0001, Iluminada Baturone	Programmable ASICs for model predictive control.	ICIT	2015	DBLP DOI BibTeX RDF
19	Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula	Dynamic and leakage power reduction of ASICs using configurable threshold logic gates.	CICC	2015	DBLP DOI BibTeX RDF
19	Khaled A. Helal, Sameh Attia, Tawfik Ismail, Hassan Mostafa	Comparative review of NoCs in the context of ASICs and FPGAs.	ISCAS	2015	DBLP DOI BibTeX RDF
19	Milos Krstic	Reducing Power Consumption in Fault Tolerant ASICs.	GI-Jahrestagung	2015	DBLP BibTeX RDF
19	Marvin Freier	Indikatoren-basierte Entwurfsraumexploration für Sensor-ASICs in automobilen Applikationen.		2015	RDF
19	Bishnu Prasad Das, Hidetoshi Onodera	Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
19	Michitarou Yabuuchi, Ryo Kishida, Kazutoshi Kobayashi	Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2014	DBLP DOI BibTeX RDF
19	Miroslaw Zoladz, Piotr Kmon, Jacek Rauza, Pawel Grybos, Tomasz Blasiak	Multichannel neural recording system based on family ASICs processed in submicron technology.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
19	Piotr Maj	Mismatch effects and their correction in large area ASICs.	DDECS	2014	DBLP DOI BibTeX RDF
19	Piotr Otfinowski, Pawel Grybos, Robert Szczygiel, Piotr Maj	ADCs in deep submicron technologies for ASICs of pixel architecture.	DDECS	2014	DBLP DOI BibTeX RDF
19	Sabrina Titri, Cherif Larbes, Kamal Youcef-Toumi	Rapid prototyping of PVS into FPGA: From model based design to FPGA/ASICs implementation.	IDT	2014	DBLP DOI BibTeX RDF
19	Martin L. Schmatz, Rik Jongerius, Gero Dittmann, Andreea Anghel, Ton Engbersen, Jan van Lunteren, Peter Buchmann	Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation.	ICASSP	2014	DBLP DOI BibTeX RDF
19	Ernesto Sánchez 0001, Luca Sterpone, Anees Ullah	Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs.	FPL	2014	DBLP DOI BibTeX RDF
19	Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti 0001	ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs.	VLSID	2014	DBLP DOI BibTeX RDF
19	Riccardo Quaglia	A family of readout ASICs for X and γ-rays spectroscopy.		2014	RDF
19	Mahdi Ahangarianabhari	Low-Noise, Low-Power Front-End ASICs for High-Resolution X-ray Spectroscopy and Imaging in Space with Silicon Drift Detectors.		2014	RDF
19	Colin Boyd, Cas Cremers, Michèle Feltz, Kenneth G. Paterson, Bertram Poettering, Douglas Stebila	ASICS: Authenticated Key Exchange Security Incorporating Certification Systems.	IACR Cryptol. ePrint Arch.	2013	DBLP BibTeX RDF