Search results for "DRAMs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Fen Ge, Jia Zhan, Yuan Xie 0001, Vijaykrishnan Narayanan	Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.	ISQED	2015	DBLP DOI BibTeX RDF
21	Chi-Chun Yang, Jin-Fu Li 0001, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou	A hybrid built-in self-test scheme for DRAMs.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
21	Matthias Jung 0001, Christian Weis, Norbert Wehn, MohammadSadegh Sadri, Luca Benini	Optimized active and power-down mode refresh control in 3D-DRAMs.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
21	Karthik Chandrasekar 0001, Sven Goossens, Christian Weis, Martijn Koedam, Benny Akesson, Norbert Wehn, Kees Goossens	Exploiting expendable process-margins in DRAMs for run-time performance optimization.	DATE	2014	DBLP DOI BibTeX RDF
21	Yun-Chao You, Chi-Chun Yang, Jin-Fu Li 0001, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu	BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.	ATS	2014	DBLP DOI BibTeX RDF
21	Majid Jalalifar, Gyung-Su Byun	An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs.	ISQED	2014	DBLP DOI BibTeX RDF
21	Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou	Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs.	DTIS	2014	DBLP DOI BibTeX RDF
21	Aadithya V. Karthik, Alper Demir 0001, Sriramkumar Venugopalan, Jaijeet S. Roychowdhury	Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
21	Karthik Chandrasekar 0001, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens	System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.	DATE	2013	DBLP DOI BibTeX RDF
21	Bibhas Ghoshal, Chittaranjan Mandal 0002, Indranil Sengupta 0001	Re-using Refresh for Self-Testing DRAMs.	ISED	2013	DBLP DOI BibTeX RDF
21	Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu	A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.	VTS	2013	DBLP DOI BibTeX RDF
21	Chih-Sheng Hou, Jin-Fu Li 0001, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu	An FPGA-based test platform for analyzing data retention time distribution of DRAMs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
21	Su Myat Min, Haris Javaid, Sri Parameswaran	XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs.	DAC	2013	DBLP DOI BibTeX RDF
21	Karthik Chandrasekar 0001, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens	Towards variation-aware system-level power estimation of DRAMs: an empirical approach.	DAC	2013	DBLP DOI BibTeX RDF
21	Mark Gottscho, Abde Ali Kagalwalla, Puneet Gupta 0001	Power Variability in Contemporary DRAMs.	IEEE Embed. Syst. Lett.	2012	DBLP DOI BibTeX RDF
21	Hao-Yu Yang, Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Shih-Chin Lin	Testing Methodology of Embedded DRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
21	Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen	Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.	ICCAD	2012	DBLP DOI BibTeX RDF
21	Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang	SECRET: Selective error correction for refresh energy reduction in DRAMs.	ICCD	2012	DBLP DOI BibTeX RDF
21	Zoran Jaksic, Ramon Canal	Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs.	ICCD	2012	DBLP DOI BibTeX RDF
21	Rei-Fu Huang, Hao-Yu Yang, Mango Chia-Tso Chao, Shih-Chin Lin	Alternate hammering test for application-specific DRAMs and an industrial case study.	DAC	2012	DBLP DOI BibTeX RDF
21	Jong-Pil Son, Jin Ho Kim, Woo Song Ahn, Seung Uk Han, Satoru Yamada, Byung-Sick Moon, Churoo Park, Hong-Sun Hwang, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Soo-Won Kim	An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
21	Jun-Yong Song, Oh-Kyong Kwon	Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
21	Jun-Yong Song, Oh-Kyong Kwon	Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18-µm CMOS Technology.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
21	Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale	Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs.	PACT	2011	DBLP DOI BibTeX RDF
21	Christian Weis, Norbert Wehn, Igor Loi, Luca Benini	Design space exploration for 3D-stacked DRAMs.	DATE	2011	DBLP DOI BibTeX RDF
21	Gabriel H. Loh	A register-file approach for row buffer caches in die-stacked DRAMs.	MICRO	2011	DBLP DOI BibTeX RDF
21	Jinyeong Moon, Hye-young Lee	A dual-loop delay locked loop with multi digital delay lines for GHz DRAMs.	ISCAS	2011	DBLP DOI BibTeX RDF
21	Madalin Neagu, Liviu Miclea, Joan Figueras	Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies.	IOLTS	2011	DBLP DOI BibTeX RDF
21	Ulf Lotzmann, Ruth Meyer	DRAMS - A Declarative Rule-Based Agent Modelling System.	ECMS	2011	DBLP DOI BibTeX RDF
21	Aadithya V. Karthik, Sriramkumar Venugopalan, Alper Demir 0001, Jaijeet S. Roychowdhury	MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs.	DAC	2011	DBLP DOI BibTeX RDF
21	Ajay N. Bhoj, Niraj K. Jha	Gated-diode FinFET DRAMs: Device and circuit design-considerations.	ACM J. Emerg. Technol. Comput. Syst.	2010	DBLP DOI BibTeX RDF
21	Peter J. Klim, John Barth 0001, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer	A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
21	Jung Ho Ahn, Jacob Leverich, Robert S. Schreiber, Norman P. Jouppi	Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs.	IEEE Comput. Archit. Lett.	2009	DBLP DOI BibTeX RDF
21	Marco Facchini, Trevor E. Carlson, Anselme Vignon, Martin Palkovic, Francky Catthoor, Wim Dehaene, Luca Benini, Paul Marchal	System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.	DATE	2009	DBLP DOI BibTeX RDF
21	Tatsuya Matano, Koji Sato, Kiyoshi Nakai, Isamu Asano	A novel on-chip voltage generator for low voltage DRAMs and PRAMs.	CICC	2009	DBLP DOI BibTeX RDF
21	Ajay N. Bhoj, Niraj K. Jha	Pragmatic design of gated-diode FinFET DRAMs.	ICCD	2009	DBLP DOI BibTeX RDF
21	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks	Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.	IEEE Micro	2008	DBLP DOI BibTeX RDF	caches, process variation, variability, dynamic memory
21	O-Sam Kwon, Yong-Jin Kwon, Ho-Jun Song, Kyeong-Sik Min	Sense amplifier driving scheme with adaptive delay line for reducing peak current and driving time variations in deep-sub-micron DRAMs.	IEICE Electron. Express	2008	DBLP DOI BibTeX RDF
21	Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen	Testing Methodology of Embedded DRAMs.	ITC	2008	DBLP DOI BibTeX RDF
21	Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georg Mueller	Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs.	ITC	2008	DBLP DOI BibTeX RDF
21	Elena Atanassova, Albena Paskaleva	Challenges of Ta2O5 as high-k dielectric for nanoscale DRAMs.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
21	Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Sultan M. Al-Harbi	Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
21	Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini	Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
21	Ozcan Ozturk 0001, Mahmut T. Kandemir	Data Replication in Banked DRAMs for Reducing Energy Consumption.	ISQED	2006	DBLP DOI BibTeX RDF
21	Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino	Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs.	PATMOS	2005	DBLP DOI BibTeX RDF
21	Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van de Goor	Framework for Fault Analysis and Test Generation in DRAMs.	DATE	2005	DBLP DOI BibTeX RDF
21	Philipp Öhler, Sybille Hellebrand	Low power embedded DRAMs with high quality error correcting capabilities.	ETS	2005	DBLP DOI BibTeX RDF
21	Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya	A programmable built-in self-test for embedded DRAMs.	MTDT	2005	DBLP DOI BibTeX RDF
21	Ozcan Ozturk 0001, Mahmut T. Kandemir	Integer linear programming based energy optimization for banked DRAMs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low-power, data compression, DRAM, ILP, data migration, memory banking
21	Jae-Yoon Sim, Kee-Won Kwon, Ki-Chul Chun	Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
21	Zemo Yang, Samiha Mourad	Crosstalk induced fault analysis in DRAMs.	SoCC	2004	DBLP DOI BibTeX RDF
21	Seong-Ik Cho, Jung-Hwan Lee, Hong-June Park, Gyu-Ho Lim, Young-Hee Kim	Two-phase boosted voltage generator for low-voltage DRAMs.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
21	Zaid Al-Ars, Ad J. van de Goor	Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	dynamic faulty behavior, functional fault models, defect simulation, spot defects, Embedded DRAM, fault primitives
21	Michael W. Ruprecht, Guenther Benstetter, Douglas B. Hunt	A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
21	Coskun Mermer, Donglok Kim, Stefan G. Berg, Robert J. Gove, Yongmin Kim 0001	Use of embedded DRAMs in video and image computing.	J. Syst. Archit.	2003	DBLP DOI BibTeX RDF
21	Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	VL-CDRAM: variable line sized cached DRAMs.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	CDRAM, VL-CDRAM, variable line, energy
21	Wenjing Zhang, Jonathan Eskritt, Graham A. Jullien, Vassil S. Dimitrov	A 2-D LNS FIR Filter with a Programmable Second Base Using DRAMs.	ESTIMedia	2003	DBLP BibTeX RDF
21	Jae-Kyung Wee, Kyeong-Sik Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, Jong-Doo Joo, Jin-Yong Chung	A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
21	Elena Atanassova, Albena Paskaleva	Breakdown fields and conduction mechanisms in thin Ta2O5 layers on Si for high density DRAMs.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
21	Guenther Benstetter, Michael W. Ruprecht, Douglas B. Hunt	A review of ULSI failure analysis techniques for DRAMs 1. Defect localization and verification.	Microelectron. Reliab.	2002	DBLP DOI BibTeX RDF
21	Pierre C. Fazan, Serguei Okhonin, Mikhail Nagoga, Jean-Michel Sallese	A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs.	CICC	2002	DBLP DOI BibTeX RDF
21	Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya	A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
21	Kyeong-Sik Min, Jin-Yong Chung	A fast pump-down VBB generator for sub-1.5-V DRAMs.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
21	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	High-Performance DRAMs in Workstation Environments.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling
21	Zaid Al-Ars, Ad J. van de Goor	Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs.	DATE	2001	DBLP DOI BibTeX RDF
21	Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter	Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs.	ITC	2001	DBLP DOI BibTeX RDF
21	Eric A. Nelson, Jeffrey H. Dreibelbis, Roderick McConnell	Test and repair of large embedded DRAMs. 2.	ITC	2001	DBLP DOI BibTeX RDF
21	Roderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey H. Dreibelbis	Test and repair of large embedded DRAMs. I.	ITC	2001	DBLP DOI BibTeX RDF
21	Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada	Test cost reduction by at-speed BISR for embedded DRAMs.	ITC	2001	DBLP DOI BibTeX RDF
21	Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki	A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
21	Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman	A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
21	Hak-soo Yu, Songjun Lee, Jacob A. Abraham	An Adder Using Charge Sharing and its Application in DRAMs.	ICCD	2000	DBLP DOI BibTeX RDF
21	Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka	A built-in self-repair analyzer (CRESTA) for embedded DRAMs.	ITC	2000	DBLP DOI BibTeX RDF
21	Dong-Sun Min, Dietrich W. Langer	Multiple twisted dataline techniques for multigigabit DRAMs.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
21	Yervant Zorian	Focus on DRAMs.	IEEE Des. Test Comput.	1999	DBLP BibTeX RDF
21	Gershom Birk, Duncan G. Elliott, Bruce F. Cockburn	A Comparative Simulation Study of Four Multilevel DRAMs.	MTDT	1999	DBLP DOI BibTeX RDF
21	Dong-Sun Min, Dietrich W. Langer	Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs.	CICC	1999	DBLP DOI BibTeX RDF
21	Chung-Yu Wu, Yu-Yee Liow	A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
21	Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu	Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention.	DFT	1999	DBLP DOI BibTeX RDF
21	Frank W. Angelotti	SCITT: Bringing DRAMs Into the Test Fold.	ITC	1999	DBLP DOI BibTeX RDF
21	Jörg E. Vollrath, Markus Huebl, Ernst Stahl	Power Analysis of DRAMs.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
21	Hoi-Jun Yoo	A study of pipeline architectures for high-speed synchronous DRAMs.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
21	Kyu-Chan Lee, Changhyun Kim, Dong-Ryul Ryu, Jai-Hoon Sim, Sang-Bo Lee, Byung-Sik Moon, Keum-Yong Kim, Nam-Jong Kim, Seung-Moon Yoo, Hongil Yoon, Jei-Hwan Yoo, Soo-In Cho	Low-voltage, high-speed circuit designs for gigabit DRAMs.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
21	C. S. Murthy, M. Gall	Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
21	Jörg E. Vollrath	Cell Signal Measurement for High-Density DRAMs.	ITC	1997	DBLP DOI BibTeX RDF
21	Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki	Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
21	Emil Gizdarski	Built-in self-test for folded bit-line Mbit DRAMs.	Integr.	1996	DBLP DOI BibTeX RDF
21	Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto	Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
21	Marco Winzker, Peter Pirsch, Jochen Reimers	Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs.	ISCAS	1995	DBLP DOI BibTeX RDF
21	Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima	A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
21	Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa	Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
21	Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki	An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
21	James A. Gasbarro	Testing High Speed Drams.	ITC	1994	DBLP DOI BibTeX RDF
21	Wha-Joon Lee	Testing Issues on High Speed Synchronous DRAMs.	ITC	1994	DBLP DOI BibTeX RDF
21	James A. Gasbarro, Mark Horowitz	Techniques for Characterizing DRAMs With a 500-MHz Interface.	ITC	1994	DBLP DOI BibTeX RDF
21	Manoj Sachdev, Math Verstraelen	Development of Fault Model and Test Algorithms for Embedded DRAMs.	ITC	1993	DBLP DOI BibTeX RDF
21	Jochen Kölzer, Johann Otto	Electrical Characterization of Megabit DRAMs, Part 2: Internal Testing.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
21	Georg Antonin, Hans-Dieter Oberle, Jochen Kölzer	Electrical Characterization of Megabit DRAMs, Part 1: External Testing.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
21	H.-D. Oberle, Peter Muhmenthaler	Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIM.	ITC	1991	DBLP DOI BibTeX RDF
21	Yoshikazu Morooka, Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada	An Address Maskable Parallel Testing for Ultra High Density DRAMs.	ITC	1991	DBLP DOI BibTeX RDF