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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1856 occurrences of 951 keywords
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Results
Found 6443 publication records. Showing 6443 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
35 | Walter J. Kozacky, Tokunbo Ogunfunmi |
Efficient DSP implementation of an adaptive line enhancer based on the convex combination of two IIR filters. |
DSP |
2015 |
DBLP DOI BibTeX RDF |
|
35 | Andreas Karlsson, Joar Sohl, Dake Liu |
ePUMA: A processor architecture for future DSP. |
DSP |
2015 |
DBLP DOI BibTeX RDF |
|
35 | Ramin Vali, Johnny Wei-Hsun Kao |
Comparing DSP realizations of correlator and SVM receivers for chaos-based multi-user DS-SS. |
DSP |
2014 |
DBLP DOI BibTeX RDF |
|
35 | Mohammed Aziz, Said Boussakta |
Efficient Residue Reduction Algorithm using DSP Circular Buffer Registers. |
DSP |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Hagai Kirshner, Moshe Porat |
On Optimal Derivative DSP Operators for Sampled Data. |
DSP |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Matthias Norbert Balzer, Helmut Stripf |
Online data reduction with a DSP-FPGA multiprocessor system. |
DSP |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Monson H. Hayes, Joel R. Jackson |
Synchronous and asynchronous distributed DSP education. |
DSP |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Konstantinos Valasoulis, Dimitrios I. Fotiadis, Isaac E. Lagaris, Aristidis Likas |
Solving differential equations with neural networks: implementation on a DSP platform. |
DSP |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Romano Fantacci, Francesco Guidi, Filipppo Rastelli, Daniele Tarchi, Piero Tortoli |
DSP implementation of a neural network based blind multiuser receiver for DS-CDMA communication systems. |
DSP |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Yianni Attikiouzel, Ramachandran Chandrasekhar |
DSP in mammography. |
DSP |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Michalis D. Galanis, Arhanassios Papazacharias, Evangelos Zigouris |
A DSP course for real-time systems design and implementation based on the TMS320C6211 DSK. |
DSP |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Christophe Couturier, Kidiyo Kpalma, Joseph Ronsin |
DSP teleoperation for digital signal processing teaching and training via Internet. |
DSP |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Hong Yue, Zhiying Wang 0003, Kui Dai |
A Heterogeneous Embedded MPSoC for Multimedia Applications. |
HPCC |
2006 |
DBLP DOI BibTeX RDF |
Transport Triggered Architecture, DSP, Embedded Processor, Heterogeneous MPSoC |
34 | Andrew A. Lamb, William Thies, Saman P. Amarasinghe |
Linear analysis and optimization of stream programs. |
PLDI |
2003 |
DBLP DOI BibTeX RDF |
algebraic simplification, optimization, embedded, FFT, DSP, linear systems, stream programming, StreamIt |
33 | Juan A. Rico-Gallego, Juan Carlos Díaz Martín, Jesús M. Álvarez Llorente |
An MPI Implementation for Distributed Signal Processing. |
PVM/MPI |
2005 |
DBLP DOI BibTeX RDF |
DSP multicomputers, communication middleware, MPI, Digital signal processing, digital signal processors |
33 | Eisaku Ohbuchi, Hiroshi Hanaizumi, Lim Ah Hock |
Barcode Readers using the Camera Device in Mobile Phones. |
CW |
2004 |
DBLP DOI BibTeX RDF |
DSP (Digital Signal Processor), image processing, mobile phone, barcode |
33 | Rainer Leupers, Peter Marwedel |
Time-constrained code compaction for DSPs. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects |
33 | Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty |
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. |
SIGARCH Comput. Archit. News |
2013 |
DBLP DOI BibTeX RDF |
|
33 | Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty |
A Novel Reconfigurable Architecture of a DSP Processor for Efficient Mapping of DSP Functions using Field Programmable DSP Arrays. |
CoRR |
2013 |
DBLP BibTeX RDF |
|
33 | Yun Wu, Yong Zhao, Jianshi Li |
Research on the eXpressDSP-Compliant Algorithms. |
WKDD |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Anuja Jayraj Thakkar, Abdel Ejnioui |
Pipelining of double precision floating point division and square root operations. |
ACM Southeast Regional Conference |
2006 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, floating point, division, square root |
33 | Chia-Jui Hsu, Shuvra S. Bhattacharyya |
Software Synthesis from the Dataflow Interchange Format. |
SCOPES |
2005 |
DBLP DOI BibTeX RDF |
DIF, dataflow interchange format, software synthesis |
33 | Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama |
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Jiyang Kang, Jongbok Lee, Wonyong Sung |
A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation. |
J. VLSI Signal Process. |
2001 |
DBLP DOI BibTeX RDF |
code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis |
33 | Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee |
Synthesis of Embedded Software from Synchronous Dataflow Specifications. |
J. VLSI Signal Process. |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Hong-Shin Jun, Sun-Young Hwang |
Design of a pipelined datapath synthesis system for digital signal processing. |
IEEE Trans. Very Large Scale Integr. Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
32 | Andrew K. C. Kwan, Mohamed Helaoui, Slim Boumaiza, Michael R. Smith 0001, Fadhel M. Ghannouchi |
Wireless Communications Transmitter Performance Enhancement Using Advanced Signal Processing Algorithms Running in a Hybrid DSP/FPGA Platform. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Memoryless predistortion, Memory effects, Wireless transmitters, FPGA, Digital signal processing, DSP, Adaptive signal processing |
32 | Huaibin Shi, Mei Xie |
Realization of Fingerprint Identification on DSP. |
ISICA |
2009 |
DBLP DOI BibTeX RDF |
Automatically power switch, DSP, Fingerprint Identification |
32 | Xingming Zhang 0001, Yingshan Li, Zihao Pan, Wenjin Gu, Jianfu Chen |
A Biological Intelligent Access Control System Based on DSP and NIR Technology. |
ICIC (1) |
2008 |
DBLP DOI BibTeX RDF |
Phone Number Recognition, Face Recognition, Biometric, DSP, Fingerprint Recognition, Near Infrared |
32 | Yi-Hsuan Lee, Cheng Chen |
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
non-orthogonal architecture, code generation, DSP |
32 | Won So, Alexander G. Dean |
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP. |
CASES |
2006 |
DBLP DOI BibTeX RDF |
TI C6000, static profitability estimation, DSP, software pipelining, VLIW, iterative compilation, software thread integration |
32 | Thomas Richter, Gerhard P. Fettweis |
Interleaving on Parallel DSP Architectures. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
parallel architectures, DSP, interleaver, digital signal processor, algorithm mapping |
32 | Abhijit K. Deb, Axel Jantsch, Johnny Öberg |
System design for DSP applications in transaction level modeling paradigm. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
system design, DSP, grammar, transaction level modeling |
32 | HongXin Zhao, Hua Zhang, Wei Hong 0002 |
A Low Cost Microwave Data Link Utilizing Spread Spectrum and DSP Techniques. |
AINA |
2003 |
DBLP DOI BibTeX RDF |
Microwave data Link, MMIC, MAC controller, DSS, DSP |
32 | Kaijian Shi, Graig Godwin |
Hybrid hierarchical timing closure methodology for a high performance and low power DSP. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
chip integration, methodology, DSP, timing closure, placement optimization |
32 | Catherine H. Gebotys |
Security-Driven Exploration of Cryptography in DSP Cores. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
methodology, DSP, low energy, power analysis attack |
32 | Tor E. Jeremiassen |
A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
GSM-EFR Speech Codec, Performance, Cache, DSP |
32 | Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G. |
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Links to layout, Synthesis, DSP, Design Methodology, Physical Design, Deep sub-micron |
32 | Dusan Suvakovic, C. André T. Salama |
Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
low power, DSP, energy consumption, switching, multiplexer, low voltage, register, datapath |
31 | Osamu Shimada, Toshiyuki Nomura, Akihiko Sugiyama, Masahiro Serizawa |
Tradeoff Between Complexity and Memory Size in the 3GPP Enhanced aacPlus Decoder: Speed-Conscious and Memory-Conscious Decoders on a 16-Bit Fixed-Point DSP. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Audio codec, 3GPP enhanced aacPlus, DSP implementation, Memory size, Computational complexity, Tradeoff |
31 | Liqiang Wang, Yan Shi, Zukang Lu, Huilong Duan |
Miniaturized CMOS Imaging Module with Real-time DSP Technology for Endoscope and Laryngoscope Applications. |
J. Signal Process. Syst. |
2009 |
DBLP DOI BibTeX RDF |
CMOS imaging module, Blackfin DSP, Minimally invasive instruments, Real-time video processing, Miniature |
31 | Subash Chandar G., Mahesh Mehendale, R. Govindarajan |
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
embedded DSP systems, re-configurable architecture, code compression, energy reduction |
31 | Christian Panis, Ulrich Hirnschrott, Gunther Laure, Wolfgang Lazian, Jari Nurmi |
DSPxPlore: design space exploration methodology for an embedded DSP core. |
SAC |
2004 |
DBLP DOI BibTeX RDF |
DSPxPlore, embedded DSP, design space exploration |
31 | Qingfeng Zhuge, Zili Shao, Bin Xiao 0001, Edwin Hsing-Mean Sha |
Design space minimization with timing and code size optimization for embedded DSP. |
CODES+ISSS |
2003 |
DBLP DOI BibTeX RDF |
retiming, unfolding, code size reduction, DSP processors |
31 | Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha |
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. |
ICPP |
2002 |
DBLP DOI BibTeX RDF |
Scheduling, Software pipelining, Retiming, DSP processors |
31 | Piia Simonen, Ilkka Saastamoinen, Mika Kuulusa, Jari Nurmi |
Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
instruction memory, memory compression, ISA, DSP processor |
31 | Chanik Park, JaeWoong Chung, Soonhoi Ha |
Extended Synchronous Dataflow for Efficient DSP System Prototyping. |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
DSP system prototyping, Synchronous Dataflow |
31 | Anupam Basu, Rainer Leupers, Peter Marwedel |
Register-Constrained Address Computation in DSP Programs. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
DSP compiler, address computation, embedded processors |
31 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Extensions to Programmable DSP architectures for Reduced Power Dissipation. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Low Power Design, DSP Architecture |
31 | Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr. |
Realization of a nonlinear digital filter on a DSP array processor. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
nonlinear digital filter, third-order Volterra digital filtering algorithm, AT&T DSP-3 parallel processor, nonlinear communication channel equalization, 64-QAM signal constellation, performance evaluation, digital signal processing chips, time-skewing |
31 | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer |
Code density optimization for embedded DSP processors using data compression techniques. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
code density optimization, embedded DSP processors, code size minimization, text compression algorithms, TMS320C25 code generator, VLSI, data compression, data compression, skeleton, minimisation, dictionary, digital signal processing chips, VLSI systems, production cost |
31 | Ivan P. Radivojevic, Jayantha A. Herath |
Executing DSP Applications in a Fine-Grained Dataflow Environment. |
IEEE Trans. Software Eng. |
1991 |
DBLP DOI BibTeX RDF |
fine-grained dataflow architecture, numerically intensive digital signal processing, pipelined data-parallel algorithms, high-level language programming blocks, logical fine-grained decomposition, serial fraction, fine-grained general-purpose dataflow computing, parallel algorithms, parallel architectures, pipeline processing, precedence relations, computerised signal processing, DSP applications |
31 | Weijia Li, Youtao Zhang |
An efficient code update scheme for DSP applications in mobile embedded systems. |
LCTES |
2010 |
DBLP DOI BibTeX RDF |
context-aware script, context-unaware script, incremental coalescing general offset assignment (icgoa), incremental coalescing simple offset assignment (icsoa) |
31 | Chien-Wei Chen, Chuan-Yue Yang, Tei-Wei Kuo, Ming-Wei Chang |
Energy-Efficient Real-Time Co-scheduling of Multimedia DSP Jobs. |
SUTC |
2008 |
DBLP DOI BibTeX RDF |
Preemption Control, System-Wide Energy Efficiency, Real-Time Systems, Energy-Efficient Scheduling |
31 | Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi |
Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Zhi-Jian Sun, Xue-Mei Liu |
Application of Floating Point DSP and FPGA in Integration Navigation System. |
CSSE (4) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He 0001, Zhixiong Zhou, Ting Lei |
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
SoC system testing, genetic and evolutionary algorithm, design verification |
31 | Zhigang Yang, Wen Gao 0001, Yan Liu 0014, Debin Zhao |
DSP Implementation of Deblocking Filter for AVS. |
ICIP (6) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu |
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Quanxi Li, Jingsong He |
A Sophisticated Architecture for Evolutionary Multiobjective Optimization Utilizing High Performance DSP. |
ICES |
2007 |
DBLP DOI BibTeX RDF |
Evolvable Hardware, Digital Signal Processor, Evolutionary Multi-objective Optimization |
31 | Chung-Ching Shen, William Plishker, Shuvra S. Bhattacharyya, Neil Goldsman |
An Energy-Driven Design Methodology for Distributing DSP Applications across Wireless Sensor Networks. |
RTSS |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Daniel Baumgartner, Peter Rössler, Wilfried Kubinger |
Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms. |
CVPR |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Zhenmin Li, Taewhan Kim |
Address Code Optimization Exploiting Code Scheduling in DSP Applications. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Zohra Yermeche, Benny Sallberg, Nedelko Grbic, Ingvar Claesson |
Real-Time DSP Implementation of a Subband Beamforming Algorithm for Dual Microphone Speech Enhancement. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang |
Algorithms and DSP implementation of H.264/AVC. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis |
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis |
A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao |
DSP engine design for LINC wireless transmitter systems. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho |
Tuning a Protocol Processor Architecture Towards DSP Operations. |
SAMOS |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Guilin Chen, Mahmut T. Kandemir |
Optimizing Address Code Generation for Array-Intensive DSP Applications. |
CGO |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Jin Ok Kim, Jin-Soo Kim, Chin Hyun Chung, Jun Hwang |
On a Video Surveillance System with a DSP by the LDA Algorithm. |
Human.Society@Internet |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Mauro Olivieri, Mirko Scarana, Simone Smorfa |
Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique. |
ISCAS (5) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Jin Ok Kim, Jin-Soo Kim, Chin Hyun Chung |
Face Recognition by the LDA-Based Algorithm for a Video Surveillance System on DSP. |
ICCSA (1) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen |
A unified processor architecture for RISC & VLIW DSP. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
dual-core processor, register organization, variable-length instruction encoding, digital signal processor |
31 | Christian Panis, Ulrich Hirnschrott, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi |
FSEL - Selective Predicated Execution for a Configurable DSP Core. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Hani Rizk, Christos A. Papachristou, Francis G. Wolff |
Designing Self Test Programs for Embedded DSP Cores. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Byeong-Doo Choi, Min-Cheol Hwang, Ju-Hun Nam, Kyung-Hoon Lee, Sung-Jea Ko |
DSP Implementation of Real-time JPEG2000 Encoder Using Overlapped Block Transferring and Pipelined Processing. |
HiPC |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Zili Shao, Qingfeng Zhuge, Yi He 0001, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha |
Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Ronggang Qi, Zifeng Li, Qing Ma |
DSP Structure Optimizations - A Multirate Signal Flow Graph Approach. |
ISNN (2) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Pablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard P. Fettweis |
Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach. |
PARELEC |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Liang Han, Jie Chen 0012, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li |
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Ming-Yung Ko, Shuvra S. Bhattacharyya |
Partitioning for DSP Software Synthesis. |
SCOPES |
2003 |
DBLP DOI BibTeX RDF |
|
31 | John Y. Oliver, Venkatesh Akella |
Improving DSP Performance with a Small Amount of Field Programmable Logic. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen |
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Richard C. S. Morling, Izzet Kale, S. J. Morris, F. Custode |
DSP engine for ultra-low-power audio applications. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Yiyan Tang, Lie Qian, Yuke Wang, Yvon Savaria |
A new memory reference reduction method for FFT implementation on DSP. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Christian Panis, Raimund Leitner, Jari Nurmi |
Scaleable Shadow Stack for a Configurable DSP Concept. |
IWSOC |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Catherine H. Gebotys |
A network flow approach to memory bandwidth utilization in embedded DSP core processors. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Sungchul Yoon, Sangwook Kim, Jae Seuk Oh, Sungho Kang |
A New DSP Architecture for Correcting Errors Using Viterbi Algorithm. |
AISA |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Shailesh Ramamurthy, Sanjeev Madhavankutty, V. Meena, Rajesh Gupta 0004 |
JPEG-2000 on an advanced architecture, multiple execution unit DSP. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Huy Nguyen 0001, Abhijit Chatterjee |
Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Elana D. Granston, Eric Stotzer, Joe Zbiciak |
Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture. |
LCTES/OM |
2001 |
DBLP DOI BibTeX RDF |
WHILE loops, software pipelining, digital signal processors, VLIW architectures |
31 | Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss |
A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera |
A vector-pipeline DSP for low-rate videophones. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
31 | James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey D. Stroomer |
System Level Tools for DSP in FPGAs. |
FPL |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Olli Lehtoranta, Timo Hämäläinen 0001, Jukka Saarinen |
Parallel implementation of H.263 encoder for CIF-sized images on quad DSP system. |
ISCAS (2) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Eric Stotzer, Ernst L. Leiss |
Modulo Scheduling for the TMS320C6x VLIW DSP Architecture. |
Workshop on Languages, Compilers, and Tools for Embedded Systems |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim |
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Felipe Fernández, Ángel Sánchez |
Application of Multidimensional Retiming and Matroid Theory to DSP Algorithm Parallelization. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
31 | James R. Armstrong, Geoff Frank, F. Gail Gray |
Efficient approaches to testing VHDL DSP models. |
J. VLSI Signal Process. |
1996 |
DBLP DOI BibTeX RDF |
|
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