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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 6443 publication records. Showing 6443 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
35 | Walter J. Kozacky, Tokunbo Ogunfunmi |
Efficient DSP implementation of an adaptive line enhancer based on the convex combination of two IIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 2015 IEEE International Conference on Digital Signal Processing, DSP 2015, Singapore, July 21-24, 2015, pp. 1256-1260, 2015, IEEE, 978-1-4799-8058-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
35 | Andreas Karlsson, Joar Sohl, Dake Liu |
ePUMA: A processor architecture for future DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 2015 IEEE International Conference on Digital Signal Processing, DSP 2015, Singapore, July 21-24, 2015, pp. 253-257, 2015, IEEE, 978-1-4799-8058-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
35 | Ramin Vali, Johnny Wei-Hsun Kao |
Comparing DSP realizations of correlator and SVM receivers for chaos-based multi-user DS-SS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 19th International Conference on Digital Signal Processing, DSP 2014, Hong Kong, China, August 20-23, 2014, pp. 464-468, 2014, IEEE, 978-1-4799-4612-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
35 | Mohammed Aziz, Said Boussakta |
Efficient Residue Reduction Algorithm using DSP Circular Buffer Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 15th International Conference on Digital Signal Processing, DSP 2009, Cardiff, UK, July 1-4, 2007, pp. 312-314, 2007, IEEE, 1-4244-0881-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Hagai Kirshner, Moshe Porat |
On Optimal Derivative DSP Operators for Sampled Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 15th International Conference on Digital Signal Processing, DSP 2009, Cardiff, UK, July 1-4, 2007, pp. 443-446, 2007, IEEE, 1-4244-0881-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Matthias Norbert Balzer, Helmut Stripf |
Online data reduction with a DSP-FPGA multiprocessor system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 14th International Conference on Digital Signal Processing, DSP 2002, Santorini, Greece, July 1-3, 2002, pp. 819-822, 2002, IEEE, 0-7803-7503-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Monson H. Hayes, Joel R. Jackson |
Synchronous and asynchronous distributed DSP education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 14th International Conference on Digital Signal Processing, DSP 2002, Santorini, Greece, July 1-3, 2002, pp. 1247-1251, 2002, IEEE, 0-7803-7503-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Konstantinos Valasoulis, Dimitrios I. Fotiadis, Isaac E. Lagaris, Aristidis Likas |
Solving differential equations with neural networks: implementation on a DSP platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 14th International Conference on Digital Signal Processing, DSP 2002, Santorini, Greece, July 1-3, 2002, pp. 1265-1268, 2002, IEEE, 0-7803-7503-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Romano Fantacci, Francesco Guidi, Filipppo Rastelli, Daniele Tarchi, Piero Tortoli |
DSP implementation of a neural network based blind multiuser receiver for DS-CDMA communication systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 14th International Conference on Digital Signal Processing, DSP 2002, Santorini, Greece, July 1-3, 2002, pp. 823-826, 2002, IEEE, 0-7803-7503-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Yianni Attikiouzel, Ramachandran Chandrasekhar |
DSP in mammography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 14th International Conference on Digital Signal Processing, DSP 2002, Santorini, Greece, July 1-3, 2002, pp. 29-34, 2002, IEEE, 0-7803-7503-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Michalis D. Galanis, Arhanassios Papazacharias, Evangelos Zigouris |
A DSP course for real-time systems design and implementation based on the TMS320C6211 DSK. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 14th International Conference on Digital Signal Processing, DSP 2002, Santorini, Greece, July 1-3, 2002, pp. 853-856, 2002, IEEE, 0-7803-7503-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Christophe Couturier, Kidiyo Kpalma, Joseph Ronsin |
DSP teleoperation for digital signal processing teaching and training via Internet. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSP ![In: 14th International Conference on Digital Signal Processing, DSP 2002, Santorini, Greece, July 1-3, 2002, pp. 1253-1256, 2002, IEEE, 0-7803-7503-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Hong Yue, Zhiying Wang 0003, Kui Dai |
A Heterogeneous Embedded MPSoC for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, Second International Conference, HPCC 2006, Munich, Germany, September 13-15, 2006, Proceedings, pp. 591-600, 2006, Springer, 3-540-39368-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Transport Triggered Architecture, DSP, Embedded Processor, Heterogeneous MPSoC |
34 | Andrew A. Lamb, William Thies, Saman P. Amarasinghe |
Linear analysis and optimization of stream programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, San Diego, California, USA, June 9-11, 2003, pp. 12-25, 2003, ACM, 1-58113-662-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
algebraic simplification, optimization, embedded, FFT, DSP, linear systems, stream programming, StreamIt |
33 | Juan A. Rico-Gallego, Juan Carlos Díaz Martín, Jesús M. Álvarez Llorente |
An MPI Implementation for Distributed Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PVM/MPI ![In: Recent Advances in Parallel Virtual Machine and Message Passing Interface, 12th European PVM/MPI Users' Group Meeting, Sorrento, Italy, September 18-21, 2005, Proceedings, pp. 475-482, 2005, Springer, 3-540-29009-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DSP multicomputers, communication middleware, MPI, Digital signal processing, digital signal processors |
33 | Eisaku Ohbuchi, Hiroshi Hanaizumi, Lim Ah Hock |
Barcode Readers using the Camera Device in Mobile Phones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CW ![In: 3rd International Conference on Cyberworlds (CW 2004), 18-20 November 2004, Tokyo, Japan, pp. 260-265, 2004, IEEE Computer Society, 0-7695-2140-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DSP (Digital Signal Processor), image processing, mobile phone, barcode |
33 | Rainer Leupers, Peter Marwedel |
Time-constrained code compaction for DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 54-59, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects |
33 | Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty |
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 41(2), pp. 1-8, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
33 | Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty |
A Novel Reconfigurable Architecture of a DSP Processor for Efficient Mapping of DSP Functions using Field Programmable DSP Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1306.0089, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
33 | Yun Wu, Yong Zhao, Jianshi Li |
Research on the eXpressDSP-Compliant Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WKDD ![In: Proceedings of the International Workshop on Knowledge Discovery and Data Mining, WKDD 2008, Adelaide, Australia, 23-24 January 2008, pp. 375-378, 2008, IEEE Computer Society, 0-7695-3090-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Anuja Jayraj Thakkar, Abdel Ejnioui |
Pipelining of double precision floating point division and square root operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 44st Annual Southeast Regional Conference, 2006, Melbourne, Florida, USA, March 10-12, 2006, pp. 488-493, 2006, ACM, 1-59593-315-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, floating point, division, square root |
33 | Chia-Jui Hsu, Shuvra S. Bhattacharyya |
Software Synthesis from the Dataflow Interchange Format. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29 - October 1, 2005, pp. 37-49, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DIF, dataflow interchange format, software synthesis |
33 | Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama |
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11), pp. 1319-1328, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Jiyang Kang, Jongbok Lee, Wonyong Sung |
A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 27(3), pp. 297-312, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis |
33 | Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee |
Synthesis of Embedded Software from Synchronous Dataflow Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 21(2), pp. 151-166, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Hong-Shin Jun, Sun-Young Hwang |
Design of a pipelined datapath synthesis system for digital signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(3), pp. 292-303, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
32 | Andrew K. C. Kwan, Mohamed Helaoui, Slim Boumaiza, Michael R. Smith 0001, Fadhel M. Ghannouchi |
Wireless Communications Transmitter Performance Enhancement Using Advanced Signal Processing Algorithms Running in a Hybrid DSP/FPGA Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(2-3), pp. 187-198, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Memoryless predistortion, Memory effects, Wireless transmitters, FPGA, Digital signal processing, DSP, Adaptive signal processing |
32 | Huaibin Shi, Mei Xie |
Realization of Fingerprint Identification on DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISICA ![In: Advances in Computation and Intelligence, 4th International Symposium, ISICA 2009, Huangshi, China, Ocotober 23-25, 2009, Proceedings, pp. 525-532, 2009, Springer, 978-3-642-04842-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Automatically power switch, DSP, Fingerprint Identification |
32 | Xingming Zhang 0001, Yingshan Li, Zihao Pan, Wenjin Gu, Jianfu Chen |
A Biological Intelligent Access Control System Based on DSP and NIR Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (1) ![In: Advanced Intelligent Computing Theories and Applications. With Aspects of Theoretical and Methodological Issues, 4th International Conference on Intelligent Computing, ICIC 2008, Shanghai, China, September 15-18, 2008, Proceedings, pp. 55-62, 2008, Springer, 978-3-540-87440-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Phone Number Recognition, Face Recognition, Biometric, DSP, Fingerprint Recognition, Near Infrared |
32 | Yi-Hsuan Lee, Cheng Chen |
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(3), pp. 281-296, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-orthogonal architecture, code generation, DSP |
32 | Won So, Alexander G. Dean |
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 13-23, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
TI C6000, static profitability estimation, DSP, software pipelining, VLIW, iterative compilation, software thread integration |
32 | Thomas Richter, Gerhard P. Fettweis |
Interleaving on Parallel DSP Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 39(1-2), pp. 161-173, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
parallel architectures, DSP, interleaver, digital signal processor, algorithm mapping |
32 | Abhijit K. Deb, Axel Jantsch, Johnny Öberg |
System design for DSP applications in transaction level modeling paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 466-471, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
system design, DSP, grammar, transaction level modeling |
32 | HongXin Zhao, Hua Zhang, Wei Hong 0002 |
A Low Cost Microwave Data Link Utilizing Spread Spectrum and DSP Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 17th International Conference on Advanced Information Networking and Applications (AINA'03), March 27-29, 2003, Xi'an, China, pp. 543-546, 2003, IEEE Computer Society, 0-7695-1906-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Microwave data Link, MMIC, MAC controller, DSS, DSP |
32 | Kaijian Shi, Graig Godwin |
Hybrid hierarchical timing closure methodology for a high performance and low power DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 850-855, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
chip integration, methodology, DSP, timing closure, placement optimization |
32 | Catherine H. Gebotys |
Security-Driven Exploration of Cryptography in DSP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 80-85, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
methodology, DSP, low energy, power analysis attack |
32 | Tor E. Jeremiassen |
A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 138-145, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
GSM-EFR Speech Codec, Performance, Cache, DSP |
32 | Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G. |
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 340-347, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Links to layout, Synthesis, DSP, Design Methodology, Physical Design, Deep sub-micron |
32 | Dusan Suvakovic, C. André T. Salama |
Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 26-29, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, DSP, energy consumption, switching, multiplexer, low voltage, register, datapath |
31 | Osamu Shimada, Toshiyuki Nomura, Akihiko Sugiyama, Masahiro Serizawa |
Tradeoff Between Complexity and Memory Size in the 3GPP Enhanced aacPlus Decoder: Speed-Conscious and Memory-Conscious Decoders on a 16-Bit Fixed-Point DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(3), pp. 297-303, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Audio codec, 3GPP enhanced aacPlus, DSP implementation, Memory size, Computational complexity, Tradeoff |
31 | Liqiang Wang, Yan Shi, Zukang Lu, Huilong Duan |
Miniaturized CMOS Imaging Module with Real-time DSP Technology for Endoscope and Laryngoscope Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 54(1-3), pp. 7-13, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS imaging module, Blackfin DSP, Minimally invasive instruments, Real-time video processing, Miniature |
31 | Subash Chandar G., Mahesh Mehendale, R. Govindarajan |
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 44(3), pp. 245-267, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
embedded DSP systems, re-configurable architecture, code compression, energy reduction |
31 | Christian Panis, Ulrich Hirnschrott, Gunther Laure, Wolfgang Lazian, Jari Nurmi |
DSPxPlore: design space exploration methodology for an embedded DSP core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), Nicosia, Cyprus, March 14-17, 2004, pp. 876-883, 2004, ACM, 1-58113-812-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DSPxPlore, embedded DSP, design space exploration |
31 | Qingfeng Zhuge, Zili Shao, Bin Xiao 0001, Edwin Hsing-Mean Sha |
Design space minimization with timing and code size optimization for embedded DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 144-149, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
retiming, unfolding, code size reduction, DSP processors |
31 | Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha |
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 31st International Conference on Parallel Processing (ICPP 2002), 20-23 August 2002, Vancouver, BC, Canada, pp. 613-620, 2002, IEEE Computer Society, 0-7695-1677-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Scheduling, Software pipelining, Retiming, DSP processors |
31 | Piia Simonen, Ilkka Saastamoinen, Mika Kuulusa, Jari Nurmi |
Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 477-479, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
instruction memory, memory compression, ISA, DSP processor |
31 | Chanik Park, JaeWoong Chung, Soonhoi Ha |
Extended Synchronous Dataflow for Efficient DSP System Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 196-, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
DSP system prototyping, Synchronous Dataflow |
31 | Anupam Basu, Rainer Leupers, Peter Marwedel |
Register-Constrained Address Computation in DSP Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 929-930, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
DSP compiler, address computation, embedded processors |
31 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Extensions to Programmable DSP architectures for Reduced Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 37-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Low Power Design, DSP Architecture |
31 | Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr. |
Realization of a nonlinear digital filter on a DSP array processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 24-33, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
nonlinear digital filter, third-order Volterra digital filtering algorithm, AT&T DSP-3 parallel processor, nonlinear communication channel equalization, 64-QAM signal constellation, performance evaluation, digital signal processing chips, time-skewing |
31 | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer |
Code density optimization for embedded DSP processors using data compression techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 272-285, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
code density optimization, embedded DSP processors, code size minimization, text compression algorithms, TMS320C25 code generator, VLSI, data compression, data compression, skeleton, minimisation, dictionary, digital signal processing chips, VLSI systems, production cost |
31 | Ivan P. Radivojevic, Jayantha A. Herath |
Executing DSP Applications in a Fine-Grained Dataflow Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 17(10), pp. 1028-1041, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
fine-grained dataflow architecture, numerically intensive digital signal processing, pipelined data-parallel algorithms, high-level language programming blocks, logical fine-grained decomposition, serial fraction, fine-grained general-purpose dataflow computing, parallel algorithms, parallel architectures, pipeline processing, precedence relations, computerised signal processing, DSP applications |
31 | Weijia Li, Youtao Zhang |
An efficient code update scheme for DSP applications in mobile embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, LCTES 2010, Stockholm, Sweden, April 13-15, 2010, pp. 105-114, 2010, ACM, 978-1-60558-953-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
context-aware script, context-unaware script, incremental coalescing general offset assignment (icgoa), incremental coalescing simple offset assignment (icsoa) |
31 | Chien-Wei Chen, Chuan-Yue Yang, Tei-Wei Kuo, Ming-Wei Chang |
Energy-Efficient Real-Time Co-scheduling of Multimedia DSP Jobs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SUTC ![In: IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC 2008), 11-13 June 2008, Taichung, Taiwan, pp. 225-232, 2008, IEEE Computer Society, 978-0-7695-3158-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Preemption Control, System-Wide Energy Efficiency, Real-Time Systems, Energy-Efficient Scheduling |
31 | Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi |
Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 205-208, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Zhi-Jian Sun, Xue-Mei Liu |
Application of Floating Point DSP and FPGA in Integration Navigation System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (4) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 4: Embedded Programming / Database Technology / Neural Networks and Applications / Other Applications, December 12-14, 2008, Wuhan, China, pp. 58-61, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He 0001, Zhixiong Zhou, Ting Lei |
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 20-25, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SoC system testing, genetic and evolutionary algorithm, design verification |
31 | Zhigang Yang, Wen Gao 0001, Yan Liu 0014, Debin Zhao |
DSP Implementation of Deblocking Filter for AVS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (6) ![In: Proceedings of the International Conference on Image Processing, ICIP 2007, September 16-19, 2007, San Antonio, Texas, USA, pp. 205-208, 2007, IEEE, 978-1-4244-1436-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu |
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 110-111, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Quanxi Li, Jingsong He |
A Sophisticated Architecture for Evolutionary Multiobjective Optimization Utilizing High Performance DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 415-425, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Evolvable Hardware, Digital Signal Processor, Evolutionary Multi-objective Optimization |
31 | Chung-Ching Shen, William Plishker, Shuvra S. Bhattacharyya, Neil Goldsman |
An Energy-Driven Design Methodology for Distributing DSP Applications across Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 28th IEEE Real-Time Systems Symposium (RTSS 2007), 3-6 December 2007, Tucson, Arizona, USA, pp. 214-226, 2007, IEEE Computer Society, 0-7695-3062-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Daniel Baumgartner, Peter Rössler, Wilfried Kubinger |
Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 18-23 June 2007, Minneapolis, Minnesota, USA, 2007, IEEE Computer Society, 1-4244-1179-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Zhenmin Li, Taewhan Kim |
Address Code Optimization Exploiting Code Scheduling in DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1573-1576, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Zohra Yermeche, Benny Sallberg, Nedelko Grbic, Ingvar Claesson |
Real-Time DSP Implementation of a Subband Beamforming Algorithm for Dual Microphone Speech Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 353-356, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, Hsueh-Ming Hang |
Algorithms and DSP implementation of H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 742-749, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis |
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis |
A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao |
DSP engine design for LINC wireless transmitter systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho |
Tuning a Protocol Processor Architecture Towards DSP Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 132-141, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Guilin Chen, Mahmut T. Kandemir |
Optimizing Address Code Generation for Array-Intensive DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 20-23 March 2005, San Jose, CA, USA, pp. 141-152, 2005, IEEE Computer Society, 0-7695-2298-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Jin Ok Kim, Jin-Soo Kim, Chin Hyun Chung, Jun Hwang |
On a Video Surveillance System with a DSP by the LDA Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Human.Society@Internet ![In: Web and Communication Technologies and Internet-Related Social Issues - HSI 2005, 3rd International Conference on Human.Society@Internet, Tokyo, Japan, July 27-29, 2005, Proceedings, pp. 200-207, 2005, Springer, 3-540-27830-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Mauro Olivieri, Mirko Scarana, Simone Smorfa |
Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5266-5269, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Jin Ok Kim, Jin-Soo Kim, Chin Hyun Chung |
Face Recognition by the LDA-Based Algorithm for a Video Surveillance System on DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2005, International Conference, Singapore, May 9-12, 2005, Proceedings, Part I, pp. 638-646, 2005, Springer, 3-540-25860-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen |
A unified processor architecture for RISC & VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 50-55, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-core processor, register organization, variable-length instruction encoding, digital signal processor |
31 | Christian Panis, Ulrich Hirnschrott, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi |
FSEL - Selective Predicated Execution for a Configurable DSP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 317-320, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Hani Rizk, Christos A. Papachristou, Francis G. Wolff |
Designing Self Test Programs for Embedded DSP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 816-823, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Byeong-Doo Choi, Min-Cheol Hwang, Ju-Hun Nam, Kyung-Hoon Lee, Sung-Jea Ko |
DSP Implementation of Real-time JPEG2000 Encoder Using Overlapped Block Transferring and Pipelined Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2004, 11th International Conference, Bangalore, India, December 19-22, 2004, Proceedings, pp. 333-341, 2004, Springer, 3-540-24129-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Zili Shao, Qingfeng Zhuge, Yi He 0001, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha |
Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Ronggang Qi, Zifeng Li, Qing Ma |
DSP Structure Optimizations - A Multirate Signal Flow Graph Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2004, International Symposium on Neural Networks, Dalian, China, August 19-21, 2004, Proceedings, Part II, pp. 1007-1012, 2004, Springer, 3-540-22843-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Pablo Robelly, Gordon Cichon, Hendrik Seidel, Gerhard P. Fettweis |
Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 7-10 September 2004, Dresden, Germany, pp. 372-375, 2004, IEEE Computer Society, 0-7695-2080-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Liang Han, Jie Chen 0012, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li |
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 446-451, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Ming-Yung Ko, Shuvra S. Bhattacharyya |
Partitioning for DSP Software Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 344-358, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | John Y. Oliver, Venkatesh Akella |
Improving DSP Performance with a Small Amount of Field Programmable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 520-532, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen |
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 275-282, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Richard C. S. Morling, Izzet Kale, S. J. Morris, F. Custode |
DSP engine for ultra-low-power audio applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 357-360, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Yiyan Tang, Lie Qian, Yuke Wang, Yvon Savaria |
A new memory reference reduction method for FFT implementation on DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 496-499, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Christian Panis, Raimund Leitner, Jari Nurmi |
Scaleable Shadow Stack for a Configurable DSP Concept. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 222-227, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Catherine H. Gebotys |
A network flow approach to memory bandwidth utilization in embedded DSP core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(4), pp. 390-398, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Sungchul Yoon, Sangwook Kim, Jae Seuk Oh, Sungho Kang |
A New DSP Architecture for Correcting Errors Using Viterbi Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AISA ![In: Advanced Internet Services and Applications, First International Workshop, AISA 2002, Seoul, Korea, August 1-2, 2002, Proceedings, pp. 95-102, 2002, Springer, 3-540-43968-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Shailesh Ramamurthy, Sanjeev Madhavankutty, V. Meena, Rajesh Gupta 0004 |
JPEG-2000 on an advanced architecture, multiple execution unit DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 325-328, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Huy Nguyen 0001, Abhijit Chatterjee |
Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 61-, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Elana D. Granston, Eric Stotzer, Joe Zbiciak |
Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 138-144, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
WHILE loops, software pipelining, digital signal processors, VLIW architectures |
31 | Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss |
A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 212-219, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera |
A vector-pipeline DSP for low-rate videophones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 1-2, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey D. Stroomer |
System Level Tools for DSP in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 534-543, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Olli Lehtoranta, Timo Hämäläinen 0001, Jukka Saarinen |
Parallel implementation of H.263 encoder for CIF-sized images on quad DSP system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 209-212, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Eric Stotzer, Ernst L. Leiss |
Modulo Scheduling for the TMS320C6x VLIW DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Languages, Compilers, and Tools for Embedded Systems ![In: Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'99), Atlanta, Georgia, USA, May 5, 1999, pp. 28-34, 1999, ACM, 1-58113-136-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim |
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 49-, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Felipe Fernández, Ángel Sánchez |
Application of Multidimensional Retiming and Matroid Theory to DSP Algorithm Parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1511-1518, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | James R. Armstrong, Geoff Frank, F. Gail Gray |
Efficient approaches to testing VHDL DSP models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 14(2), pp. 221-234, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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