Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
37 | Qiang Ma 0002, Evangeline F. Y. Young |
Voltage island-driven floorplanning. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Eric Wong 0002, Sung Kyu Lim |
3D floorplanning with thermal vias. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh |
Microarchitectural floorplanning under performance and thermal tradeoff. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Azadeh Davoodi, Ankur Srivastava 0001 |
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Chung-Kuan Cheng, Jun Gu |
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang |
SoC test scheduling using the B-tree based floorplanning technique. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong |
CMP aware shuttle mask floorplanning. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Azadeh Davoodi, Ankur Srivastava 0001 |
Simultaneous floorplanning and resource binding: a probabilistic approach. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Chiu-Wing Sham, Evangeline F. Y. Young |
Congestion prediction in floorplanning. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani |
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong |
Bus-driven floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003 |
Robust fixed-outline floorplanning through evolutionary search. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Peter G. Sassone, Sung Kyu Lim |
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel |
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Saurabh N. Adya, Igor L. Markov |
Consistent placement of macro-blocks using floorplanning and standard-cell placement. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Hiroshi Miyashita, Yoji Kajitani |
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders [floorplanning]. |
APCCAS (2) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Hung-Ming Chen, Hai Zhou 0001, Fung Yu Young, D. F. Wong 0001, Hannah Honghua Yang, Naveed A. Sherwani |
Integrated floorplanning and interconnect planning. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Jason Cong, Tianming Kong, David Zhigang Pan |
Buffer block planning for interconnect-driven floorplanning. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh |
Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Kazuhiko Eguchi, Junya Suzuki, Satoshi Yamane, Kenji Oshima |
An Application of Genetic Algorithms to Floorplanning of VLSI. |
Rough Sets and Current Trends in Computing |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Amir H. Salek, Jinan Lou, Massoud Pedram |
A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Morteza Saheb Zamani, Graham R. Hellestrand |
A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. |
IWANN |
1995 |
DBLP DOI BibTeX RDF |
|
37 | Yung-Ming Fang, D. F. Wong 0001 |
Simultaneous functional-unit binding and floorplanning. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
37 | Jürgen Herrmann, Reiner Ackermann, Jörg Peters 0003, Detlef Reipa |
A Multistrategy Learning System and Its Integration into an Interactive Floorplanning Tool. |
ECML |
1994 |
DBLP DOI BibTeX RDF |
learning and problem solving, applications of machine learning, multistrategy learning |
37 | Sarma Sastry, Jen-I Pi |
Estimating the minimum of partitioning and floorplanning problems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
37 | Kevin McCullen, John Thorvaldson, David Demaris, Patrick Lampin |
A system for floorplanning with hierarchical placement and wiring. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
37 | Wayne Wei-Ming Dai |
Hierarchical placement and floorplanning in BEAR. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
37 | Sarma Sastry, Jen-I Pi |
An Investigation into Statistical Properties of Partitioning and Floorplanning Problems. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
36 | Chiu-Wing Sham, Evangeline F. Y. Young |
Area reduction by deadspace utilization on interconnect optimized floorplan. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
area reduction, Floorplanning |
36 | Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong |
An effective buffer planning algorithm for IP based fixed-outline SOC placement. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
buffer planning, very large scale integration (VLSI), floorplanning, fixed-outline |
36 | Chen-Wei Liu, Yao-Wen Chang |
Floorplan and power/ground network co-synthesis for fast design convergence. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
power/ground analysis, simulated annealing, floorplanning, IR drop, power integrity |
36 | Saurabh N. Adya, Igor L. Markov |
Combinatorial techniques for mixed-size placement. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
VLSI, placement, floorplanning |
36 | Hayward H. Chan, Saurabh N. Adya, Igor L. Markov |
Are floorplan representations important in digital design? |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
B*-tree, floorplanning, sequence pair, circuit layout |
36 | Mario R. Casu, Luca Macchiarulo |
Floorplan assisted data rate enhancement through wire pipelining: a real assessment. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
through-put, systems-on-chip, floorplanning, wire pipelining |
36 | Wonjoon Choi, Kia Bazargan |
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
floorplacement, global placement, area migration, Design, Algorithms, simulated annealing, Management, Floorplanning, network flow, hierarchical, Placement and routing |
32 | Cristiana Bolchini, Antonio Miele, Chiara Sandionigi |
Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems. |
FPL |
2011 |
DBLP DOI BibTeX RDF |
FPGA, floorplanning, partial reconfiguration |
32 | Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden |
An effective approach for large scale floorplanning. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
placement, floorplanning, legalization |
32 | Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou 0001 |
Optimizing wirelength and routability by searching alternative packings in floorplanning. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
wirelength reduction, Floorplanning |
32 | Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 0001 |
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining |
32 | Andrew B. Kahng |
Classical floorplanning harmful? |
ISPD |
2000 |
DBLP DOI BibTeX RDF |
VLSI floorplanning, block packing and layout, coarse placement, hierarchical design methodology |
32 | Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan 0002 |
CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Register and Module Assignment Design for low power, High level synthesis, Low power design, Floorplanning |
32 | John Marty Emmert, Dinesh Bhatia |
A Methodology for Fast FPGA Floorplanning. |
FPGA |
1999 |
DBLP DOI BibTeX RDF |
clustering, FPGA, placement, Tabu search, floorplanning |
30 | Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang 0003, Robert P. Dick, Li Shang |
TAPHS: thermal-aware unified physical-level and high-level synthesis. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong |
Optimal redistribution of white space for wire length minimization. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Xiaoping Tang, Martin D. F. Wong |
On handling arbitrary rectilinear shape constraint. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Johan Berntsson, Maolin Tang |
A Slicing Structure Representation for the Multi-layer Floorplan Layout Problem. |
EvoWorkshops |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Terry Tao Ye, Giovanni De Micheli |
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan |
PEPPER - a timing driven early floorplanner. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay |
27 | Jia Wang 0003, Hai Zhou 0001 |
Exploring adjacency in floorplanning. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Cheng-Yu Wang, Wai-Kei Mak |
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Renshen Wang, Chung-Kuan Cheng |
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
3-D integrated circuits, cuboidal dual, computational complexity |
27 | Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang |
Buffer/flip-flop block planning for power-integrity-driven floorplanning. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Pritha Banerjee 0001, Megha Sangtani, Susmita Sur-Kolay |
Floorplanning for Partial Reconfiguration in FPGAs. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Song Chen 0001, Takeshi Yoshimura |
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Chaomin Luo, Miguel F. Anjos, Anthony Vannelli |
Large-scale fixed-outline floorplanning design using convex optimization techniques. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Hushrav Mogal, Kia Bazargan |
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Qiang Ma 0002, Evangeline F. Y. Young |
Network flow-based power optimization under timing constraints in MSV-driven floorplanning. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Tsu-Shuan Chang, Manish Kumar, Teng-Sheng Moh, Chung-Li Tseng |
On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen |
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang |
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
27 | William H. Kao, Xiaopeng Dong |
Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCs. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang 0003, Ching-Hwa Cheng |
Noise-Aware Floorplanning for Fast Power Supply Network Design. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou 0001, Xianlong Hong |
Power Delivery Aware Floorplanning for Voltage Island Designs. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Pritha Banerjee 0001, Susmita Sur-Kolay, Arijit Bishnu |
Floorplanning in Modern FPGAs. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong |
Minimizing wire length in floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Mario R. Casu, Luca Macchiarulo |
Floorplanning With Wire Pipelining in Adaptive Communication Channels. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin |
Floorplanning Based on Particle Swarm Optimization. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang |
Simultaneous block and I/O buffer floorplanning for flip-chip design. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Love Singhal, Elaheh Bozorgzadeh |
Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang |
Voltage island aware floorplanning for power and timing optimization. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Sheqin Dong, Shuyi Zheng, Xianlong Hong |
Floorplanning for 2.5-D system integration using multi-layer-BSG structure. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Royce L. S. Ching, Evangeline F. Y. Young |
Shuttle mask floorplanning with modified alpha-restricted grid. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
multi-project wafers, reticle design |
27 | Jia Wang 0003, Hai Zhou 0001, Ping-Chih Wu |
Processing Rate Optimization by Sequential System Floorplanning. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma |
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Mario R. Casu, Luca Macchiarulo |
Throughput-driven floorplanning with wire pipelining. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yici Cai, Bin Liu 0007, Qiang Zhou 0001, Xianlong Hong |
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang |
Substrate noise modeling in early floorplanning of MS-SOCs. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Chung-Kuan Cheng |
Performance constrained floorplanning based on partial clustering [IC layout]. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh |
Floorplanning with clock tree estimation. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Chung-Kuan Cheng |
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Pawoumodom L. Takouda, Miguel F. Anjos, Anthony Vannelli |
Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga |
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani |
Abstraction and optimization of consistent floorplanning with pillar block constraints. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Zion Cien Shen, Chris C. N. Chu |
Accurate and efficient flow based congestion estimation in floorplanning. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
Temporal floorplanning using the T-tree formulation. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Yan Feng, Dinesh P. Mehta |
Constrained Floorplanning with Whitespace. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Saurabh N. Adya, Igor L. Markov |
Fixed-outline floorplanning: enabling hierarchical design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Jae-Gon Kim, Yeong-Dae Kim |
A linear programming-based algorithm for floorplanning in VLSI design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu |
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong |
Bus-Driven Floorplanning. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Malgorzata Chrzanowska-Jeske, Benyi Wang, Garrison W. Greenwood |
Floorplanning with performance-based clustering. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Hua Tang, Hui Zhang 0057, Alex Doboli |
Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
?? modulator, continuous-time filter, synthesis |
27 | Tianpei Zhang, Sachin S. Sapatnekar |
Optimized pin assignment for lower routing congestion after floorplanning phase. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo |
An interconnect optimized floorplanning of a scalar product macrocell. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura |
Floorplanning using a tree representation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
VLSI floorplanning with boundary constraints based on corner block list. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani |
Consistent floorplanning with super hierarchical constraints. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Christine L. Valenzuela, Pearl Y. Wang |
A Genetic Algorithm for VLSI Floorplanning. |
PPSN |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Frank Wolz, Reiner Kolla |
A New Floorplanning Method for FPGA Architectural Research. |
FPL |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh |
Fast Hierarchical Floorplanning with Congestion and Timing Control. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|