Search results for "MediaBench"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Yen-Jen Chang, Feipei Lai, Chia-Lin Yang	Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
12	Raksit Ashok, Saurabh Chheda, Csaba Andras Moritz	Coupling compiler-enabled and conventional memory accessing for energy efficiency.	ACM Trans. Comput. Syst.	2004	DBLP DOI BibTeX RDF	translation buffers, virtually addressed caches, Energy efficiency
12	Zhiyong Xu, Sohum Sohoni, Rui Min, Yiming Hu	An Analysis of Cache Performance of Multimedia Applications.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Multimedia applications, memory systems, cache performance, TLB
12	Greg Stitt, Frank Vahid, Shawn Nematbakhsh	Energy savings and speedups from partitioning critical software loops to hardware in embedded systems.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	FPGA, embedded systems, synthesis, platforms, speedup, low energy, Hardware/software partitioning
12	Chuanjun Zhang, Frank Vahid, Roman L. Lysecky	A self-tuning cache architecture for embedded systems.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning
12	Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang	Frequent value encoding for low power data buses.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
12	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.	DATE	2004	DBLP DOI BibTeX RDF
12	Chuanjun Zhang, Frank Vahid	Using a Victim Buffer in an Application-Specific Memory Hierarchy.	DATE	2004	DBLP DOI BibTeX RDF
12	Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan	MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor.	DATE	2004	DBLP DOI BibTeX RDF
12	Manish Verma, Lars Wehmeyer, Peter Marwedel	Cache-Aware Scratchpad Allocation Algorithm.	DATE	2004	DBLP DOI BibTeX RDF
12	Chuanjun Zhang, Frank Vahid, Roman L. Lysecky	A Self-Tuning Cache Architecture for Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF	on-chip CAD, embedded systems, low power, Cache, configurable, dynamic optimization, low energy, architecture tuning
12	Peter G. Sassone, D. Scott Wills	Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication.	MICRO	2004	DBLP DOI BibTeX RDF
12	Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz	Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
12	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal	Instruction buffering exploration for low energy VLIWs with instruction clusters.	ASP-DAC	2004	DBLP DOI BibTeX RDF
12	Arthur Stoutchinin, Guang R. Gao	If-Conversion in SSA Form.	Euro-Par	2004	DBLP DOI BibTeX RDF
12	Daniel Citron, Gadi Haber, Roy Levin	Reducing program image size by extracting frozen code and data.	EMSOFT	2004	DBLP DOI BibTeX RDF	feedback directed, frozen code, frozen data, image size
12	Kun Zhang 0006, Tao Zhang 0037, Santosh Pande	Binary translation to improve energy efficiency through post-pass register re-allocation.	EMSOFT	2004	DBLP DOI BibTeX RDF	cache power consumption, dead registers, register re-allocation, unused registers
12	Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan	Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
12	Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar	A way-halting cache for low-energy high-performance systems.	ISLPED	2004	DBLP DOI BibTeX RDF	low power techniques, cache design
12	Yau Chin, John Sheu, David M. Brooks	Evaluating Techniques for Exploiting Instruction Slack.	ICCD	2004	DBLP DOI BibTeX RDF
12	Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo	Multi-Profile Instruction Based Compression.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
12	Shalini Ghosh, Nur A. Touba, Sugato Basu	Reducing Power Consumption in Memory ECC Checkers.	ITC	2004	DBLP DOI BibTeX RDF
12	Hongkyu Kim, D. Scott Wills, Linda M. Wills	Empirical Analysis of Operand Usage and Transport in Multimedia Applications.	IWSOC	2004	DBLP DOI BibTeX RDF
12	Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark	Formal online methods for voltage/frequency control in multiple clock domain microprocessors.	ASPLOS	2004	DBLP DOI BibTeX RDF	MCD processors, formal methods, dynamic voltage/frequency scaling
12	Eduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo	Multi-profile based code compression.	DAC	2004	DBLP DOI BibTeX RDF	compression, code compression, code density
12	Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt	Introduction of local memory elements in instruction set extensions.	DAC	2004	DBLP DOI BibTeX RDF	ad-hoc functional units, genetic algorithm, ASIPs, coprocessors, instruction set extensions, customizable processors
12	Ann Gordon-Ross, Susan Cotterell, Frank Vahid	Tiny instruction caches for low power embedded systems.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	embedded systems., fixed program, low power, instruction cache, low energy, architecture tuning, Loop cache, filter cache
12	Xiaotong Zhuang, ChokSheak Lau, Santosh Pande	Storage assignment optimizations through variable coalescence for embedded processors.	LCTES	2003	DBLP DOI BibTeX RDF	GOA, variable coalescence, SOA, storage assignment
12	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor	Instruction Buffering Exploration for Low Energy Embedded Processors.	PATMOS	2003	DBLP DOI BibTeX RDF
12	Mahesh Mamidipaka, Nikil D. Dutt	On-chip Stack Based Memory Organization for Low Power Embedded Architectures.	DATE	2003	DBLP DOI BibTeX RDF
12	Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal	SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.	DATE	2003	DBLP DOI BibTeX RDF
12	Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon	A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.	DATE	2003	DBLP DOI BibTeX RDF	Data compression algorithms, system-level energy optimization, VLIW embedded processors
12	Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture.	DATE	2003	DBLP DOI BibTeX RDF	Embedded Systems, Low-Power, Design Space Exploration
12	Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin	WaveScalar.	MICRO	2003	DBLP DOI BibTeX RDF
12	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.	CGO	2003	DBLP DOI BibTeX RDF
12	Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers	Improving Offset Assignment through Simultaneous Variable Coalescing.	SCOPES	2003	DBLP DOI BibTeX RDF
12	Bernard Goossens	The Instruction Register File.	PaCT	2003	DBLP DOI BibTeX RDF
12	Marcio Buss, Tony Givargis, Nikil D. Dutt	Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores.	RTSS	2003	DBLP DOI BibTeX RDF
12	Montserrat Ros, Peter Sutton	Compiler optimization and ordering effects on VLIW code compression.	CASES	2003	DBLP DOI BibTeX RDF	compiler optimizations, VLIW, code compression
12	Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob	A control-theoretic approach to dynamic voltage scheduling.	CASES	2003	DBLP DOI BibTeX RDF	nqPID, low-power, dynamic voltage scaling, PID
12	Chuanjun Zhang, Frank Vahid	Cache Configuration Exploration on Prototyping Platforms.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF	embedded systems, low power, memory hierarchy, low energy, architecture tuning, Configurable cache, system-level exploration
12	Keith D. Cooper, Li Xu	Memory Redundancy Elimination to Improve Application Energy Efficiency.	LCPC	2003	DBLP DOI BibTeX RDF
12	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A Highly-Configurable Cache Architecture for Embedded Systems.	ISCA	2003	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, low energy, architecture tuning
12	Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, Eren Kursun	Global resource sharing for synthesis of control data flow graphs on FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	control data flow graph, FPGA, resource sharing
12	Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott	Dynamic frequency and voltage control for a multiple clock domain microarchitecture.	MICRO	2002	DBLP DOI BibTeX RDF
12	Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott	Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.	HPCA	2002	DBLP DOI BibTeX RDF	Off-Line Analysis Tool, Dynamic Reconfiguration Algorithm, Low Power, Dynamic Voltage and Frequency Scaling, Multiple Clock Domain
12	Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung	Code Compression by Register Operand Dependency.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	Dictionary-based compression, Code compression
12	Linda M. Wills, Tarek M. Taha, Lewis Benton Baumstark Jr., D. Scott Wills	Estimating Potential Parallelism for Platform Retargeting.	WCRE	2002	DBLP DOI BibTeX RDF
12	Zhiyuan Li 0001, Cheng Wang 0019, Rong Xu	Task Allocation for Distributed Multimedia Processing on Wirelessly Networked Handheld Devices.	IPDPS	2002	DBLP DOI BibTeX RDF
12	Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano	Datapath Merging and Interconnection Sharing for Reconfigurable Architectures.	ISSS	2002	DBLP DOI BibTeX RDF	high level and architectural synthesis, reconfigurable computing
12	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	An interleaved cache clustered VLIW processor.	ICS	2002	DBLP DOI BibTeX RDF	attraction buffers, modulo scheduling, VLIW processors, distributed cache, clustered microarchitectures
12	Esther Salamí, Jesús Corbal, Carlos Álvarez 0001, Mateo Valero	Cost effective memory disambiguation for multimedia codes.	CASES	2002	DBLP DOI BibTeX RDF	multimedia, VLIW, run-time analysis, time-to-market, memory disambiguation
12	Eren Kursun, Ankur Srivastava 0001, Seda Ogrenci Memik, Majid Sarrafzadeh	Early evaluation techniques for low power binding.	ISLPED	2002	DBLP DOI BibTeX RDF	metric evaluation, scheduling, low power design, resource binding
12	Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar	Exploring the Number of Register Windows in ASIP Synthesis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Regular language recognition, Processor and memory configuration, ASIP Synthesis, Context switch, Register windows
12	Raksit Ashok, Saurabh Chheda, Csaba Andras Moritz	Cool-Mem: combining statically speculative memory accessing with selective address translation for energy efficiency.	ASPLOS	2002	DBLP DOI BibTeX RDF
12	Darko Kirovski, Milenko Drinic, Miodrag Potkonjak	Enabling trusted software integrity.	ASPLOS	2002	DBLP DOI BibTeX RDF
12	Wen-Tsong Shiue, Sathishkumar Udayanarayanan, Chaitali Chakrabarti	Data memory design and exploration for low-power embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Data cache, search space pruning
12	Bjorn De Sutter, Bruno De Bus, Koenraad De Bosschere, Saumya K. Debray	Combining Global Code and Data Compaction.	LCTES/OM	2001	DBLP DOI BibTeX RDF
12	Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler	A design space evaluation of grid processor architectures.	MICRO	2001	DBLP DOI BibTeX RDF
12	Emmett Witchel, Samuel Larsen, C. Scott Ananian, Krste Asanovic	Direct addressed caches for reduced power consumption.	MICRO	2001	DBLP DOI BibTeX RDF
12	John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu	Enhancing loop buffering of media and telecommunications applications using low-overhead predication.	MICRO	2001	DBLP DOI BibTeX RDF
12	Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala	CARS: A New Code Generation Framework for Clustered ILP Processors.	HPCA	2001	DBLP DOI BibTeX RDF
12	Sohum Sohoni, Rui Min, Zhiyong Xu, Yiming Hu	A study of memory system performance of multimedia applications.	SIGMETRICS/Performance	2001	DBLP DOI BibTeX RDF
12	William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	Fast system-level exploration of memory architectures driven by energy-delay metrics.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
12	Mihai Budiu, Majd F. Sakr, Kip Walker, Seth Copen Goldstein	BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations.	Euro-Par	2000	DBLP DOI BibTeX RDF
12	Xianfeng Zhou, Margaret Martonosi	Augmenting Modern Superscalar Architectures with Configurable Extended Instructions.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF