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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 908 occurrences of 401 keywords
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Results
Found 1076 publication records. Showing 1076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
43 | Natalino G. Busá, Albert van der Werf, Marco Bekooij |
Scheduling Coarse-Grain Operations for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 47-54, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Morteza Biglari-Abhari, Kamran Eshraghian, Michael J. Liebelt |
Improving Binary Compatibility in VLIW Machines through Compiler Assisted Dynamic Rescheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1386-1393, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Catherine H. Gebotys, Robert J. Gebotys, S. Wiratunga |
Power minimization derived from architectural-usage of VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 308-311, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Rainer Leupers |
Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 105-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind |
Execution-Based Scheduling for VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings, pp. 1269-1280, 1999, Springer, 3-540-66443-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
INSTRUCTION-LEVEL PARALLELISM, SUPERSCALAR, BINARY TRANSLATION, DYNAMIC COMPILATION |
43 | Mladen Berekovic, Peter Pirsch, Johannes Kneip |
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 20(1-2), pp. 163-180, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | Esther Stümpel, Michael Thies, Uwe Kastens |
VLIW Compilation Techniques for Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 7th International Conference, CC'98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings, pp. 234-248, 1998, Springer, 3-540-64304-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
43 | Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papworth, Paul K. Rodman |
A VLIW Architecture for a Trace Scheduling Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 180-192, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
42 | Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster 0001 |
Reducing power while increasing performance with supercisc. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(3), pp. 658-686, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Low-power, synthesis, VLIW, predication, multicore architectures |
42 | Nan Wu 0003, Mei Wen, Ju Ren 0002, Yi He 0008, Chunyuan Zhang |
Register Allocation on Stream Processor with Local Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 545-551, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
local register file, spilling, register allocation, VLIW, stream processor |
42 | Catherine H. Gebotys |
Design of secure cryptography against the threat of power-attacks in DSP-embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(1), pp. 92-113, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VLIW |
42 | Catherine H. Gebotys, Robert J. Gebotys |
Optimized mapping of video applications to hardware-software for VLSI architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 41-48, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
integer optimization, video computations, video systems, optimized mapping, scheduling, VLSI, optimisation, VLSI architectures, video signal processing, VLIW processor |
42 | Manoj Franklin, Mark Smotherman |
A fill-unit approach to multiple instruction issue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 162-171, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
multiple operation issue, instruction-level parallelism, VLIW, superscalar |
39 | Vincenzo Catania, Maurizio Palesi, Davide Patti |
Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(2), pp. 11:1-11:33, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hyperblock formation, genetic algorithms, performances, statistical analysis, power, energy, design space exploration, multiobjective optimization, ILP, VLIW architectures |
39 | Wonchul Lee, Hyojin Choi, Wonyong Sung |
Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(3), pp. 289-302, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
variable block size motion estimation, H.264/AVC encoder, VLIW (very long instruction word), SIMD (single instruction multiple data) |
39 | Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Reducing dynamic and leakage energy in VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(1), pp. 1-28, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic energy, schedule slacks, compiler, VLIW architecture, leakage energy |
39 | Zili Shao, Bin Xiao 0001, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha |
Loop scheduling with timing and switching-activity minimization for VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 165-185, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction bus optimization, low-power optimization, compilers, software pipelining, VLIW, retiming, instruction scheduling, loops |
39 | Won So, Alexander G. Dean |
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 13-23, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
TI C6000, static profitability estimation, DSP, software pipelining, VLIW, iterative compilation, software thread integration |
39 | Rahul Nagpal, Y. N. Srikant |
Integrated temporal and spatial scheduling for extended operand clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 457-470, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
spatial scheduling, temporal scheduling, clustered VLIW processors |
39 | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Adapting instruction level parallelism for optimizing leakage in VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03). San Diego, California, USA, June 11-13, 2003, pp. 275-283, 2003, ACM, 1-58113-647-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units |
39 | Montserrat Ros, Peter Sutton |
Compiler optimization and ordering effects on VLIW code compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 95-103, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
compiler optimizations, VLIW, code compression |
39 | Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana |
Cluster assignment for high-performance embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(3), pp. 430-454, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Operation binding, clustered VLIW datapaths, embedded systems, partitioning, embedded processors |
39 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Loop fusion for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 112-119, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
clustered VLIW architectures, loop fusion |
39 | M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha |
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 2-7, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Trimaran, performance, design space exploration, VLIW, ASIP |
39 | David López 0001, Josep Llosa, Mateo Valero, Eduard Ayguadé |
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(10), pp. 1033-1051, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
numerical applications, performance/cost trade-off, instruction level parallelism, software pipelining, VLIW processors |
39 | Elana D. Granston, Eric Stotzer, Joe Zbiciak |
Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 138-144, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
WHILE loops, software pipelining, digital signal processors, VLIW architectures |
39 | Cagdas Akturan, Margarida F. Jacome |
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001, pp. 67-72, 2001, ACM, 1-58113-364-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors |
39 | Cristiana Bolchini, Fabio Salice |
A Software Methodology for Detecting Hardware Faults in VLIW Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 170-175, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Software code scheduling, VLIW processors, Hardware fault detection |
39 | Thomas M. Conte, Sumedh W. Sathaye |
Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(8), pp. 814-825, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
instruction-set encoding, list encoding, VLIW, Microarchitecture, processor architecture, instruction cache |
39 | Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye |
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 201-211, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures |
39 | Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia |
A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 4-13, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
LRU replacement, disk caching scheme, dynamic rescheduling, first-time page faults, high-overhead programs, low overhead object code compatibility, overhead-based replacement, page replacement policies, persistent rescheduled-page cache, run-time software rescheduling, simulations, cache storage, VLIW architectures, program executions, operating system support, program performance |
39 | Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park |
Scheduling of conditional branches using SSA form for superscalar/VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 344-351, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA |
39 | Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park |
Eliminating Conditional Branches for Enhancing Instruction Level Parallelism in VLIW Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 193-199, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Compiler, Instruction Level Parallelism, VLIW, Superscalar, Conditional Branches |
39 | Kemal Ebcioglu, Randy D. Groves, Ki-Chang Kim, Gabriel M. Silberman, Isaac Ziv |
VLIW Compilation Techniques in a Superscalar Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'94 Conference on Programming Language Design and Implementation (PLDI), Orlando, Florida, USA, June 20-24, 1994, pp. 36-48, 1994, ACM, 0-89791-662-X. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
profiling directed feedback, compiler optimizations, software pipelining, VLIW, superscalars, global scheduling, IBM RS/6000 |
39 | Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker |
Sentinel Scheduling for VLIW and Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 11(4), pp. 376-408, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor |
36 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch |
Design Space Exploration of Media Processors: A Parameterized Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007, pp. 41-49, 2007, IEEE, 1-4244-1058-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Michael Dupré, Nathalie Drach, Olivier Temam |
VHC: Quickly Building an Optimizer for Complex Embedded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 53-64, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Yangyang Pan, Tong Zhang 0002 |
Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 38-45, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Talal Bonny, Jörg Henkel |
LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 903-906, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
embedded systems, code compression, Huffman coding |
34 | Benoît Dupont de Dinechin |
Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2008 - Parallel Processing, 14th International Euro-Par Conference, Las Palmas de Gran Canaria, Spain, August 26-29, 2008, Proceedings, pp. 370-381, 2008, Springer, 978-3-540-85450-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Chun-Nan Liu, Jui Hong Hung, Tsung-Han Tsai 0001 |
Optimization techniques of AAC decoder on PACDSP VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1468-1471, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Meng Wang 0005, Zili Shao, Hui Liu 0006, Chun Jason Xue |
Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIPES ![In: Distributed Embedded Systems: Design, Middleware and Resources, IFIP 20th World Computer Congress, TC10 Working Conference on Distributed and Parallel Embedded Systems (DIPES 2008), September 7-10, 2008, Milano, Italy, pp. 111-120, 2008, Springer, 978-0-387-09660-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Hung-Chuan Lai, Shi-Jinn Horng, Yung-Yuan Chen |
An Online Control Flow Check for VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 256-264, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Yuan Xie 0001, Wayne H. Wolf, Haris Lekatsas |
Code Decompression Unit Design for VLIW Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 975-980, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Chang Hong Lin, Yuan Xie 0001, Wayne H. Wolf |
Code Compression for VLIW Embedded Systems Using a Self-Generating Table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(10), pp. 1160-1171, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Rahul Nagpal, Y. N. Srikant |
Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 405-417, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch |
Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2007, 20th International Conference, Zurich, Switzerland, March 12-15, 2007, Proceedings, pp. 254-267, 2007, Springer, 978-3-540-71267-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Min Li 0001, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor |
A Wavelet-FFT Based Efficient Sparse OFDMA Demodulator and Its Implementation on VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 7-12, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Meng Wang 0005, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha |
Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea, pp. 12-19, 2007, IEEE Computer Society, 0-7695-2975-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen |
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3506-3509, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Abhishek Pillai, Wei Zhang 0002, Laurence Tianruo Yang |
Exploring Functional Unit Design Space of VLIW Processors for Optimizing Both Performance and Energy Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA Workshops (1) ![In: 21st International Conference on Advanced Information Networking and Applications (AINA 2007), Workshops Proceedings, Volume 1, May 21-23, 2007, Niagara Falls, Canada, pp. 792-797, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Shuming Chen, Xiao Hu, Biwei Liu, Jihua Chen |
An On-Line Control Flow Checking Method for VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 17-19 December, 2007, Melbourne, Victoria, Australia, pp. 248-255, 2007, IEEE Computer Society, 0-7695-3054-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Chan-Hao Chang, Diana Marculescu |
Design and Analysis of a Low Power VLIW DSP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 167-172, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Andrzej Bednarski, Christoph W. Kessler |
Optimal Integrated VLIW Code Generation with Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 461-472, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo |
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Kostas Masselos, Yiannis Andreopoulos, Thanos Stouraitis |
Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Yung-Yuan Chen, Kuen-Long Leu, Chao-Sung Yeh |
Fault-Tolerant VLIW Processor Design and Error Coverage Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 754-765, 2006, Springer, 3-540-36679-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Alok Kumar Pani, Ratnam V. Raja Kumar |
Optimized VLIW Architecture for Non-zero IF QAM-Modem Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 513-516, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Daniele Bagni |
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 748-749, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 730-735, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 940-943, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Yue Li, Tao Li 0006 |
Bioinformatics on Embedded Systems: A Case Study of Computational Biology Applications on VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 16-29, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Shu Xiao 0001, Edmund Ming-Kit Lai, A. Benjamin Premkumar |
Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 28-40, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi |
Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 255-257, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee |
Compiler Supports and Optimizations for PAC VLIW DSP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers, pp. 466-474, 2005, Springer, 978-3-540-69329-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4090-4093, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
Exploring Design Space of VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 86-91, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen |
A unified processor architecture for RISC & VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 50-55, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-core processor, register organization, variable-length instruction encoding, digital signal processor |
34 | Esther Salamí, Mateo Valero |
Initial Evaluation of Multimedia Extensions on VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 403-412, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins |
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1224-1229, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Chang Hong Lin, Yuan Xie 0001, Wayne H. Wolf |
LZW-Based Code Compression for VLIW Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 76-81, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
Synthesizable HDL generation method for configurable VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 842-845, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Rahul Nagpal, Y. N. Srikant |
A Graph Matching Based Integrated Scheduling Framework for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 33rd International Conference on Parallel Processing Workshops (ICPP 2004 Workshops), 15-18 August 2004, Montreal, Quebec, Canada, pp. 530-537, 2004, IEEE Computer Society, 0-7695-2198-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Yung-Yuan Chen, Kun-Feng Chen |
Incorporating Signature-Monitoring Technique in VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 395-402, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
Multi-objective Optimization of a Parameterized VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 24-26 June 2004, Seattle, WA, USA, pp. 191-198, 2004, IEEE Computer Society, 0-7695-2145-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Sourabh Saluja, Anshul Kumar |
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 761-764, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Cristiana Bolchini |
A software methodology for detecting hardware faults in VLIW data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 52(4), pp. 458-468, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Satish Pillai, Margarida F. Jacome |
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10422-10427, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai |
An Integrated Fault-Tolerant Design Framework for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 555-562, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar |
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 177-182, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon |
Low-power data forwarding for VLIW embedded architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(5), pp. 614-622, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana |
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8), pp. 889-903, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Enric Gibert, F. Jesús Sánchez, Antonio González 0001 |
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 123-133, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Haris Lekatsas, Wayne H. Wolf, Yuan Xie 0001 |
Code Compression for VLIW Processors Using Variable-to-Fixed Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 138-143, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
assembly-level analysis, performance estimation, superscalar architectures |
34 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Modulo scheduling with integrated register spilling for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 160-169, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Rainer Leupers |
Instruction Scheduling for Clustered VLIW DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 291-300, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel |
A Hardware Platform for VLIW Based Emulation of Digital Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 747, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
Instruction-level power estimation for embedded VLIW cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000, pp. 34-38, 2000, ACM, 1-58113-268-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Margarida F. Jacome, Gustavo de Veciana |
Lower bound on latency for VLIW ASIP datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 261-269, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Jae-Woo Ahn, Soo-Mook Moon, Wonyong Sung |
An Efficient Compiled Simulation System for VLIW Code Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 31st Annual Simulation Symposium (SS '98), 5-9 April 1998, Boston, MA, USA, pp. 91-95, 1998, IEEE Computer Society, 0-8186-8418-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
34 | Soohong P. Kim, Raymond Hoare, Henry G. Dietz |
VLIW Across Multiple Superscalar Processors on a Single Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 166-, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
34 | R. Milikowski, Willem G. Vree |
Non-homogeneous Parallel Memory Operations in a VLIW Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 485-496, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker |
Sentinel Scheduling for VLIW and Superscalar Processors. (long version: TOCS 11(4): 376-408) ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-V Proceedings - Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, October 12-15, 1992., pp. 238-247, 1992, ACM Press, 0-89791-534-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
34 | Robert P. Colwell, W. Eric Hall, Chandra S. Joshi, David B. Papworth, Paul K. Rodman, James E. Tornes |
Architecture and implementation of a VLIW supercomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, pp. 910-919, 1990, IEEE Computer Society, 0-89791-412-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
34 | Toshio Nakatani, Kemal Ebcioglu |
"Combining" as a compilation technique for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989, pp. 43-55, 1989, ACM/IEEE, 0-89791-324-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
34 | Monica Lam 0001 |
Software Pipelining: An Effective Scheduling Technique for VLIW Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'88 Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, June 22-24, 1988, pp. 318-328, 1988, ACM, 0-89791-269-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
33 | Peter Rounce, Alberto Ferreira de Souza |
Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(2), pp. 184-205, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Simultaneous multi-threading, Wide issue architectures, VLIW, Dynamic instruction scheduling |
33 | Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao |
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 197-200, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
subgraph covering, VLIW, ASIPs, extensible processors |
33 | Won So, Alexander G. Dean |
Complementing software pipelining with software thread integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 137-146, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
TI C6000, DSP, software pipelining, VLIW, stream programming, coarse-grain parallelism, software thread integration |
33 | Gayathri Krishnamurthy, Elana D. Granston, Eric Stotzer |
Affinity-based cluster assignment for unrolled loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 107-116, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
affinity-based clustering (ABC) algorithms, homogeneous clusters, partitioned register files, software pipelining, loop optimizations, loop scheduling, VLIW architectures, loop unrolling, cluster assignment |
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