Search results for "VLIW"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
43	Natalino G. Busá, Albert van der Werf, Marco Bekooij	Scheduling Coarse-Grain Operations for VLIW Processors.	ISSS	2000	DBLP DOI BibTeX RDF
43	Morteza Biglari-Abhari, Kamran Eshraghian, Michael J. Liebelt	Improving Binary Compatibility in VLIW Machines through Compiler Assisted Dynamic Rescheduling.	EUROMICRO	2000	DBLP DOI BibTeX RDF
43	Catherine H. Gebotys, Robert J. Gebotys, S. Wiratunga	Power minimization derived from architectural-usage of VLIW processors.	DAC	2000	DBLP DOI BibTeX RDF
43	Rainer Leupers	Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors.	DATE	1999	DBLP DOI BibTeX RDF
43	Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind	Execution-Based Scheduling for VLIW Architectures.	Euro-Par	1999	DBLP DOI BibTeX RDF	INSTRUCTION-LEVEL PARALLELISM, SUPERSCALAR, BINARY TRANSLATION, DYNAMIC COMPILATION
43	Mladen Berekovic, Peter Pirsch, Johannes Kneip	An Algorithm-Hardware-System Approach to VLIW Multimedia Processors.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
43	Esther Stümpel, Michael Thies, Uwe Kastens	VLIW Compilation Techniques for Superscalar Architectures.	CC	1998	DBLP DOI BibTeX RDF
43	Robert P. Colwell, Robert P. Nix, John J. O'Donnell, David B. Papworth, Paul K. Rodman	A VLIW Architecture for a Trace Scheduling Compiler.	ASPLOS	1987	DBLP DOI BibTeX RDF
42	Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster 0001	Reducing power while increasing performance with supercisc.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Low-power, synthesis, VLIW, predication, multicore architectures
42	Nan Wu 0003, Mei Wen, Ju Ren 0002, Yi He 0008, Chunyuan Zhang	Register Allocation on Stream Processor with Local Register File.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	local register file, spilling, register allocation, VLIW, stream processor
42	Catherine H. Gebotys	Design of secure cryptography against the threat of power-attacks in DSP-embedded processors.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	VLIW
42	Catherine H. Gebotys, Robert J. Gebotys	Optimized mapping of video applications to hardware-software for VLSI architectures.	HICSS (1)	1995	DBLP DOI BibTeX RDF	integer optimization, video computations, video systems, optimized mapping, scheduling, VLSI, optimisation, VLSI architectures, video signal processing, VLIW processor
42	Manoj Franklin, Mark Smotherman	A fill-unit approach to multiple instruction issue.	MICRO	1994	DBLP DOI BibTeX RDF	multiple operation issue, instruction-level parallelism, VLIW, superscalar
39	Vincenzo Catania, Maurizio Palesi, Davide Patti	Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	hyperblock formation, genetic algorithms, performances, statistical analysis, power, energy, design space exploration, multiobjective optimization, ILP, VLIW architectures
39	Wonchul Lee, Hyojin Choi, Wonyong Sung	Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	variable block size motion estimation, H.264/AVC encoder, VLIW (very long instruction word), SIMD (single instruction multiple data)
39	Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Reducing dynamic and leakage energy in VLIW architectures.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	dynamic energy, schedule slacks, compiler, VLIW architecture, leakage energy
39	Zili Shao, Bin Xiao 0001, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Loop scheduling with timing and switching-activity minimization for VLIW DSP.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction bus optimization, low-power optimization, compilers, software pipelining, VLIW, retiming, instruction scheduling, loops
39	Won So, Alexander G. Dean	Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP.	CASES	2006	DBLP DOI BibTeX RDF	TI C6000, static profitability estimation, DSP, software pipelining, VLIW, iterative compilation, software thread integration
39	Rahul Nagpal, Y. N. Srikant	Integrated temporal and spatial scheduling for extended operand clustered VLIW processors.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	spatial scheduling, temporal scheduling, clustered VLIW processors
39	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Adapting instruction level parallelism for optimizing leakage in VLIW architectures.	LCTES	2003	DBLP DOI BibTeX RDF	power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units
39	Montserrat Ros, Peter Sutton	Compiler optimization and ordering effects on VLIW code compression.	CASES	2003	DBLP DOI BibTeX RDF	compiler optimizations, VLIW, code compression
39	Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana	Cluster assignment for high-performance embedded VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Operation binding, clustered VLIW datapaths, embedded systems, partitioning, embedded processors
39	Yi Qian, Steve Carr 0001, Philip H. Sweany	Loop fusion for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	clustered VLIW architectures, loop fusion
39	M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.	ISSS	2002	DBLP DOI BibTeX RDF	Trimaran, performance, design space exploration, VLIW, ASIP
39	David López 0001, Josep Llosa, Mateo Valero, Eduard Ayguadé	Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	numerical applications, performance/cost trade-off, instruction level parallelism, software pipelining, VLIW processors
39	Elana D. Granston, Eric Stotzer, Joe Zbiciak	Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture.	LCTES/OM	2001	DBLP DOI BibTeX RDF	WHILE loops, software pipelining, digital signal processors, VLIW architectures
39	Cagdas Akturan, Margarida F. Jacome	RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors.	CODES	2001	DBLP DOI BibTeX RDF	embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors
39	Cristiana Bolchini, Fabio Salice	A Software Methodology for Detecting Hardware Faults in VLIW Data Paths.	DFT	2001	DBLP DOI BibTeX RDF	Software code scheduling, VLIW processors, Hardware fault detection
39	Thomas M. Conte, Sumedh W. Sathaye	Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	instruction-set encoding, list encoding, VLIW, Microarchitecture, processor architecture, instruction cache
39	Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye	Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.	MICRO	1996	DBLP DOI BibTeX RDF	TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures
39	Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia	A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures.	MICRO	1996	DBLP DOI BibTeX RDF	LRU replacement, disk caching scheme, dynamic rescheduling, first-time page faults, high-overhead programs, low overhead object code compatibility, overhead-based replacement, page replacement policies, persistent rescheduled-page cache, run-time software rescheduling, simulations, cache storage, VLIW architectures, program executions, operating system support, program performance
39	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Scheduling of conditional branches using SSA form for superscalar/VLIW processors.	ICPADS	1996	DBLP DOI BibTeX RDF	conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA
39	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Eliminating Conditional Branches for Enhancing Instruction Level Parallelism in VLIW Compiler.	ISPAN	1996	DBLP DOI BibTeX RDF	Compiler, Instruction Level Parallelism, VLIW, Superscalar, Conditional Branches
39	Kemal Ebcioglu, Randy D. Groves, Ki-Chang Kim, Gabriel M. Silberman, Isaac Ziv	VLIW Compilation Techniques in a Superscalar Environment.	PLDI	1994	DBLP DOI BibTeX RDF	profiling directed feedback, compiler optimizations, software pipelining, VLIW, superscalars, global scheduling, IBM RS/6000
39	Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
36	Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch	Design Space Exploration of Media Processors: A Parameterized Scheduler.	ICSAMOS	2007	DBLP DOI BibTeX RDF
36	Michael Dupré, Nathalie Drach, Olivier Temam	VHC: Quickly Building an Optimizer for Complex Embedded Architectures.	CGO	2004	DBLP DOI BibTeX RDF
34	Yangyang Pan, Tong Zhang 0002	Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking.	ASAP	2009	DBLP DOI BibTeX RDF
34	Talal Bonny, Jörg Henkel	LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors.	DAC	2009	DBLP DOI BibTeX RDF	embedded systems, code compression, Huffman coding
34	Benoît Dupont de Dinechin	Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors.	Euro-Par	2008	DBLP DOI BibTeX RDF
34	Chun-Nan Liu, Jui Hong Hung, Tsung-Han Tsai 0001	Optimization techniques of AAC decoder on PACDSP VLIW processor.	ISCAS	2008	DBLP DOI BibTeX RDF
34	Meng Wang 0005, Zili Shao, Hui Liu 0006, Chun Jason Xue	Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors.	DIPES	2008	DBLP DOI BibTeX RDF
34	Hung-Chuan Lai, Shi-Jinn Horng, Yung-Yuan Chen	An Online Control Flow Check for VLIW Processor.	PRDC	2008	DBLP DOI BibTeX RDF
34	Yuan Xie 0001, Wayne H. Wolf, Haris Lekatsas	Code Decompression Unit Design for VLIW Embedded Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
34	Chang Hong Lin, Yuan Xie 0001, Wayne H. Wolf	Code Compression for VLIW Embedded Systems Using a Self-Generating Table.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
34	Rahul Nagpal, Y. N. Srikant	Compiler-Assisted Instruction Decoder Energy Optimization for Clustered VLIW Architectures.	HiPC	2007	DBLP DOI BibTeX RDF
34	Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch	Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler.	ARCS	2007	DBLP DOI BibTeX RDF
34	Min Li 0001, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor	A Wavelet-FFT Based Efficient Sparse OFDMA Demodulator and Its Implementation on VLIW Architecture.	SiPS	2007	DBLP DOI BibTeX RDF
34	Meng Wang 0005, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha	Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.	RTCSA	2007	DBLP DOI BibTeX RDF
34	Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen	Latency-Tolerant Virtual Cluster Architecture for VLIW DSP.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Abhishek Pillai, Wei Zhang 0002, Laurence Tianruo Yang	Exploring Functional Unit Design Space of VLIW Processors for Optimizing Both Performance and Energy Consumption.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
34	Shuming Chen, Xiao Hu, Biwei Liu, Jihua Chen	An On-Line Control Flow Checking Method for VLIW Processor.	PRDC	2007	DBLP DOI BibTeX RDF
34	Chan-Hao Chang, Diana Marculescu	Design and Analysis of a Low Power VLIW DSP Core.	ISVLSI	2006	DBLP DOI BibTeX RDF
34	Andrzej Bednarski, Christoph W. Kessler	Optimal Integrated VLIW Code Generation with Integer Linear Programming.	Euro-Par	2006	DBLP DOI BibTeX RDF
34	Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo	Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach.	IPDPS	2006	DBLP DOI BibTeX RDF
34	Kostas Masselos, Yiannis Andreopoulos, Thanos Stouraitis	Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP.	ISCAS	2006	DBLP DOI BibTeX RDF
34	Yung-Yuan Chen, Kuen-Long Leu, Chao-Sung Yeh	Fault-Tolerant VLIW Processor Design and Error Coverage Analysis.	EUC	2006	DBLP DOI BibTeX RDF
34	Alok Kumar Pani, Ratnam V. Raja Kumar	Optimized VLIW Architecture for Non-zero IF QAM-Modem Implementations.	VLSI Design	2006	DBLP DOI BibTeX RDF
34	Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Daniele Bagni	Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications.	DATE	2005	DBLP DOI BibTeX RDF
34	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	DATE	2005	DBLP DOI BibTeX RDF
34	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems.	ASP-DAC	2005	DBLP DOI BibTeX RDF
34	Yue Li, Tao Li 0006	Bioinformatics on Embedded Systems: A Case Study of Computational Biology Applications on VLIW Architecture.	ICESS	2005	DBLP DOI BibTeX RDF
34	Shu Xiao 0001, Edmund Ming-Kit Lai, A. Benjamin Premkumar	Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
34	Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi	Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
34	Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee	Compiler Supports and Optimizations for PAC VLIW DSP Processors.	LCPC	2005	DBLP DOI BibTeX RDF
34	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	Hyperblock formation: a power/energy perspective for high performance VLIW architectures.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
34	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	Exploring Design Space of VLIW Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
34	Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen	A unified processor architecture for RISC & VLIW DSP.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-core processor, register organization, variable-length instruction encoding, digital signal processor
34	Esther Salamí, Mateo Valero	Initial Evaluation of Multimedia Extensions on VLIW Architectures.	SAMOS	2004	DBLP DOI BibTeX RDF
34	Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins	Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study.	DATE	2004	DBLP DOI BibTeX RDF
34	Chang Hong Lin, Yuan Xie 0001, Wayne H. Wolf	LZW-Based Code Compression for VLIW Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF
34	Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Synthesizable HDL generation method for configurable VLIW processors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
34	Rahul Nagpal, Y. N. Srikant	A Graph Matching Based Integrated Scheduling Framework for Clustered VLIW Processors.	ICPP Workshops	2004	DBLP DOI BibTeX RDF
34	Yung-Yuan Chen, Kun-Feng Chen	Incorporating Signature-Monitoring Technique in VLIW Processors.	DFT	2004	DBLP DOI BibTeX RDF
34	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	Multi-objective Optimization of a Parameterized VLIW Architecture.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
34	Sourabh Saluja, Anshul Kumar	Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture.	VLSI Design	2004	DBLP DOI BibTeX RDF
34	Cristiana Bolchini	A software methodology for detecting hardware faults in VLIW data paths.	IEEE Trans. Reliab.	2003	DBLP DOI BibTeX RDF
34	Satish Pillai, Margarida F. Jacome	Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling.	DATE	2003	DBLP DOI BibTeX RDF
34	Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai	An Integrated Fault-Tolerant Design Framework for VLIW Processors.	DFT	2003	DBLP DOI BibTeX RDF
34	Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar	Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.	VLSI Design	2003	DBLP DOI BibTeX RDF
34	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon	Low-power data forwarding for VLIW embedded architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
34	Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana	Application-specific clustered VLIW datapaths: early exploration on a parameterized design space.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
34	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.	MICRO	2002	DBLP DOI BibTeX RDF
34	Haris Lekatsas, Wayne H. Wolf, Yuan Xie 0001	Code Compression for VLIW Processors Using Variable-to-Fixed Coding.	ISSS	2002	DBLP DOI BibTeX RDF	assembly-level analysis, performance estimation, superscalar architectures
34	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Modulo scheduling with integrated register spilling for clustered VLIW architectures.	MICRO	2001	DBLP DOI BibTeX RDF
34	Rainer Leupers	Instruction Scheduling for Clustered VLIW DSPs.	IEEE PACT	2000	DBLP DOI BibTeX RDF
34	Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel	A Hardware Platform for VLIW Based Emulation of Digital Designs.	DATE	2000	DBLP DOI BibTeX RDF
34	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	Instruction-level power estimation for embedded VLIW cores.	CODES	2000	DBLP DOI BibTeX RDF
34	Margarida F. Jacome, Gustavo de Veciana	Lower bound on latency for VLIW ASIP datapaths.	ICCAD	1999	DBLP DOI BibTeX RDF
34	Jae-Woo Ahn, Soo-Mook Moon, Wonyong Sung	An Efficient Compiled Simulation System for VLIW Code Verification.	Annual Simulation Symposium	1998	DBLP DOI BibTeX RDF
34	Soohong P. Kim, Raymond Hoare, Henry G. Dietz	VLIW Across Multiple Superscalar Processors on a Single Chip.	IEEE PACT	1997	DBLP DOI BibTeX RDF
34	R. Milikowski, Willem G. Vree	Non-homogeneous Parallel Memory Operations in a VLIW Machine.	CONPAR	1994	DBLP DOI BibTeX RDF
34	Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors. (long version: TOCS 11(4): 376-408)	ASPLOS	1992	DBLP DOI BibTeX RDF
34	Robert P. Colwell, W. Eric Hall, Chandra S. Joshi, David B. Papworth, Paul K. Rodman, James E. Tornes	Architecture and implementation of a VLIW supercomputer.	SC	1990	DBLP DOI BibTeX RDF
34	Toshio Nakatani, Kemal Ebcioglu	"Combining" as a compilation technique for VLIW architectures.	MICRO	1989	DBLP DOI BibTeX RDF
34	Monica Lam 0001	Software Pipelining: An Effective Scheduling Technique for VLIW Machines.	PLDI	1988	DBLP DOI BibTeX RDF
33	Peter Rounce, Alberto Ferreira de Souza	Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Simultaneous multi-threading, Wide issue architectures, VLIW, Dynamic instruction scheduling
33	Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao	Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques.	DAC	2008	DBLP DOI BibTeX RDF	subgraph covering, VLIW, ASIPs, extensible processors
33	Won So, Alexander G. Dean	Complementing software pipelining with software thread integration.	LCTES	2005	DBLP DOI BibTeX RDF	TI C6000, DSP, software pipelining, VLIW, stream programming, coarse-grain parallelism, software thread integration
33	Gayathri Krishnamurthy, Elana D. Granston, Eric Stotzer	Affinity-based cluster assignment for unrolled loops.	ICS	2002	DBLP DOI BibTeX RDF	affinity-based clustering (ABC) algorithms, homogeneous clusters, partitioned register files, software pipelining, loop optimizations, loop scheduling, VLIW architectures, loop unrolling, cluster assignment