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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2846 occurrences of 1432 keywords
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Results
Found 14080 publication records. Showing 14080 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Daniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali |
Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 226-231, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
crosstalk, mixed-signal ICs |
36 | Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler, David V. Anderson |
Developing Large-Scale Field-Programmable Analog Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | T. Salim, John C. Devlin, Jim Whittington |
Analog Conversion for FPGA Implementation of the TIGER Transmitter using a 14 bit DAC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 437-439, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Alex Doboli, Ranga Vemuri |
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), pp. 1504-1520, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Binlin Guo, Jiarong Tong |
A SC-based novel configurable analog cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 243, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin |
A Statistical Sampler for a New On-line Analog Test Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 79-, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham |
Signature analysis for analog and mixed-signal circuit test response compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6), pp. 540-546, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Jan Sevenhans, Didier Haspeslagh, Jacques Wenin |
Wireless telecom silicon integration: analog design for radio, baseband and speech spectrum. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Networks ![In: Wirel. Networks 4(1), pp. 71-77, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Nai-Chi Lee |
A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(4), pp. 361-368, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen |
Model Development and Verification for High Level Analog Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 376-382, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
36 | Jaeha Kim |
Mixed-Signal System Verification: A High-Speed Link Example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 16, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
analog and mixed-signal verification, analog design intent, linear system models |
36 | DongHyun Ko, Ji-Hoon Jung, YoungGun Pu, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam |
A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 3-6, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ADC(Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), Sigma-Delta Modulator |
36 | José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski |
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 96-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate |
36 | Naim Ben-Hamida, Khaled Saab 0001, David Marche, Bozena Kaminska |
A perturbation based fault modeling and simulation for mixed-signal circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 182-187, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
analog circuit fault simulation, perturbation fault model, fault abstraction, structural fault modeling, perturbation estimation, fault observation, hierarchical analog fault simulator, complexity, test generation, CMOS, mixed-signal circuits, mixed analogue-digital integrated circuits, functional fault modeling, physical defects |
36 | Michiel de Bakker, Piet W. Verbeek, Gijs K. Steenvoorden |
Design Considerations for a Range Image Sensor Containing a PSD-array and An On-chip Multiplexer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIM ![In: International Conference on Recent Advances in 3-D Digital Imaging and Modeling (3DIM '97), May 12-15, 1997, Ottawa, Ontario, Canada, pp. 11-18, 1997, IEEE Computer Society, 0-8186-7943-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
range image sensor, PSD-array, on-chip multiplexer, PSD-chip, light range imaging, analog preamplifiers, analog current multiplexer, image sensors, image sensor, low-pass filtering |
35 | Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras |
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(2), pp. 143-153, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Analog Switch, DC defective behaviour, DC test, open defect, bridging defect |
34 | Fernando De Bernardinis, Pierluigi Nuzzo 0001, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli |
Enriching an analog platform for analog-to-digital converter design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1286-1289, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Joachim Becker, Fabian Henrici, Yiannos Manoli |
System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 434-438, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | José Franco Machado do Amaral, Jorge Luís Machado do Amaral, Cristina Costa Santini, Marco Aurélio Cavalcanti Pacheco, Ricardo Tanscheit, Moisés H. Szwarcman |
Intrinsic Evolution of Analog Circuits on a Programmable Analog Multiplexer Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science ![In: Computational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part III, pp. 1273-1280, 2004, Springer, 3-540-22116-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Mario Costa, Davide Palmisano, Eros Pasero |
NESP2: a Low Power Analog NEural Signal Processor with Analog Weight Storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (4) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 4, pp. 51-56, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia |
Analog hardware implementation of a vector quantizer for focal-plane image compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 233-238, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CMOS analog hardware, analog image processing, vector quantization |
34 | Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud |
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 399-409, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
structural fault modeling, analog fault modeling, Neyman-Pearson decision, fault detection, analog test, supply current monitoring |
34 | Miguel Angel Domínguez, José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli |
A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 437-448, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog built-in self-test, analog IC test, on-chip spectrum analyzer, switched-capacitor circuits, non-uniform sampling |
34 | Michel Morneau, Abdelhakim Khouas |
TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 425-436, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
DC fault simulation, analog fault detection, Newton-Raphson algorithm, analog testing |
34 | Haralampos-G. D. Stratigopoulos, Yiorgos Makris |
An Analog Checker with Input-Relative Tolerance for Duplicate Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(5), pp. 479-488, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
analog checkers, on-line test, analog test, concurrent test |
34 | Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen |
A high-level design and optimization tool for analog RF receiver front-ends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 550-553, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analog CAD, analog high-level synthesis, RF design and optimization |
34 | Stephen K. Sunter |
A low cost 100 MHz analog test bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 60-65, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analog test bus, on-chip analog bus, digital three-state inverter, low-input capacitance, signal bandwidth, bus input, design for testability, DFT, integrated circuit design, mixed-signal circuits, capacitance, mixed analogue-digital integrated circuits, IC design, 100 MHz |
34 | Valeriu Beiu |
A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 167-177, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Abhijit Chatterjee, Naveena Nagi |
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 388-392, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
33 | Brandon Rumberg, David W. Graham, Vinod Kulathumani |
Hibernets: energy-efficient sensor networks using analog signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSN ![In: Proceedings of the 9th International Conference on Information Processing in Sensor Networks, IPSN 2010, April 12-16, 2010, Stockholm, Sweden, pp. 442-443, 2010, ACM, 978-1-60558-988-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog signal processing, selective wake up, sensor networks, energy-efficient, in-network processing |
33 | Brandon Rumberg, David W. Graham, Vinod Kulathumani |
Hibernets: energy-efficient sensor networks using analog signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSN ![In: Proceedings of the 9th International Conference on Information Processing in Sensor Networks, IPSN 2010, April 12-16, 2010, Stockholm, Sweden, pp. 129-139, 2010, ACM, 978-1-60558-988-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog signal processing, selective wake up, sensor networks, energy-efficient, in-network processing |
33 | Qiang Gao, Yin Shen, Yici Cai, Hailong Yao |
Analog circuit shielding routing algorithm based on net classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 123-128, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog routing, shielding routing, A* algorithm |
33 | Xuening Sun, Pierluigi Nuzzo 0002, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli |
Contract-based system-level composition of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 605-610, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
integration, composition, contract, system, analog, UWB, platform, platform-based design, radio-frequency, assume-guarantee |
33 | Fang Liu 0029, Sule Ozev, Plamen K. Nikolov |
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 33:1-33:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Hierarchical variance analysis, parameter correlations, performance model, process variations, analog circuits |
33 | Emilia Sipos, Lelia Festila, Gabriel Oltean |
Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (3) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 12th International Conference, KES 2008, Zagreb, Croatia, September 3-5, 2008, Proceedings, Part III, pp. 351-359, 2008, Springer, 978-3-540-85566-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Analog multiplexer, reconfigurable circuit, transmission gate, CMOS transistors, SUS-LOC |
33 | Saurabh Sinha, Asha Balijepalli, Yu Cao |
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 502-507, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Schottky barrier, analog design metrics, modeling, CNT |
33 | Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell |
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(6), pp. 497-512, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Analog built-in self-test, Transient response analysis, FPAA |
33 | Di Long, Xianlong Hong, Sheqin Dong |
Signal-path driven partition and placement for analog circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 694-699, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog placement, device merging, layout automation, signal-path, symmetry constrain, circuit partition |
33 | Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell |
Functional Test of Field Programmable Analog Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 326-333, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analog built-in self-test, transient response analysis, FPAA |
33 | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 |
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(3), pp. 243-255, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
analog filter, trim bit, dynamic supply current (IDD), wavelet transform, frequency response |
33 | Viera Stopjaková, Pavol Malosek, Daniel Micusík, Marek Matej, Martin Margala |
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 25-37, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
artificial neural networks, analog test, catastrophic faults, supply current monitoring |
33 | Hajime Shibata, Adrian Stoica, Nobuo Fujii |
Controllable decoding for automated analog circuit structure design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Comput. ![In: Soft Comput. 8(5), pp. 344-353, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Automated circuit synthesis, Genetic algorithm, Analog circuit |
33 | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 |
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 389-394, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Analog Filer, Trim Bit, Dynamic Supply Current (IDD), Wavelet Transform |
33 | L. Cassol, O. Betat, Luigi Carro, Marcelo Lubaszewski |
The SigmaDelta-BIST Method Applied to Analog Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(1), pp. 13-20, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
BIST, analog test, mixed signal testing, sigma-delta modulator |
33 | Sule Ozev, Alex Orailoglu |
Statistical Tolerance Analysis for Assured Analog Test Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(2), pp. 173-182, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
tolerance analysis, test signal propagation, statistical analysis, analog test |
33 | Maria del Mar Hershenson |
Efficient description of the design space of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 970-973, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
optimization, verification, synthesis, analog, circuits, convex programming, geometric program |
33 | Xin Li 0001, Peng Li 0001, Yang Xu 0017, Lawrence T. Pileggi |
Analog and RF circuit macromodels for system-level analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 478-483, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
analog/RF circuits, macromodel |
33 | M. A. El-Gamal |
Genetically Evolved Neural Networks for Fault Classification in Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 11(2), pp. 112-121, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Fault grouping, Genetically evolved neural networks, Genetic algorithms, Fault simulation, Analog circuits, Fault classification |
33 | Sree Ganesan, Ranga Vemuri |
A Methodology for Rapid Prototyping of Analog Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 482-488, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
rapid prototyping, technology mapping, placement and routing, FPAA, field-programmable analog arrays |
33 | Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung Lee, John L. Wyatt Jr. |
Estimating the Focus of Expansion in Analog VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Vis. ![In: Int. J. Comput. Vis. 28(3), pp. 261-277, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
passive navigation, analog VLSI, motion vision, focus of expansion |
33 | Ralf Rosenberger, Sorin A. Huss |
A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 721-728, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
analog modeling, simulation methodologies |
33 | Firas Mohamed, Meryem Marzouki |
Test and diagnosis of analog circuits: When fuzziness can lead to accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(1-2), pp. 203-216, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
analog test and diagnosis, AI approaches, fuzzy logic |
33 | Marcelo Lubaszewski, Salvador Mir, Leandro Pulz |
ABILBO: Analog BuILt-in Block Observer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 600-603, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
built-in self-test, design for test, analog and mixed-signal testing |
33 | Yeong-Ruey Shieh, Cheng-Wen Wu |
DC control and observation structures for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 120-126, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
level-sensitive scan-design, test points, DC voltage levels, diagnosis capability, calibration process, read-out voltage levels, VLSI, VLSI, fault diagnosis, controllability, controllability, integrated circuit testing, calibration, observability, observability, analog circuits, mixed signal circuits, mixed analogue-digital integrated circuits |
33 | George A. Hadgis, P. R. Mukund |
A novel CMOS monolithic analog multiplier with wide input dynamic range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 310-314, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits |
33 | Mounir Fares, Bozena Kaminska |
Fuzzy optimization models for analog test decisions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(2-3), pp. 299-305, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Analog circuits, test selection, parametric optimization, fuzzy decision-making |
31 | ByongChan Lim, Jaeha Kim, Mark A. Horowitz |
An efficient test vector generation for checking analog/mixed-signal functional models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 767-772, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
linear abstraction, validation, equivalence checking, verilog, functional model, test vector, mixed-signal circuits |
31 | Wolfgang Eberle, Michaël Goffioul |
A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 710-715, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Thomas Jacob Koickal, Luiz Carlos Gouveia, Alister Hamilton |
Bio-inspired Event Coded Configurable Analog Circuit Block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings, pp. 285-295, 2008, Springer, 978-3-540-85856-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Ali Namazi, Syed Askari, Mehrdad Nourani |
Highly reliable A/D converter using analog voting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 334-339, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Sheng-Yu Peng, Bradley A. Minch, Paul E. Hasler |
Analog VLSI implementation of support vector machine learning and classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 860-863, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Didier Le Ruyet, Berna Özbek |
Partial and Analog Feedback for MISO Precoding Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2007, Glasgow, Scotland, UK, 24-28 June 2007, pp. 2767-2772, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Qingjian Ji, Youren Wang, Min Xie, Jiang Cui |
Research on Fault-Tolerance of Analog Circuits Based on Evolvable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 100-108, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
EHW, FPACA, Amplifier circuit, Fault-tolerance, Evolutionary algorithm |
31 | Xin Li 0001, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi |
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 450-457, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Guo Yu, Peng Li 0001 |
Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 464-469, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Brian Gestner, Jason Tanner, David V. Anderson |
Glass Break Detector Analog Front-End Using Novel Classifier Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3586-3589, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Aaron St. Leger, Chika O. Nwankpa |
Analog and Hybrid Computation Approaches for Static Power Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 40th Hawaii International International Conference on Systems Science (HICSS-40 2007), CD-ROM / Abstracts Proceedings, 3-6 January 2007, Waikoloa, Big Island, HI, USA, pp. 119, 2007, IEEE Computer Society, 0-7695-2755-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Lihong Zhang, Ulrich Kleine, Yingtao Jiang |
An automated design tool for analog layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 881-894, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Seiji Kameda, Tetsuya Yagi |
An analog silicon retina with multichip configuration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 17(1), pp. 197-210, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel |
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 12-22, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Aaron St. Leger, Chika O. Nwankpa |
Static generator model for analog power flow computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Shweta Chary, Michael L. Bushnell |
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 818-823, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri |
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 689-694, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Robert J. Bowman |
An Educational Program for Engineering Careers in Analog and Mixed-Signal Electronic Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2005 International Conference on Microelectronics Systems Education, MSE 2005, Anaheim, CA, USA, June 12-13, 2005, pp. 39-40, 2005, IEEE Computer Society, 0-7695-2374-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Ji Luo 0003, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang 0001, Kuan-Jung Chung, Anthony L. Wilson |
A High Performance Radiation-Hard Field Programmable Analog Array . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 522-527, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Mohamed Hafed |
Glamorous Analog Testability - We Already Test them and Ship Them - So What is the Problem? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1416, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Yang Xu 0017, Lawrence T. Pileggi, Stephen P. Boyd |
ORACLE: optimization with recourse of analog circuits including layout extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 151-154, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization with recourse |
31 | Roman Genov, Gert Cauwenberghs |
Algorithmic partial analog-to-digital conversion in mixed-signal array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 769-772, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov |
Analog IP design flow for SoC applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 676-679, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Danica Stefanovic, Maher Kayal, Marc Pastre, Vanco B. Litovski |
Procedural Analog Design (PAD) Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 313-318, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | T. M. Massengill, Denise M. Wilson, Paul E. Hasler, David W. Graham |
Empirical comparison of analog and digital auditory preprocessing for automatic speech recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 77-80, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Sree Ganesan, Ranga Vemuri |
Library Binding for High-Level Synthesis of Analog Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 261-268, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Resve A. Saleh, Brian A. A. Antao, Jaidip Singh |
Multilevel and mixed-domain simulation of analog circuits and systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1), pp. 68-82, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Brian A. A. Antao, Arthur J. Brodersen |
Behavioral simulation for analog system design verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(3), pp. 417-429, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois |
Analog checkers with absolute and relative tolerances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5), pp. 607-612, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Arun Achyuthan, Mohamed I. Elmasry |
Mixed analog/digital hardware synthesis of artificial neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9), pp. 1073-1087, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
31 | Linda S. Milor, Alberto L. Sangiovanni-Vincentelli |
Minimizing production test time to detect faults in analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6), pp. 796-813, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
31 | Genhong Ruan, Jirí Vlach, James A. Barby, Ajoy Opal |
Analog functional simulator for multilevel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5), pp. 565-576, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
31 | Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 449-462, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array |
31 | Gert Cauwenberghs |
Design and VLSI Implementation of an Adaptive Delta-Sigma Modulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 155-160, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
neural networks, reinforcement learning, analog VLSI, delta-sigma modulation, analog-to-digital conversion |
31 | Zhenhua Wang |
Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 383-386, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
robustness enhancement, sensitivity reduction, low-power, low-energy, analog integrated circuits, biasing |
29 | Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng |
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 62-67, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Bradley A. Minch |
Translinear Analog Signal Processing: A Modular Approach to Large-Scale Analog Computation with Multiple-Input Translinear Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 186-199, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Moshe Mishali, Yonina C. Eldar |
Xampling: Analog Data Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCC ![In: 2010 Data Compression Conference (DCC 2010), 24-26 March 2010, Snowbird, UT, USA, pp. 366-375, 2010, IEEE Computer Society, 978-0-7695-3994-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog processing circuits, data conversion, sampling methods, analog digital conversion |
29 | Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani |
Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 281, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adc, sd card, fpga, real-time, multiplexing, data acquisition, fft |
29 | Reimund Wittmann, Massimo Vanzi, Hans-Joachim Wassener, Navraj Nandra, Joachim Kunkel, José E. da Franca, Christian Münker |
Life begins at 65: unless you are mixed signal? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 936-941, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Paul E. Hasler |
Low-Power Programmable Signal Processing, invited. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 413-418, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | José Luis Huertas |
Test and design-for-test of mixed-signal integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 4, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Alvernon Walker |
A Step Response Based Mixed-Signal BIST Approach . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 329-337, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Peter Frey, Radharamanan Radhakrishnan |
Parallel mixed-technology simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADS ![In: Proceedings of the 14th Workshop on Parallel and Distributed Simulation, PADS 2000, Bologna, Italy, May 28-31, 2000, pp. 7-14, 2000, IEEE Computer Society, 0-7695-0667-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
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