|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 2846 occurrences of 1432 keywords
|
|
|
Results
Found 14080 publication records. Showing 14080 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
36 | Daniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali |
Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
crosstalk, mixed-signal ICs |
36 | Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler, David V. Anderson |
Developing Large-Scale Field-Programmable Analog Arrays. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
36 | T. Salim, John C. Devlin, Jim Whittington |
Analog Conversion for FPGA Implementation of the TIGER Transmitter using a 14 bit DAC. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Alex Doboli, Ranga Vemuri |
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Binlin Guo, Jiarong Tong |
A SC-based novel configurable analog cell. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin |
A Statistical Sampler for a New On-line Analog Test Method. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham |
Signature analysis for analog and mixed-signal circuit test response compaction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Jan Sevenhans, Didier Haspeslagh, Jacques Wenin |
Wireless telecom silicon integration: analog design for radio, baseband and speech spectrum. |
Wirel. Networks |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Nai-Chi Lee |
A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards. |
J. Electron. Test. |
1993 |
DBLP DOI BibTeX RDF |
|
36 | Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen |
Model Development and Verification for High Level Analog Blocks. |
DAC |
1988 |
DBLP BibTeX RDF |
|
36 | Jaeha Kim |
Mixed-Signal System Verification: A High-Speed Link Example. |
CAV |
2009 |
DBLP DOI BibTeX RDF |
analog and mixed-signal verification, analog design intent, linear system models |
36 | DongHyun Ko, Ji-Hoon Jung, YoungGun Pu, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam |
A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS Process. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
ADC(Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), Sigma-Delta Modulator |
36 | José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski |
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate |
36 | Naim Ben-Hamida, Khaled Saab 0001, David Marche, Bozena Kaminska |
A perturbation based fault modeling and simulation for mixed-signal circuits. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
analog circuit fault simulation, perturbation fault model, fault abstraction, structural fault modeling, perturbation estimation, fault observation, hierarchical analog fault simulator, complexity, test generation, CMOS, mixed-signal circuits, mixed analogue-digital integrated circuits, functional fault modeling, physical defects |
36 | Michiel de Bakker, Piet W. Verbeek, Gijs K. Steenvoorden |
Design Considerations for a Range Image Sensor Containing a PSD-array and An On-chip Multiplexer. |
3DIM |
1997 |
DBLP DOI BibTeX RDF |
range image sensor, PSD-array, on-chip multiplexer, PSD-chip, light range imaging, analog preamplifiers, analog current multiplexer, image sensors, image sensor, low-pass filtering |
35 | Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras |
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
Analog Switch, DC defective behaviour, DC test, open defect, bridging defect |
34 | Fernando De Bernardinis, Pierluigi Nuzzo 0001, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli |
Enriching an analog platform for analog-to-digital converter design. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Joachim Becker, Fabian Henrici, Yiannos Manoli |
System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
34 | José Franco Machado do Amaral, Jorge Luís Machado do Amaral, Cristina Costa Santini, Marco Aurélio Cavalcanti Pacheco, Ricardo Tanscheit, Moisés H. Szwarcman |
Intrinsic Evolution of Analog Circuits on a Programmable Analog Multiplexer Array. |
International Conference on Computational Science |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Mario Costa, Davide Palmisano, Eros Pasero |
NESP2: a Low Power Analog NEural Signal Processor with Analog Weight Storage. |
IJCNN (4) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia |
Analog hardware implementation of a vector quantizer for focal-plane image compression. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
CMOS analog hardware, analog image processing, vector quantization |
34 | Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud |
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
structural fault modeling, analog fault modeling, Neyman-Pearson decision, fault detection, analog test, supply current monitoring |
34 | Miguel Angel Domínguez, José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli |
A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
analog built-in self-test, analog IC test, on-chip spectrum analyzer, switched-capacitor circuits, non-uniform sampling |
34 | Michel Morneau, Abdelhakim Khouas |
TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
DC fault simulation, analog fault detection, Newton-Raphson algorithm, analog testing |
34 | Haralampos-G. D. Stratigopoulos, Yiorgos Makris |
An Analog Checker with Input-Relative Tolerance for Duplicate Signals. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
analog checkers, on-line test, analog test, concurrent test |
34 | Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen |
A high-level design and optimization tool for analog RF receiver front-ends. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
analog CAD, analog high-level synthesis, RF design and optimization |
34 | Stephen K. Sunter |
A low cost 100 MHz analog test bus. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
analog test bus, on-chip analog bus, digital three-state inverter, low-input capacitance, signal bandwidth, bus input, design for testability, DFT, integrated circuit design, mixed-signal circuits, capacitance, mixed analogue-digital integrated circuits, IC design, 100 MHz |
34 | Valeriu Beiu |
A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments. |
ASAP |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Abhijit Chatterjee, Naveena Nagi |
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
33 | Brandon Rumberg, David W. Graham, Vinod Kulathumani |
Hibernets: energy-efficient sensor networks using analog signal processing. |
IPSN |
2010 |
DBLP DOI BibTeX RDF |
analog signal processing, selective wake up, sensor networks, energy-efficient, in-network processing |
33 | Brandon Rumberg, David W. Graham, Vinod Kulathumani |
Hibernets: energy-efficient sensor networks using analog signal processing. |
IPSN |
2010 |
DBLP DOI BibTeX RDF |
analog signal processing, selective wake up, sensor networks, energy-efficient, in-network processing |
33 | Qiang Gao, Yin Shen, Yici Cai, Hailong Yao |
Analog circuit shielding routing algorithm based on net classification. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
analog routing, shielding routing, A* algorithm |
33 | Xuening Sun, Pierluigi Nuzzo 0002, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli |
Contract-based system-level composition of analog circuits. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
integration, composition, contract, system, analog, UWB, platform, platform-based design, radio-frequency, assume-guarantee |
33 | Fang Liu 0029, Sule Ozev, Plamen K. Nikolov |
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Hierarchical variance analysis, parameter correlations, performance model, process variations, analog circuits |
33 | Emilia Sipos, Lelia Festila, Gabriel Oltean |
Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers. |
KES (3) |
2008 |
DBLP DOI BibTeX RDF |
Analog multiplexer, reconfigurable circuit, transmission gate, CMOS transistors, SUS-LOC |
33 | Saurabh Sinha, Asha Balijepalli, Yu Cao |
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Schottky barrier, analog design metrics, modeling, CNT |
33 | Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell |
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. |
J. Electron. Test. |
2007 |
DBLP DOI BibTeX RDF |
Analog built-in self-test, Transient response analysis, FPAA |
33 | Di Long, Xianlong Hong, Sheqin Dong |
Signal-path driven partition and placement for analog circuit. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
analog placement, device merging, layout automation, signal-path, symmetry constrain, circuit partition |
33 | Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell |
Functional Test of Field Programmable Analog Arrays. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
analog built-in self-test, transient response analysis, FPAA |
33 | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 |
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
analog filter, trim bit, dynamic supply current (IDD), wavelet transform, frequency response |
33 | Viera Stopjaková, Pavol Malosek, Daniel Micusík, Marek Matej, Martin Margala |
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
artificial neural networks, analog test, catastrophic faults, supply current monitoring |
33 | Hajime Shibata, Adrian Stoica, Nobuo Fujii |
Controllable decoding for automated analog circuit structure design. |
Soft Comput. |
2004 |
DBLP DOI BibTeX RDF |
Automated circuit synthesis, Genetic algorithm, Analog circuit |
33 | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 |
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
Analog Filer, Trim Bit, Dynamic Supply Current (IDD), Wavelet Transform |
33 | L. Cassol, O. Betat, Luigi Carro, Marcelo Lubaszewski |
The SigmaDelta-BIST Method Applied to Analog Filters. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
BIST, analog test, mixed signal testing, sigma-delta modulator |
33 | Sule Ozev, Alex Orailoglu |
Statistical Tolerance Analysis for Assured Analog Test Coverage. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
tolerance analysis, test signal propagation, statistical analysis, analog test |
33 | Maria del Mar Hershenson |
Efficient description of the design space of analog circuits. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
optimization, verification, synthesis, analog, circuits, convex programming, geometric program |
33 | Xin Li 0001, Peng Li 0001, Yang Xu 0017, Lawrence T. Pileggi |
Analog and RF circuit macromodels for system-level analysis. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
analog/RF circuits, macromodel |
33 | M. A. El-Gamal |
Genetically Evolved Neural Networks for Fault Classification in Analog Circuits. |
Neural Comput. Appl. |
2002 |
DBLP DOI BibTeX RDF |
Fault grouping, Genetically evolved neural networks, Genetic algorithms, Fault simulation, Analog circuits, Fault classification |
33 | Sree Ganesan, Ranga Vemuri |
A Methodology for Rapid Prototyping of Analog Systems. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
rapid prototyping, technology mapping, placement and routing, FPAA, field-programmable analog arrays |
33 | Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung Lee, John L. Wyatt Jr. |
Estimating the Focus of Expansion in Analog VLSI. |
Int. J. Comput. Vis. |
1998 |
DBLP DOI BibTeX RDF |
passive navigation, analog VLSI, motion vision, focus of expansion |
33 | Ralf Rosenberger, Sorin A. Huss |
A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
analog modeling, simulation methodologies |
33 | Firas Mohamed, Meryem Marzouki |
Test and diagnosis of analog circuits: When fuzziness can lead to accuracy. |
J. Electron. Test. |
1996 |
DBLP DOI BibTeX RDF |
analog test and diagnosis, AI approaches, fuzzy logic |
33 | Marcelo Lubaszewski, Salvador Mir, Leandro Pulz |
ABILBO: Analog BuILt-in Block Observer. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
built-in self-test, design for test, analog and mixed-signal testing |
33 | Yeong-Ruey Shieh, Cheng-Wen Wu |
DC control and observation structures for analog circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
level-sensitive scan-design, test points, DC voltage levels, diagnosis capability, calibration process, read-out voltage levels, VLSI, VLSI, fault diagnosis, controllability, controllability, integrated circuit testing, calibration, observability, observability, analog circuits, mixed signal circuits, mixed analogue-digital integrated circuits |
33 | George A. Hadgis, P. R. Mukund |
A novel CMOS monolithic analog multiplier with wide input dynamic range. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits |
33 | Mounir Fares, Bozena Kaminska |
Fuzzy optimization models for analog test decisions. |
J. Electron. Test. |
1994 |
DBLP DOI BibTeX RDF |
Analog circuits, test selection, parametric optimization, fuzzy decision-making |
31 | ByongChan Lim, Jaeha Kim, Mark A. Horowitz |
An efficient test vector generation for checking analog/mixed-signal functional models. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
linear abstraction, validation, equivalence checking, verilog, functional model, test vector, mixed-signal circuits |
31 | Wolfgang Eberle, Michaël Goffioul |
A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Thomas Jacob Koickal, Luiz Carlos Gouveia, Alister Hamilton |
Bio-inspired Event Coded Configurable Analog Circuit Block. |
ICES |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Ali Namazi, Syed Askari, Mehrdad Nourani |
Highly reliable A/D converter using analog voting. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Sheng-Yu Peng, Bradley A. Minch, Paul E. Hasler |
Analog VLSI implementation of support vector machine learning and classification. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Didier Le Ruyet, Berna Özbek |
Partial and Analog Feedback for MISO Precoding Systems. |
ICC |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Qingjian Ji, Youren Wang, Min Xie, Jiang Cui |
Research on Fault-Tolerance of Analog Circuits Based on Evolvable Hardware. |
ICES |
2007 |
DBLP DOI BibTeX RDF |
EHW, FPACA, Amplifier circuit, Fault-tolerance, Evolutionary algorithm |
31 | Xin Li 0001, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi |
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Guo Yu, Peng Li 0001 |
Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Brian Gestner, Jason Tanner, David V. Anderson |
Glass Break Detector Analog Front-End Using Novel Classifier Circuit. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Aaron St. Leger, Chika O. Nwankpa |
Analog and Hybrid Computation Approaches for Static Power Flow. |
HICSS |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Lihong Zhang, Ulrich Kleine, Yingtao Jiang |
An automated design tool for analog layouts. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Seiji Kameda, Tetsuya Yagi |
An analog silicon retina with multichip configuration. |
IEEE Trans. Neural Networks |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel |
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter. |
ASYNC |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Aaron St. Leger, Chika O. Nwankpa |
Static generator model for analog power flow computation. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Shweta Chary, Michael L. Bushnell |
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri |
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Robert J. Bowman |
An Educational Program for Engineering Careers in Analog and Mixed-Signal Electronic Design. |
MSE |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Ji Luo 0003, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang 0001, Kuan-Jung Chung, Anthony L. Wilson |
A High Performance Radiation-Hard Field Programmable Analog Array . |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Mohamed Hafed |
Glamorous Analog Testability - We Already Test them and Ship Them - So What is the Problem? |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Yang Xu 0017, Lawrence T. Pileggi, Stephen P. Boyd |
ORACLE: optimization with recourse of analog circuits including layout extraction. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
optimization with recourse |
31 | Roman Genov, Gert Cauwenberghs |
Algorithmic partial analog-to-digital conversion in mixed-signal array processors. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov |
Analog IP design flow for SoC applications. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Danica Stefanovic, Maher Kayal, Marc Pastre, Vanco B. Litovski |
Procedural Analog Design (PAD) Tool. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
31 | T. M. Massengill, Denise M. Wilson, Paul E. Hasler, David W. Graham |
Empirical comparison of analog and digital auditory preprocessing for automatic speech recognition. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Sree Ganesan, Ranga Vemuri |
Library Binding for High-Level Synthesis of Analog Systems. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Resve A. Saleh, Brian A. A. Antao, Jaidip Singh |
Multilevel and mixed-domain simulation of analog circuits and systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Brian A. A. Antao, Arthur J. Brodersen |
Behavioral simulation for analog system design verification. |
IEEE Trans. Very Large Scale Integr. Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois |
Analog checkers with absolute and relative tolerances. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Arun Achyuthan, Mohamed I. Elmasry |
Mixed analog/digital hardware synthesis of artificial neural networks. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
31 | Linda S. Milor, Alberto L. Sangiovanni-Vincentelli |
Minimizing production test time to detect faults in analog circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
31 | Genhong Ruan, Jirí Vlach, James A. Barby, Ajoy Opal |
Analog functional simulator for multilevel systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
31 | Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array |
31 | Gert Cauwenberghs |
Design and VLSI Implementation of an Adaptive Delta-Sigma Modulator. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
neural networks, reinforcement learning, analog VLSI, delta-sigma modulation, analog-to-digital conversion |
31 | Zhenhua Wang |
Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
robustness enhancement, sensitivity reduction, low-power, low-energy, analog integrated circuits, biasing |
29 | Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng |
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Bradley A. Minch |
Translinear Analog Signal Processing: A Modular Approach to Large-Scale Analog Computation with Multiple-Input Translinear Elements. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Moshe Mishali, Yonina C. Eldar |
Xampling: Analog Data Compression. |
DCC |
2010 |
DBLP DOI BibTeX RDF |
analog processing circuits, data conversion, sampling methods, analog digital conversion |
29 | Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani |
Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
adc, sd card, fpga, real-time, multiplexing, data acquisition, fft |
29 | Reimund Wittmann, Massimo Vanzi, Hans-Joachim Wassener, Navraj Nandra, Joachim Kunkel, José E. da Franca, Christian Münker |
Life begins at 65: unless you are mixed signal? |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Paul E. Hasler |
Low-Power Programmable Signal Processing, invited. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
29 | José Luis Huertas |
Test and design-for-test of mixed-signal integrated circuits. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Alvernon Walker |
A Step Response Based Mixed-Signal BIST Approach . |
DFT |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Peter Frey, Radharamanan Radhakrishnan |
Parallel mixed-technology simulation. |
PADS |
2000 |
DBLP DOI BibTeX RDF |
|
Displaying result #101 - #200 of 14080 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ >>] |
|