Search results for "busses"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Björn Griese, Boris Kettelhoit, Mario Porrmann	Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors.	PARELEC	2006	DBLP DOI BibTeX RDF
13	Ralf M. Schreier, A. Tushar Iqbal Rahman, Ganesh Krishnamurthy, Albrecht Rothermel	Architecture Analysis for Low-Delay Video Coding.	ICME	2006	DBLP DOI BibTeX RDF
13	Eui Bong Jung, Han Wook Cho, Neungsoo Park, Yong Ho Song	SONA: An On-Chip Network for Scalable Interconnection of AMBA-Based IPs.	International Conference on Computational Science (4)	2006	DBLP DOI BibTeX RDF
13	Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten	Dynamic-SIMD for lens distortion compensation.	ASAP	2006	DBLP DOI BibTeX RDF
13	Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys	Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects.	ISQED	2006	DBLP DOI BibTeX RDF
13	Jochen Müller, Ulrich Epple	A Generic Information Model for an XML-based Device Profile of Pumps.	ETFA	2006	DBLP DOI BibTeX RDF
13	Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli	A robust self-calibrating transmission scheme for on-chip networks.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
13	Ken Tseng, Mark Horowitz	False coupling exploration in timing analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
13	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware low-power high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
13	Robert C. Martin	The Test Bus Imperative: Architectures That Support Automated Acceptance Testing.	IEEE Softw.	2005	DBLP DOI BibTeX RDF	automated acceptance testing, test bus
13	Ronald Hochreiter, Clemens Wiesinger, David Wozabal	Large-Scale Computational Finance Applications on the Open Grid Service Environment.	EGC	2005	DBLP DOI BibTeX RDF
13	Luciano Ost, Aline Mello 0001, José Palma 0002, Fernando Gehm Moraes, Ney Calazans	MAIA: a framework for networks on chip generation and verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
13	Oliver Bringmann 0001, Wolfgang Rosenstiel, Axel Siebenborn	Conflict analysis in multiprocess synthesis for optimized system integration.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	scheduling, systems-on-chip, system level design, concurrent systems, binding, behavioral synthesis
13	Jean-Luc Scharbarg, Marc Boyer, Jérôme Ermont, Christian Fraboul	TTCAN over mixed CAN/switched Ethernet architecture.	ETFA	2005	DBLP DOI BibTeX RDF
13	Atul Katoch, Maurice Meijer, Sanjeev K. Jain	Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication.	VLSI Design	2005	DBLP DOI BibTeX RDF
13	Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards	A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
13	André K. Nieuwland, Atul Katoch, Maurice Meijer	Reducing Cross-Talk Induced Power Consumption and Delay.	PATMOS	2004	DBLP DOI BibTeX RDF
13	Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis	Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing.	DATE	2004	DBLP DOI BibTeX RDF
13	Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus	A Hierarchical Self Test Scheme for SoCs.	IOLTS	2004	DBLP DOI BibTeX RDF
13	Jeff Young, Ron Sass	FERP Interface and Interconnect Cores for Stream Processing Applications.	EUC	2004	DBLP DOI BibTeX RDF
13	Mirko Loghi, Massimo Poncino, Luca Benini	Cycle-accurate power analysis for multiprocessor systems-on-a-chip.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, multiprocessor, system-on-chip
13	Peter Manhart, Kurt Schneider	Breaking the Ice for Agile Development of Embedded Software: An Industry Experience Report.	ICSE	2004	DBLP DOI BibTeX RDF
13	A. T. Sivaram, Pascal Pierra, Shida Sheibani, Nancy Wang-Lee, Jorge E. Solorzano, Lily Tran	Active Tester Interface Unit Design For Data Collection.	ITC	2004	DBLP DOI BibTeX RDF
13	Juha Häkkinen, Pekka Syri, Juha-Veikko Voutilainen, Markku Moilanen	A Frequency Mixing and Sub-Sampling Based RF-Measurement Apparatus for IEEE 1149.4.	ITC	2004	DBLP DOI BibTeX RDF
13	Nikos Pitsianis, Gerald G. Pechanek	Indirect VLIW memory allocation for the ManArray multiprocessor DSP.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF
13	Brian White, Jay Lepreau, Shashi Guruprasad	Lowering the barrier to wireless and mobile experimentation.	Comput. Commun. Rev.	2003	DBLP DOI BibTeX RDF
13	Stephan Eberle, Peter Göhner	Adaptive Information Exchange with Field Bus Systems.	ICCSA (1)	2003	DBLP DOI BibTeX RDF
13	Daniele Rossi 0001, S. Cavallotti, Cecilia Metra	Error Correcting Codes for Crosstalk Effect Minimization.	DFT	2003	DBLP DOI BibTeX RDF
13	Martin Schulz 0001, Jie Tao 0001, Jürgen Jeitner, Wolfgang Karl	A proposal for a new hardware cache monitoring architecture.	MSP/ISMM	2002	DBLP DOI BibTeX RDF
13	Kai Richter 0001, Rolf Ernst	Event Model Interfaces for Heterogeneous System Analysis.	DATE	2002	DBLP DOI BibTeX RDF
13	Paul Wielage, Kees Goossens	Networks on Silicon: Blessing or Nightmare?	DSD	2002	DBLP DOI BibTeX RDF
13	Lin Zhong 0001, Niraj K. Jha	Interconnect-aware high-level synthesis for low power.	ICCAD	2002	DBLP DOI BibTeX RDF
13	Daniele Rossi 0001, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra	Coding Scheme for Low Energy Consumption Fault-Tolerant Bus.	IOLTW	2002	DBLP DOI BibTeX RDF
13	Jan-Michael Frahm, Jan-Friso Evers-Senne, Reinhard Koch	Network Protocol for I teraction and Scalable Distributed Visualization.	3DPVT	2002	DBLP DOI BibTeX RDF
13	Rung-Bin Lin, Chi-Ming Tsai	Weight-Based Bus-Invert Coding for Low-Power Applications.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
13	Andrew Shane Huang	Keeping Secrets in Hardware: The Microsoft Xbox™ Case Study.	CHES	2002	DBLP DOI BibTeX RDF
13	Wolfgang Hansmann, Matthias Frank 0001, Michael Wolf	Performance Analysis of TCP Handover in a Wireless/Mobile Multi-Radio Environment.	LCN	2002	DBLP DOI BibTeX RDF
13	Olivier Cozette, Cyril Randriamaro, Gil Utard	Improving Cluster IO Performance with Remote Efficient Access to Distant Device.	LCN	2002	DBLP DOI BibTeX RDF
13	Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Arne Schulz, Enrico Macii, Wolfgang Nebel	Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
13	Paul-Peter Sotiriadis, Anantha P. Chandrakasan	Reducing bus delay in submicron technology using coding.	ASP-DAC	2001	DBLP DOI BibTeX RDF
13	Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	Hierarchical power supply noise evaluation for early power grid design prediction.	SLIP	2001	DBLP DOI BibTeX RDF
13	Vishal Dalal, C. P. Ravikumar	Software Power Optimizations In An Embedded System.	VLSI Design	2001	DBLP DOI BibTeX RDF
13	Vinodh Cuppu, Bruce L. Jacob	Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?.	ISCA	2001	DBLP DOI BibTeX RDF	Systems Application Architecture
13	A. V. Hariharakrishnan, Simon Johney	Validation Platform for a P1394a OHCI-Link Layer Synthesizable Core (With a PCI Bus Interface).	EUROMICRO	2000	DBLP DOI BibTeX RDF
13	Sudhakar Bobba, Ibrahim N. Hajj	High-performance bidirectional repeaters.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
13	Martin L. Griss	Agent-Mediated E-Commerce Agents, Components, Services, Workflow, UML, Java, XML and Games.	TOOLS (34)	2000	DBLP DOI BibTeX RDF	Simulation, Java, XML, UML, Agents, E-commerce, Workflow, Games, Components, Features, Aspects, Product Lines, CBSE
13	Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Novel techniques for bus power consumption reduction in realizations of sum-of-product computation.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
13	Frank Poehl, Walter Anheier	Quality Determination for Gate Delay Fault Tests Considering Three-State Elements.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	ATPG, fault modelling, fault simulation
13	Rajeev Murgai, Masahiro Fujita	On Reducing Transitions Through Data Modifications.	DATE	1999	DBLP DOI BibTeX RDF
13	Peter Thoma	Automotive Electronics - A Challenge For Systems Engineering.	DATE	1999	DBLP DOI BibTeX RDF
13	Pierpaolo Baglietto	Euclidean Distance Transform on a Dedicated Architecture Based on a Reconfigurable Mesh Networ.	ICIAP	1999	DBLP DOI BibTeX RDF
13	Tommy Klevin, Lennart Lindh	Scalable Architecture for Real-Time Applications and Use of Bus-Monitoring.	RTCSA	1999	DBLP DOI BibTeX RDF	bus monitor and multiprocessor systems, real-time system, architecture, real-time kernel
13	Jim Kenney	Co-verification as risk management: minimizing the risk of incorporating a new processor in your next embedded system design.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
13	John Poulton	Problems and Prospects for Electrical Signaling.	ARVLSI	1999	DBLP DOI BibTeX RDF
13	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop	Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems.	DATE	1998	DBLP DOI BibTeX RDF	Real time systems, Embedded systems, System design, Design automation, Performance estimation, Hardware/Software co-design, Process scheduling, System-level synthesis
13	Matthew Moe, Herman Schmit, Seth Copen Goldstein	Characterization and Parameterization of a Pipeline Reconfigurable FPGA.	FCCM	1998	DBLP DOI BibTeX RDF
13	Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop	Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems.	EUROMICRO	1998	DBLP DOI BibTeX RDF
13	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001	Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.	VLSI Design	1998	DBLP DOI BibTeX RDF	Hardware/Software High Level Synthesis, Low Power Design, FIR Filters
13	Jason Cong, Patrick H. Madden	Performance-driven routing with multiple sources.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
13	C. P. Ravikumar, R. Aggarwal, C. Sharma	A Graph-Theoretic Approach for Register File Based Synthesis.	VLSI Design	1997	DBLP DOI BibTeX RDF
13	David R. Engebretsen, Daniel M. Kuchta, Richard C. Booth, John D. Crow, Wayne G. Nation	Parallel Fiber-Optic SCI Links.	IEEE Micro	1996	DBLP DOI BibTeX RDF	fiber optics, SCI-Link (Scalable Coherent Interface-Link), Parallel processing, interconnects
13	Michel Langevin, Eduard Cerny	A recursive technique for computing lower-bound performance of schedules.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	lower-bound on performance, microcode optimization, scheduling, resource constraints, dataflow graph
13	Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin	Some Issues in Gray Code Addressing.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
13	Tom Lovett, Russell M. Clapp	STiNG: A CC-NUMA Computer System for the Commercial Marketplace.	ISCA	1996	DBLP DOI BibTeX RDF
13	Arun K. Jagota	A near-optimal algorithm for gossiping in a d-dimensional mesh bus interconnection network.	IPPS	1995	DBLP DOI BibTeX RDF	near-optimal algorithm, d-dimensional mesh bus interconnection network, geometric characterization, parallel algorithms, multiprocessor interconnection networks, upper bound, gossiping, message transmission
13	Catherine H. Gebotys, Robert J. Gebotys	Optimized mapping of video applications to hardware-software for VLSI architectures.	HICSS (1)	1995	DBLP DOI BibTeX RDF	integer optimization, video computations, video systems, optimized mapping, scheduling, VLSI, optimisation, VLSI architectures, video signal processing, VLIW processor
13	M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
13	Catherine H. Gebotys	An optimization approach to the synthesis of multichip architectures.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
13	Jung-Cheun Lien, Melvin A. Breuer	Test program synthesis for modules and chips having boundary scan.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	Board and system test, test controllers, test program synthesis, built-in self-test, design-for-test, boundary scan
13	Ernst D. Dickmanns	A general dynamic vision architecture for UGV and UAV.	Appl. Intell.	1992	DBLP DOI BibTeX RDF	vision architecture, vehicle guidance, modeling, Machine vision, state estimation
13	Catherine H. Gebotys, Mohamed I. Elmasry	Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis.	DAC	1991	DBLP DOI BibTeX RDF
13	Forrest Brewer, Barry M. Pangrle, Andrew Seawright	Interconnection synthesis with geometric constraints.	MICRO	1990	DBLP BibTeX RDF
13	Daniel Fischer, Yossi Levhari, Gadi Singer	NETHDL: abstraction of schematics to high-level HDL.	EURO-DAC	1990	DBLP DOI BibTeX RDF
13	Jason Cong, Bryan Preas, C. L. Liu 0001	General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design.	DAC	1990	DBLP DOI BibTeX RDF
13	P. A. Subrahmanyam	What's in a Timing Discipline? Considerations in the Specification and Synthesis of Systems with Interacting Asynchronous and Synchronous Components.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
13	Ahmed E. Kamal 0001, Bandula W. Abeysundara	X-NET: A Dual Bus Fiber-Optic LAN Using Active Switches.	SIGCOMM	1989	DBLP DOI BibTeX RDF
13	David R. Cheriton, Hendrik A. Goosen, Patrick D. Boyle	Multi-level Shared Caching Techniques for Scalability in VMP-M/C.	ISCA	1989	DBLP DOI BibTeX RDF
13	José L. Melús, E. Sanvicente, J. Magriñá	Modelling and Performance Evaluation of Multiprocessor Based Packet Switches.	SIGMETRICS	1988	DBLP DOI BibTeX RDF
13	Len Dekker, Edward E. E. Frietman	Optical link and processor clustering in the Delft parallel processor.	ICS	1988	DBLP DOI BibTeX RDF
13	Richard E. Brown	The Kiewit network: a large Apple Talk internetwork.	Comput. Commun. Rev.	1987	DBLP DOI BibTeX RDF
13	Timothy A. Gonsalves, Fouad A. Tobagi	Performance of the Expressnet with Voice/Data Traffic.	SIGMETRICS	1987	DBLP DOI BibTeX RDF
13	Domenico Saccà, Gio Wiederhold	Database Partitioning in a Cluster of Processors.	ACM Trans. Database Syst.	1985	DBLP DOI BibTeX RDF
13	Richard H. Lathrop, Robert S. Kirk	An extensible object-oriented mixed-mod functional simulation system.	DAC	1985	DBLP DOI BibTeX RDF	LISP
13	Douglas J. Theis	Distributed network and multiprocessing minicomputer state-of-the-art capabilities.	AFIPS National Computer Conference	1980	DBLP DOI BibTeX RDF
13	Richard J. Swan, Andreas von Bechtolsheim, Kwok-Woon Lai, John K. Ousterhout	The implementation of the Cm* multi-microprocessor.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
13	G. Jack Lipovski	An organization for optical linkages between integrated circuits.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF