Search results for "clock"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou	Experimental Evaluation of Resonant Clock Distribution.	ISVLSI	2004	DBLP DOI BibTeX RDF
47	Dongsheng Wang 0012, Peter Suaris, Nan-Chi Chou	A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages.	PATMOS	2003	DBLP DOI BibTeX RDF
47	Srigurunath Chakravarthi, Anand Pillai, Jothi P. Neelamegam, Manoj Apte, Anthony Skjellum	A Fine-Grain Clock Synchronization Mechanism for Myrinet Clusters.	LCN	2002	DBLP DOI BibTeX RDF
47	Elie Torbey, John P. Knight	Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
47	Michael Mock, Reiner Frings, Edgar Nett, Spiro Trikaliotis	Continuous Clock Synchronization in Wireless Real-Time Applications.	SRDS	2000	DBLP DOI BibTeX RDF
47	Joe G. Xi, Wayne Wei-Ming Dai	Useful-Skew Clock Routing with Gate Sizing for Low Power Design.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
47	Chuan Lin 0002, Hai Zhou 0001	Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains.	ASP-DAC	2007	DBLP DOI BibTeX RDF	delay padding, prescribed skew domains, optimal skew scheduling algorithm, domain assignment, sequential circuit, flip-flops, memory elements, clock period, clock skew scheduling
47	Guy Even, Ami Litman	Overcoming chip-to-chip delays and clock skews.	ASAP	1996	DBLP DOI BibTeX RDF	chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
47	K. Arvind	Probabilistic Clock Synchronization in Distributed Systems.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	distributedsystems, probability of invalidity, deterministicalgorithm, master-slave scheme, time transmission protocol, distributed processing, probability, synchronisation, clock synchronization, probabilistic algorithm, clock skew, synchronization messages
46	Eric Chun, Zeshan Chishti, T. N. Vijaykumar	Shapeshifter: Dynamically changing pipeline width and speed to address process variations.	MICRO	2008	DBLP DOI BibTeX RDF
46	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
45	Mingoo Seok, David T. Blaauw, Dennis Sylvester	Clock network design for ultra-low power applications.	ISLPED	2010	DBLP DOI BibTeX RDF	ultra-low power, robust design, clock network
45	Sari Onaissi, Khaled R. Heloue, Farid N. Najm	Clock skew optimization via wiresizing for timing sign-off covering all process corners.	DAC	2009	DBLP DOI BibTeX RDF	clock skew optimization, parameterized timing analysis, sign-off, wiresizing, variability
45	Ranan Fraer, Gila Kamhi, Muhammad K. Mhameed	A new paradigm for synthesis and propagation of clock gating conditions.	DAC	2008	DBLP DOI BibTeX RDF	low-power design, clock gating
45	Xu Zhang, Xiaohong Jiang 0001, Susumu Horiguchi	A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	H-Tree, X Architecture, performance evluation, variant X-Tree, clock distribution network
45	Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu	Register binding for clock period minimization.	DAC	2006	DBLP DOI BibTeX RDF	high-level synthesis, clock skew, timing optimization
45	Kun Sun 0001, Peng Ning, Cliff Wang	Fault-Tolerant Cluster-Wise Clock Synchronization for Wireless Sensor Networks.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	wireless sensor networks, fault tolerance, Clock synchronization
45	Guofang Nan, Minqiang Li, Jisong Kou	Multi-level genetic algorithm (MLGA) for the construction of clock binary tree.	GECCO	2005	DBLP DOI BibTeX RDF	genetic algorithms, binary tree, multi-level model, clock routing
45	Kai Wang 0011, Malgorzata Marek-Sadowska	Clock network sizing via sequential linear programming with time-domain analysis.	ISPD	2004	DBLP DOI BibTeX RDF	sequential linear programming, sizing, clock skew, time-domain analysis
45	Young Sik Hong, J. H. No	Clock Synchronization in Wireless Distributed Embedded Applications.	WSTFES	2003	DBLP DOI BibTeX RDF	time transmission protocol, master/slave structure, wireless communication, clock synchronization, distributed embedded system
45	Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott	Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.	HPCA	2002	DBLP DOI BibTeX RDF	Off-Line Analysis Tool, Dynamic Reconfiguration Algorithm, Low Power, Dynamic Voltage and Frequency Scaling, Multiple Clock Domain
45	Baris Taskin, Ivan S. Kourtev	Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	optimization, linear programming, clock skew, cycle stealing
45	Marcelo M. de Azevedo, Douglas M. Blough	Multistep Interactive Convergence: An Efficient Approach to the Fault-Tolerant Clock Synchronization of Large Multicomputers.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	interactive convergence, fault tolerance, multicomputers, Clock synchronization
45	Subhrajit Bhattacharya, Sujit Dey, Franc Brglez	Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	resorce sharing, high-level synthesis, clock period
45	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
44	Kan Takeuchi, Atsushi Yoshikawa 0003, Michio Komoda, Ken Kotani, Hiroaki Matsushita, Yusaku Katsuki, YuyoYamamoto, Takao Sato	Clock-Skew Test Module for Exploring Reliable Clock-Distribution Under Process and Global Voltage-Temperature Variations.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
44	Yanfeng Wang, Qiang Zhou 0001, Xianlong Hong, Yici Cai	Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.	ISCAS	2007	DBLP DOI BibTeX RDF
44	M. B. Maaz, Magdy A. Bayoumi	A non-zero clock skew scheduling algorithm for high speed clock distribution network.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
43	George D. O'Clock, Wendy Strouse Watt	A Model and Simulation With Therapeutic Device-Protocol Design Implications for Acute and Chronic Wounds.	EMBC	2020	DBLP DOI BibTeX RDF
43	George D. O'Clock	Modeling of coupled differential equations for cellular chemical signaling pathways: Implications for assay protocols utilized in cellular engineering.	EMBC	2016	DBLP DOI BibTeX RDF
43	George D. O'Clock	A multi-scale feedback control system model for wound healing electrical activity: Therapeutic device/protocol implications.	EMBC	2014	DBLP DOI BibTeX RDF
43	George D. O'Clock, Yong Wan Lee, Jongwong Lee, Warren J. Warwick	High-Frequency and Low-Frequency Chest Compression: Effects on Lung Water Secretion, Mucus Transport, Heart Rate, and Blood Pressure Using a Trapezoidal Source Pressure Waveform.	IEEE Trans. Biomed. Eng.	2012	DBLP DOI BibTeX RDF
43	George D. O'Clock, Yong Wan Lee, Jongwong Lee, Warren J. Warwick	A Simulation Tool to Study High-Frequency Chest Compression Energy Transfer Mechanisms and Waveforms for Pulmonary Disease Applications.	IEEE Trans. Biomed. Eng.	2010	DBLP DOI BibTeX RDF
43	George D. O'Clock, Donald L. Henderson	Design and Analysis of Data Communication Systems.	Int. J. Netw. Manag.	1994	DBLP DOI BibTeX RDF
43	Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li 0001	Accurate clock mesh sizing via sequential quadraticprogramming.	ISPD	2010	DBLP DOI BibTeX RDF	optimization, sequential quadratic programming
43	Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou 0001	Improve clock gating through power-optimal enable function selection.	DDECS	2009	DBLP DOI BibTeX RDF
43	Vinayak Honkote, Baris Taskin	Zero clock skew synchronization with rotary clocking technology.	ISQED	2009	DBLP DOI BibTeX RDF
43	Arjun Kapoor, Nikhil Jayakumar, Sunil P. Khatri	Dynamically De-Skewable Clock Distribution Methodology.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
43	Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
43	Jeff Mueller, Resve A. Saleh	Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance.	VLSI Design	2008	DBLP DOI BibTeX RDF
43	Julien Lamoureux, Steven J. E. Wilton	Clock-Aware Placement for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
43	Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang	Skew aware polarity assignment in clock tree.	ICCAD	2007	DBLP DOI BibTeX RDF
43	Atanu Chattopadhyay, Zeljko Zilic	Reconfigurable Clock Distribution Circuitry.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud	Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers.	ISQED	2007	DBLP DOI BibTeX RDF
43	Sherif A. Tawfik, Volkan Kursun	Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.	ISQED	2007	DBLP DOI BibTeX RDF
43	Zhengtao Yu 0002, Xun Liu	Power Analysis of Rotary Clock.	ISVLSI	2005	DBLP DOI BibTeX RDF
43	Min Pan, Chris C. N. Chu, J. Morris Chang	Transition time bounded low-power clock tree construction.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
43	Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh	Floorplanning with clock tree estimation.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
43	Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera	Statistical Analysis of Clock Skew Variation in H-Tree Structure.	ISQED	2005	DBLP DOI BibTeX RDF
43	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Low Cost Scheme for On-Line Clock Skew Compensation.	VTS	2005	DBLP DOI BibTeX RDF
43	Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu	Race-condition-aware clock skew scheduling.	DAC	2005	DBLP DOI BibTeX RDF	sequential circuits, high performance, timing optimization
43	Aseem Agarwal, Vladimir Zolotov, David T. Blaauw	Statistical clock skew analysis considering intradie-process variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
43	Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng	A multiple level network approach for clock skew minimization with process variations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
43	Y. Elboim, Avinoam Kolodny, Ran Ginosar	A clock-tuning circuit for system-on-chip.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
43	Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman	Reduced Delay Uncertainty in High Performance Clock Distribution Networks.	DATE	2003	DBLP DOI BibTeX RDF
43	Aseem Agarwal, David T. Blaauw, Vladimir Zolotov	Statistical Clock Skew Analysis Considering Intra-Die Process Variations.	ICCAD	2003	DBLP DOI BibTeX RDF
43	A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl	Electrical and optical clock distribution networks for gigascale microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
43	Anoop Iyer, Diana Marculescu	Power efficiency of voltage scaling in multiple clock, multiple voltage cores.	ICCAD	2002	DBLP DOI BibTeX RDF
43	Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser	Clock skew verification in the presence of IR-drop in the powerdistribution network.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
43	Xiaohong Jiang 0001, Susumu Horiguchi	Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model.	DFT	2000	DBLP DOI BibTeX RDF
43	Zhaoyun Xing, Prithviraj Banerjee	A parallel algorithm for zero skew clock tree routing.	ISPD	1998	DBLP DOI BibTeX RDF
43	Keith M. Carrig, Albert M. Chu, Frank D. Ferraiolo, John G. Petrovick, P. Andrew Scott, Richard J. Weiss	A Clock Methodology for High-Performance Microprocessors.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
43	Uri Frank, Tsachy Kapschitz, Ran Ginosar	A predictive synchronizer for periodic clock domains.	Formal Methods Syst. Des.	2006	DBLP DOI BibTeX RDF	Predictive Synchronizer, Multiple Clock Domains (MCD), Formal Verification, Systems on Chip (SoC), Clock Synchronization, Metastability
43	Cecilia Metra, Stefano Di Francescantonio, T. M. Mak	Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	clock faults, Testing, clock distribution network, manufacturing test
43	Ali Kanso	More Generalized Clock-Controlled Alternating Step Generator.	ACNS	2004	DBLP DOI BibTeX RDF	Clock-Controlled Registers, Alternating Step Generator and Clock-Controlled Alernating Step Generator, Stream Ciphers
43	Sandeep Kumar Goel, Bart Vermeulen	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
42	Isamu Tsuneizumi, Ailixier Aikebaier, Tomoya Enokido, Makoto Takizawa 0001	A flexible group communication protocol with hybrid clocks.	MoMM	2009	DBLP DOI BibTeX RDF
42	Sei Hyung Jang	A new synchronous mirror delay with an auto-skew-generation circuit.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
42	Frank Grassert, Dirk Timmermann	Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
42	Nithya Raghavan, Venkatesh Akella, Smita Bakshi	Automatic Insertion of Gated Clocks at Register Transfer Level.	VLSI Design	1999	DBLP DOI BibTeX RDF
41	Fabian Kuhn, Christoph Lenzen 0001, Thomas Locher, Rotem Oshman	Optimal gradient clock synchronization in dynamic networks.	PODC	2010	DBLP DOI BibTeX RDF	clock synchronization, dynamic networks
41	Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu	Logic synthesis for low power using clock gating and rewiring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, logic synthesis, clock gating
41	Tak-Yung Kim, Taewhan Kim	Clock tree synthesis with pre-bond testability for 3D stacked IC designs.	DAC	2010	DBLP DOI BibTeX RDF	optimization, routing, buffer insertion, 3D ICs, clock tree
41	Chrisil Arackaparambil, Sergey Bratus, Anna Shubina, David Kotz	On the reliability of wireless fingerprinting using clock skews.	WISEC	2010	DBLP DOI BibTeX RDF	fake access point, mac address spoofing, wireless, ieee 802.11, fingerprinting, clock skew, timestamp
41	Anthony Rowe 0001, Vikram Gupta, Ragunathan Rajkumar	Low-power clock synchronization using electromagnetic energy radiating from AC power lines.	SenSys	2009	DBLP DOI BibTeX RDF	hardware clock synchronization, wireless sensor networks, sensor networks, synchronization
41	Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert	Ispd2009 clock network synthesis contest.	ISPD	2009	DBLP DOI BibTeX RDF	benchmarks, physical design, vlsi, clock network synthesis
41	Jaehan Lee, Jang-Sub Kim, Erchin Serpedin	Clock Offset Estimation in Wireless Sensor Networks Using Bootstrap Bias Correction.	WASA	2008	DBLP DOI BibTeX RDF	Bias Correction, Wireless Sensor Networks, Bootstrap, Clock Synchronization
41	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
41	Dong Zhou, Ten-Hwang Lai	An Accurate and Scalable Clock Synchronization Protocol for IEEE 802.11-Based Multihop Ad Hoc Networks.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	scalability, MANET, IEEE 802.11, clock synchronization
41	Rupesh S. Shelar	An efficent clustering algorithm for low power clock tree synthesis.	ISPD	2007	DBLP DOI BibTeX RDF	clustering, low power, clock tree synthesis
41	Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi 0001	A fast clock scheduling for peak power reduction in LSI.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	general-synchronous framework, peak power reduction, power consumption estimation, clock scheduling
41	Mahyar R. Malekpour	A Byzantine-Fault Tolerant Self-stabilizing Protocol for Distributed Clock Synchronization Systems.	SSS	2006	DBLP DOI BibTeX RDF	fault tolerant, algorithm, model checking, verification, protocol, distributed, self-stabilization, clock synchronization, Byzantine
41	Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara	Power-constrained test scheduling for multi-clock domain SoCs.	DATE	2006	DBLP DOI BibTeX RDF	multi-clock domain SoC, power consumption, test scheduling, test access mechanism
41	Uday Padmanabhan, Janet Meiling Wang, Jiang Hu	Statistical clock tree routing for robustness to process variations.	ISPD	2006	DBLP DOI BibTeX RDF	routing, robustness, process variations, clock tree
41	Anand Rajaram, David Z. Pan, Jiang Hu	Improved algorithms for link-based non-tree clock networks for skew variability reduction.	ISPD	2005	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
41	Shlomi Dolev, Jennifer L. Welch	Self-stabilizing clock synchronization in the presence of Byzantine faults.	J. ACM	2004	DBLP DOI BibTeX RDF	self-stabilization, clock synchronization, Byzantine failures
41	Hans M. Jacobson	Improved clock-gating through transparent pipelining.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating
41	Hechmi Khlifi, Jean-Charles Grégoire	Estimation and Removal of Clock Skew From Delay Measures.	LCN	2004	DBLP DOI BibTeX RDF	clock skew, delay measurement
41	Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong	Design of a 10GHz clock distribution network using coupled standing-wave oscillators.	DAC	2003	DBLP DOI BibTeX RDF	distributed oscillators, on-chip phase measurement, resonant clocking, salphasic, standing wave, clock distribution, coupled oscillators
41	Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò	On-Chip Clock Faults' Detector.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	clock faults, systems-on-a-chip, on-line testing
41	David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Impact of Technology Scaling in the Clock System Power.	ISVLSI	2002	DBLP DOI BibTeX RDF	Clock Power, Low-power-design, Power modeling, Technology Scaling
41	J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir	A Heuristic for Clock Selection in High-Level Synthesis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	clock selection, heuristics, high-level synthesis, design space exploration, graph structure
41	Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar	A hierarchical decomposition methodology for multistage clock circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	performance driven router, routing, process variations, manufacturability, clock
40	Conrado Daws, Sergio Yovine	Reducing the number of clock variables of timed automata.	RTSS	1996	DBLP DOI BibTeX RDF	clock variable number reduction, active clock detection, equal clock detection, memory space reduction, real-time systems, real time systems, verification, case studies, timed automata, bisimulation, experimental results, system evolution
40	Minsoo Ryu, Jungkeun Park, Seongsoo Hong	Timing Constraint Remapping to Achieve Time Equi-Continuity in Distributed Real-Time Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	timing constraint transformation, real-time scheduling, clock synchronization, Distributed real-time system
39	Jeff Mueller, Resve A. Saleh	A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks.	ISQED	2008	DBLP DOI BibTeX RDF
39	Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas	A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
39	Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid	Clock-frequency assignment for multiple clock domain systems-on-a-chip.	DATE	2007	DBLP DOI BibTeX RDF
39	Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou	A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
39	Jui-Hao Chiang, Tzi-cker Chiueh	Accurate Clock Synchronization for IEEE 802.11-Based Multi-Hop Wireless Networks.	ICNP	2009	DBLP DOI BibTeX RDF