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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14306 occurrences of 4820 keywords
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Results
Found 45278 publication records. Showing 45278 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
31 | Alain J. Martin |
The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program Transformation. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
|
31 | Steffen Lange |
A program synthesis algorithm exemplified. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
31 | Klaus P. Jantke |
An algebraic framework for inductive program synthesis. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
31 | Ognian Botusharov |
Learning on the basis of a polynomial pattern synthesis algorithm. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
31 | Rolf Wiehagen |
How fast is program synthesis from examples. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
31 | Gisela Schäfer |
Some results in the theory of effective program synthesis: learning by defective information. |
Mathematical Methods of Specification and Synthesis of Software Systems |
1985 |
DBLP DOI BibTeX RDF |
|
31 | Greg Stitt, Frank Vahid |
Thread warping: a framework for dynamic synthesis of thread accelerators. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
dynamic synthesis, thread warping, warp processing, FPGA, synthesis, multi-core, threads, just-in-time compilation |
31 | Andreas Hamfelt, Jørgen Fischer Nilsson |
Inductive Synthesis of Logic Programs by Composition of Combinatory Program Schemes. |
LOPSTR |
1998 |
DBLP DOI BibTeX RDF |
logic program schemata, logical combinators, synthesis by composition and specialization of schemas, inductive synthesis, metalogic program environment |
31 | Wen-Jong Fang, Allen C.-H. Wu |
Multiway FPGA partitioning by fully exploiting design hierarchy. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
fine-grained synthesis, functional clustering, multi-way partitioning, multiple-FPGA synthesis |
31 | Toshiyuki Kimura, Munenori Naoe, Yoko Yamakata, Michiaki Katsumoto |
Subjective effect of synthesis conditions in 3D sound field reproduction system using a few transducers and wave field synthesis. |
IUCS |
2009 |
DBLP DOI BibTeX RDF |
microphone directivity, sound field reproduction, wave field synthesis |
31 | Sandeep S. Kulkarni, Borzoo Bonakdarpour, Ali Ebnenasir |
Mechanical Verification of Automatic Synthesis of Fault-Tolerant Programs. |
LOPSTR |
2004 |
DBLP DOI BibTeX RDF |
Addition of faulttolerance, Fault-tolerance, Program transformation, Theorem proving, Program synthesis, PVS, Mechanical verification |
31 | Oliver Bringmann 0001, Wolfgang Rosenstiel, Carsten Menn |
Controller Estimation for FPGA Target Architectures during High-Level Synthesis. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
FPGA, controller, high-level synthesis, area estimation |
31 | Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith |
SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
System design, hardware/software codesign |
31 | Rajesh K. Gupta 0001, Sandeep K. Shukla, Nick Savoiu |
Efficient Simulation of Synthesis-Oriented System Level Designs. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
simulation, SystemC, system-level design |
31 | Jörg Henkel, Rolf Ernst, Ulrich Holtmann, Thomas Benner |
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
30 | Balakrishnan Iyer, Ramesh Karri, Israel Koren |
Phantom redundancy: a high-level synthesis approach for manufacturability. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
fabrication-time reconfigurability, functional unit failure, microarchitecture synthesis, phantom redundancy, genetic algorithm, high level synthesis, high-level synthesis, redundancy, logic design, reconfigurable architectures, manufacturability, microarchitecture, circuit CAD |
30 | Jay K. Adams, John Alan Miller, Donald E. Thomas |
Execution-time profiling for multiple-process behavioral synthesis. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model |
30 | Mahsa Vahidi, Alex Orailoglu |
Testability metrics for synthesis of self-testable designs and effective test plans. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs |
30 | Enric Musoll, Jordi Cortadella |
Scheduling and resource binding for low power. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding |
30 | F. Keith Hanna, Neil Daeche, Mark Longley |
Veritas+: A Specification Language Based on Type Theory. |
Hardware Specification, Verification and Synthesis |
1989 |
DBLP DOI BibTeX RDF |
Formal verification, Specification languages, Type theory |
30 | Howard Zhou, Jie Sun 0004, Greg Turk, James M. Rehg |
Terrain Synthesis from Digital Elevation Models. |
IEEE Trans. Vis. Comput. Graph. |
2007 |
DBLP DOI BibTeX RDF |
Terrain synthesis, terrain analysis, texture synthesis, Digital Elevation Models |
30 | Borzoo Bonakdarpour, Sandeep S. Kulkarni, Fuad Abujarad |
Distributed Synthesis of Fault-Tolerant Programs in the High Atomicity Model. |
SSS |
2007 |
DBLP DOI BibTeX RDF |
Parallel synthesis, Fault-tolerance, Distributed algorithms, Program transformation, Program synthesis |
30 | Andrew Ireland, Jamie Stark |
Combining Proof Plans with Partial Order Planning for Imperative Program Synthesis. |
Autom. Softw. Eng. |
2006 |
DBLP DOI BibTeX RDF |
partial order planning, deductive synthesis, program synthesis, proof planning |
30 | Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton |
A General Purpose Behavioural Asynchronous Synthesis System. |
ASYNC |
2004 |
DBLP DOI BibTeX RDF |
Behavioural synthesis, asynchronous synthesis, cryptography |
30 | Pao-Ann Hsiung |
POSE: a parallel object-oriented synthesis environment. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
design-completion check, synthesis rollback, object-oriented technology, hardware synthesis, parallel design |
30 | Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel |
Verification by Simulation Comparison using Interface Synthesis. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Simulation Comparison, Verification, High-Level Synthesis, Interface Synthesis |
30 | Oliver Bringmann 0001, Wolfgang Rosenstiel |
Cross-Level Hierarchical High-Level Synthesis. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Hierarchical Synthesis, Complex Components, High-Level Synthesis |
30 | Bhed Bahadur Bista, Kaoru Takahashi, Hiroaki Kaminaga, Norio Shiratori |
A flexible protocol synthesis method for adopting requirement changes. |
ICPADS |
1996 |
DBLP DOI BibTeX RDF |
flexible protocol synthesis method, requirement changes adoption, communicating entities, maintenance issue, protocol synthesis method, formal specification language LOTOS, formal specification, protocols, software maintenance, specification languages, protocol specification |
30 | Robert B. Norwood, Edward J. McCluskey |
Synthesis-for-scan and scan chain ordering. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications |
30 | Kaushik De, John A. Chandy, Sumit Roy 0003, Steven Parkes, Prithviraj Banerjee |
Parallel algorithms for logic synthesis using the MIS approach. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
combinational logic synthesis, VLSI system design, ProperMIS, portable parallel algorithm, parallel algorithms, parallel algorithms, parallel architectures, logic design, combinational circuits, logic synthesis, logic CAD |
30 | Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal |
Finite state machine synthesis with fault tolerant test function. |
J. Electron. Test. |
1993 |
DBLP DOI BibTeX RDF |
Design for combinational test generation, finite state machine synthesis, test function embedding, synthesis for testability, fault-tolerant design |
30 | Javier Esparza, Manuel Silva Suárez |
On the analysis and synthesis of free choice systems. |
Applications and Theory of Petri Nets |
1989 |
DBLP DOI BibTeX RDF |
free choice nets, linear algebra techniques, state refinement, structure of systems, modular synthesis, top-down synthesis, Analysis, transformation, reduction |
29 | Wencheng Wang, Feitong Liu, Peijie Huang, Enhua Wu |
Texture synthesis via the matching compatibility between patches. |
Sci. China Ser. F Inf. Sci. |
2009 |
DBLP DOI BibTeX RDF |
texture patch, large textures, match, texture synthesis |
29 | Hyunh Van Luong, Sangjin Cho, Jong-Myon Kim, Uipil Chong |
Real-Time Sound Synthesis of Plucked String Instruments Using a Data Parallel Architecture. |
ICIC (1) |
2009 |
DBLP DOI BibTeX RDF |
Music synthesis, Plucked-string instrument, Data parallel architectures, Parallel processing, Physical modeling |
29 | Xin Chen, Wencheng Wang |
Texture synthesis by interspersing patches in a chessboard pattern. |
VRCAI |
2009 |
DBLP DOI BibTeX RDF |
large textures, real-time synthesis, GPU |
29 | Paul Merrell |
Example-based model synthesis. |
SI3D |
2007 |
DBLP DOI BibTeX RDF |
texture synthesis, procedural modeling |
29 | Junhyung Um, Taewhan Kim |
Resource Sharing Combined with Layout Effects in High-Level Synthesis. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
resource allocation, high-level synthesis, layout |
29 | Holger Giese, Stefan Henkler, Martin Hirsch 0001, Florian Klein 0001 |
Nobody's perfect: interactive synthesis from parametrized real-time scenarios. |
SCESM |
2006 |
DBLP DOI BibTeX RDF |
scenario-based synthesis, model checking, patterns, diagnosis |
29 | Steve Roach, Jeffrey Van Baalen |
Automated Procedure Construction for Deductive Synthesis. |
Autom. Softw. Eng. |
2005 |
DBLP DOI BibTeX RDF |
synthesis, procedures, deductive, decision, partial deduction |
29 | Catherine Blake |
Information synthesis: a new approach to explore secondary information in scientific literature. |
JCDL |
2005 |
DBLP DOI BibTeX RDF |
information synthesis, information retrieval, information extraction, text mining, document summarization |
29 | Xinguo Liu, Yaohua Hu, Jingdan Zhang, Xin Tong 0001, Baining Guo, Heung-Yeung Shum |
Synthesis and Rendering of Bidirectional Texture Functions on Arbitrary Surfaces. |
IEEE Trans. Vis. Comput. Graph. |
2004 |
DBLP DOI BibTeX RDF |
texture mapping, texture synthesis, surfaces, Bidirectional texture function, reflectance and shading models, mesh parameterization |
29 | Sumit Gupta, Rajesh K. Gupta 0001, Nikil D. Dutt, Alexandru Nicolau |
Coordinated parallelizing compiler optimizations and high-level synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
dynamic CSE, parallelizing transformations, presynthesis, embedded systems, high-level synthesis, Code motions, common subexpression elimination |
29 | Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri |
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
genetic algorithms, branch-and-bound, performance estimation, VHDL-AMS, Analog synthesis |
29 | Kai Kapp, Viktor K. Sabelfeld |
Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
scheduling, transformational design, formal synthesis |
29 | Kiam Tian Seow, Chuan Ma, Makoto Yokoo |
Multiagent Planning as Control Synthesis. |
AAMAS |
2004 |
DBLP DOI BibTeX RDF |
Discrete-Event Control Synthesis, Multiagent Planning, Multiagent Coordination |
29 | Tatsuo Yotsukura, Shigeo Morishima, Satoshi Nakamura 0001 |
Model-based talking face synthesis for anthropomorphic spoken dialog agent system. |
ACM Multimedia |
2003 |
DBLP DOI BibTeX RDF |
anthropomorphic dialog agent, face image synthesis, facial animation, lip synchronization |
29 | Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas |
Bounding the efforts on congestion optimization for physical synthesis. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
optimization, logic synthesis, physical design, technology mapping, routing congestion |
29 | Navin Vemuri, Priyank Kalla, Russell Tessier |
BDD-based logic synthesis for LUT-based FPGAs. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
FPGA, decomposition, logic synthesis, BDD |
29 | Ing-Jer Huang |
Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
compiler instruction optimization, instruction set processor, pipeline hazards, pipeline taxonomy, synthesis |
29 | Li-Yi Wei, Marc Levoy |
Fast texture synthesis using tree-structured vector quantization. |
SIGGRAPH |
2000 |
DBLP DOI BibTeX RDF |
image processing, texture synthesis, compression algorithms |
29 | Arvind Rajawat, M. Balakrishnan, Anshul Kumar |
nterface Synthesis: Issues and Approaches. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Codesign methodology, Interface optimization, Communication protocols, Interface synthesis |
29 | Rastislav Bodík |
Algorithmic Program Synthesis with Partial Programs and Decision Procedures. |
SAS |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler |
Reversible Logic Synthesis with Output Permutation. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Almitra Pradhan, Ranga Vemuri |
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick |
Adaptive chip-package thermal analysis for synthesis and design. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Xuejie Qin, Yee-Hong Yang |
Basic Gray Level Aura Matrices: Theory and its Application to Texture Synthesis. |
ICCV |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Ioannis A. Ypsilos, Adrian Hilton 0001, Aseel Turkmani, Philip J. B. Jackson |
Speech-Driven Face Synthesis from 3D Video. |
3DPVT |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Steve Roach, Jeffrey Van Baalen |
Experience Report on Automated Procedure Construction for Deductive Synthesis. |
ASE |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Makoto Nakashizuka, Hisakazu Kikuchi |
Edge-based image synthesis model and its application to image coding. |
ISCAS (4) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Reinaldo A. Bergamaschi, Andreas Kuehlmann |
A system for production use of high-level synthesis. |
IEEE Trans. Very Large Scale Integr. Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Ingo Sander, Axel Jantsch, Zhonghai Lu |
A Case Study of Hardware and Software Synthesis in ForSyDe. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
system design, design methodology, software synthesis, hardware synthesis |
28 | Min Xu, Fadi J. Kurdahi |
Layout-Driven RTL Binding Techniques for High-Level Synthesis. |
ISSS |
1996 |
DBLP DOI BibTeX RDF |
layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process |
28 | Preeti Ranjan Panda, Nikil D. Dutt |
1995 high level synthesis design repository. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units |
28 | Levent Aksoy, Diego Jaccottet, Eduardo Costa 0001 |
Design of low complexity digital FIR filters. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
low-level synthesis, multiple constant multiplications, multiplierless filter design, high-level synthesis, array multipliers |
28 | Michal Irani, Tal Hassner, P. Anandan 0001 |
What Does the Scene Look Like from a Scene Point? |
ECCV (2) |
2002 |
DBLP DOI BibTeX RDF |
Novel-view synthesis, Synthesis without structure or motion |
28 | Felix Reimann, Michael Glaß, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich |
Symbolic voter placement for dependability-aware system synthesis. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
mttuf, bdd, system synthesis, voter, mean time to failure, mttf |
28 | Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, Li Shang |
Reliable multiprocessor system-on-chip synthesis. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
synthesis, multiprocessor system-on-chip, thermal |
28 | Brett H. Meyer, Donald E. Thomas |
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
bus architecture synthesis, embedded multiprocessor systems-on-chip, partitioning, sharing, memory allocation, data mapping |
28 | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt |
System-level power-performance trade-offs in bus matrix communication architecture synthesis. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs |
28 | Oliver Bringmann 0001, Wolfgang Rosenstiel, Axel Siebenborn |
Conflict analysis in multiprocess synthesis for optimized system integration. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
scheduling, systems-on-chip, system level design, concurrent systems, binding, behavioral synthesis |
28 | Pai H. Chou, Ross B. Ortega, Gaetano Borriello |
The Chinook hardware/software co-synthesis system. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
Chinook hardware/software co-synthesis system, custom logic, design co-simulation, design time constraints, embedded controller design, error-prone tasks, function migration, interface hardware, interface software, system components integration, real-time systems, software tools, logic design, microprocessors, logic CAD, microcontrollers, computer-aided design tools |
28 | Fuad Abujarad, Sandeep S. Kulkarni |
Multicore Constraint-Based Automated Stabilization. |
SSS |
2009 |
DBLP DOI BibTeX RDF |
Multicore Algorithms, Stabilization, Program Transformation, Distributed Programs, Program Synthesis |
27 | Katsuyuki Kamei, Minoru Maruyama, Kazuo Seo |
Scene Synthesis by Assembling Striped Areas of Source Images. |
ICIP (2) |
1997 |
DBLP DOI BibTeX RDF |
striped areas assembling, source images, image-based rendering method, scene synthesis, memory data management, walkthrough operations, flythrough system, real time, virtual environment, image synthesis, rendering (computer graphics), view synthesis |
26 | Chen Liu 0013, Chengmo Yang |
Defense Against Hardware Trojan Collusion in MPSoCs. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Sheikh Ariful Islam, Srinivas Katkoori |
Hardware Trojan Localization: Modeling and Empirical Approach. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat |
Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Mike Borowczak, Ranga Vemuri |
S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Srinivas Katkoori, Sheikh Ariful Islam |
Introduction and Background. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Nandeesha Veeranna, Benjamin Carrion Schafer |
Source Code Obfuscation of Behavioral IPs: Challenges and Solutions. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Matthew Lewandowski, Srinivas Katkoori |
State Encoding Based Watermarking of Sequential Circuits Using Hybridized Darwinian Genetic Algorithm. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Pranesh Santikellur, Rajat Subhra Chakraborty, Swarup Bhunia |
Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Farhath Zareen, Robert Karam |
A Framework for Detecting Hardware Trojans in RTL Using Artificial Immune Systems. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Richa Agrawal, Ranga Vemuri |
Encoding of Finite-State Controllers for Graded Security and Power. |
Behavioral Synthesis for Hardware Security |
2022 |
DBLP DOI BibTeX RDF |
|
26 | Ernst-Rüdiger Olderog, Bernhard Steffen, Wang Yi 0001 (eds.) |
Model Checking, Synthesis, and Learning - Essays Dedicated to Bengt Jonsson on The Occasion of His 60th Birthday |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Anthony W. Lin, Philipp Rümmer |
Regular Model Checking Revisited. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Giovanni Bacci 0001, Benoît Delahaye, Kim G. Larsen, Anders Mariegaard |
Quantitative Analysis of Interval Markov Chains. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Markus Frohme, Bernhard Steffen |
Never-Stop Context-Free Learning. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Manuel Gieseking, Ernst-Rüdiger Olderog |
High-Level Representation of Benchmark Families for Petri Games. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Simon Dierl, Falk Howar |
A Taxonomy and Reductions for Common Register Automata Formalisms. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Jakaria Abdullah, Wang Yi 0001 |
Cause-Effect Reaction Latency in Real-Time Systems. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Tiziana Margaria, Alexander Schieweck |
Towards Engineering Digital Twins by Active Behaviour Mining. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Yih-Kuen Tsay, Moshe Y. Vardi |
From Linear Temporal Logics to Büchi Automata: The Early and Simple Principle. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Parosh Aziz Abdulla |
Regular Model Checking: Evolution and Perspectives. |
Model Checking, Synthesis, and Learning |
2021 |
DBLP DOI BibTeX RDF |
|
26 | Tsutomu Sasao, Jon T. Butler |
Decomposition of Index Generation Functions Using a Monte Carlo Method. |
Advanced Logic Synthesis |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Yu-Yun Dai, Robert K. Brayton |
Identifying Transparent Logic in Gate-Level Circuits. |
Advanced Logic Synthesis |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Xuesong Peng, Weikang Qian |
A Branch-and-Bound-Based Minterm Assignment Algorithm for Synthesizing Stochastic Circuit. |
Advanced Logic Synthesis |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Yi-Shan Lu, Keshav Pingali |
Can Parallel Programming Revolutionize EDA Tools? |
Advanced Logic Synthesis |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Rafael Trapani Possignolo, Elnaz Ebrahimi 0001, Haven Blake Skinner, Jose Renau |
Automated Pipeline Transformations with Fluid Pipelines. |
Advanced Logic Synthesis |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler, Priyank Kalla |
Emerging Circuit Technologies: An Overview on the Next Generation of Circuits. |
Advanced Logic Synthesis |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, Paolo Ienne |
Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. |
Advanced Logic Synthesis |
2018 |
DBLP DOI BibTeX RDF |
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