Search results for "coprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
32	Andrew Morton, Wayne M. Loucks	A hardware/software kernel for system on chip designs.	SAC	2004	DBLP DOI BibTeX RDF	operating systems, SoC, hardware/software codesign
32	Yuan C. Chou, John Paul Shen	Instruction path coprocessors.	ISCA	2000	DBLP DOI BibTeX RDF
32	Marcel-Catalin Rosu, Karsten Schwan, Richard Fujimoto	Supporting Parallel Applications on Clusters of Workstations: The Intelligent Network Interface Approach.	HPDC	1997	DBLP DOI BibTeX RDF	intelligent network interface, performance, parallel architectures, networking architecture, high speed network, parallel applications, clusters of workstations, low overhead
32	Johan Stärner, Joakim Adomat, John Furunäs, Lennart Lindh	Real-Time Scheduling Co-Processor in Hardware for Single and Multiprocessor Systems.	EUROMICRO	1996	DBLP DOI BibTeX RDF	real-time scheduling co-processor, predictable time behaviour, digital chip, Real-Time Unit, global resources, task synchronisation, multiprocessor systems, timing analysis, processor scheduling
32	H. Pottinger, W. Eatherton, J. Kelly, T. Schiefelbein, L. R. Mullin, R. Ziegler	Hardware Assists for High Performance Computing Using a Mathematics of Arrays.	FPGA	1995	DBLP DOI BibTeX RDF
29	Nikos Anastasiadis, Isidoros Sideris, Kiamal Z. Pekmestzi	A fast multiplier-less edge detection accelerator for FPGAs.	SAC	2010	DBLP DOI BibTeX RDF	FPGA, edge detection, coprocessor, FSL
29	Jason Cong, Karthik Gururaj, Guoling Han	Synthesis of reconfigurable high-performance multicore systems.	FPGA	2009	DBLP DOI BibTeX RDF	coprocessor synthesis, reconfigurable high-performance computing, design space exploration
29	Peiheng Zhang, Guangming Tan, Guang R. Gao	Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform.	HPRCTA	2007	DBLP DOI BibTeX RDF	reconfigurable supercomputing, FPGA, coprocessor, Smith-Waterman algorithm
29	Howon Kim 0001, Mun-Kyu Lee, Dong Kyue Kim, Sang-Kyoon Chung, Kyoil Chung	Design and Implementation of Crypto Co-processor and Its Application to Security Systems.	CIS (2)	2005	DBLP DOI BibTeX RDF	Crypto Algorithm, Power Consumption, Crypto Coprocessor
29	Chenghuai Lu, André L. M. dos Santos, Francisco R. Pimentel	Implementation of fast RSA key generation on smart cards.	SAC	2002	DBLP DOI BibTeX RDF	RSA key generation, prime finding, smart card, coprocessor
29	M. Ernst, Michael Jung 0002, Felix Madlener, Sorin A. Huss, Rainer Blümel	A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n).	CHES	2002	DBLP DOI BibTeX RDF	$ mathbb {GF}(2^n)$ arithmetic, Karatsuba multiplication, VHDL model generator, coprocessor synthesis, FPGA hardware acceleration, Atmel FPSLIC platform, Elliptic Curve cryptography
29	Johann Großschädl	A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m).	CHES	2001	DBLP DOI BibTeX RDF	iterative modulo multiplication, polynomial basis representation, bit-serial multiplier architecture, smart card crypto-coprocessor, Elliptic curve cryptography, finite field arithmetic
29	Luis Alejandro Cortés, Petru Eles, Zebo Peng	Definitions of Equivalence for Transformational Synthesis of Embedded Systems.	ICECCS	2000	DBLP DOI BibTeX RDF	transformational synthesis, PRES+, explicit notion, Ethernet network coprocessor, embedded systems, Petri nets, computational model, equivalence, embedded systems design, data transformation, formal notation, design cycles, complex task
27	Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi	A dynamically configurable coprocessor for convolutional neural networks.	ISCA	2010	DBLP DOI BibTeX RDF	dynamic reconfiguration, parallel computer architecture, convolutional neural networks
27	Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu	Multithreaded coprocessor interface for multi-core multimedia SoC.	ASP-DAC	2008	DBLP DOI BibTeX RDF
27	Reza Ebrahimi Atani, Sattar Mirzakuchaki, Shahabaddin Ebrahimi Atani	Design and Implementation of an Image CoProcessor.	ICISP	2008	DBLP DOI BibTeX RDF
27	Chen Huang 0005, Frank Vahid	Dynamic coprocessor management for FPGA-enhanced compute platforms.	CASES	2008	DBLP DOI BibTeX RDF	coprocessing, online algorithms., FPGAs, dynamic optimization, acceleration, runtime configuration
27	Kehuai Wu, Jan Madsen	COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems.	ICSAMOS	2007	DBLP DOI BibTeX RDF
27	Mohammad Amin Amiri, Reza Ebrahimi Atani, Sattar Mirzakuchaki, Mojdeh Mahdavi	Design and Implementation of a 50MHZ DXT CoProcessor.	DSD	2007	DBLP DOI BibTeX RDF
27	Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle	DynaCORE - A Dynamically Reconfigurable Coprocessor Architecture for Network Processors.	PDP	2006	DBLP DOI BibTeX RDF
27	Xue-mi Zhao, Zhiying Wang 0003, Hongyi Lu, Kui Dai	A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
27	Gianmarco Angius, Cristian Manca, Danilo Pani, Luigi Raffo	Cooperative VLSI Tiled Architectures: Stigmergy in a Swarm Coprocessor.	ANTS Workshop	2006	DBLP DOI BibTeX RDF
27	Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat	Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards.	ASAP	2006	DBLP DOI BibTeX RDF
27	Antonio Di Stefano, G. Costantino Giaconia	An FPGA-Based Adaptive Fuzzy Coprocessor.	IWANN	2005	DBLP DOI BibTeX RDF
27	Walter Stechele, L. Alvado Cárcel, Stephan Herrmann 0002, J. Lidón Simón	A Coprocessor for Accelerating Visual Information Processing.	DATE	2005	DBLP DOI BibTeX RDF
27	Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Yuan-Cheng Lai	A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering Coprocessor.	ASAP	2005	DBLP DOI BibTeX RDF
27	Elena Trichina, Tymur Korkishko, Kyung-Hee Lee	Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results.	AES Conference	2004	DBLP DOI BibTeX RDF
27	Harald Aigner, Holger Bock, Markus Hütter, Johannes Wolkerstorfer	A Low-Cost ECC Coprocessor for Smartcards.	CHES	2004	DBLP DOI BibTeX RDF	multiplicative inverse, digital signature, Elliptic Curve Cryptography (ECC), hardware implementation
27	María Dolores Valdés, María José Moure, Camilo Quintáns, Enrique Mandado	A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications.	FPL	2003	DBLP DOI BibTeX RDF
27	Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti	FPGA Based Coprocessor to Calculate the Energy of Dipolar System.	PDP	2002	DBLP DOI BibTeX RDF
27	Abbes Amira, Ahmed Bouridane, Peter Milligan, Faycal Bensaali	Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing.	FPL	2002	DBLP DOI BibTeX RDF
27	Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol	Design of multi-tasking coprocessor control for Eclipse.	CODES	2002	DBLP DOI BibTeX RDF
27	Mokhtar Nibouche, Omar Nibouche, Ahmed Bouridane, Danny Crookes	An FPGA-based wavelet transforms coprocessor.	ICIP (3)	2001	DBLP DOI BibTeX RDF
27	Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim	In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
27	Nick Howgrave-Graham, Joan G. Dyer, Rosario Gennaro	Pseudo-random Number Generation on the IBM 4758 Secure Crypto Coprocessor.	CHES	2001	DBLP DOI BibTeX RDF
27	Gülbin Ezer	Xtensa with User Defined DSP Coprocessor Microarchitectures.	ICCD	2000	DBLP DOI BibTeX RDF
27	Jae Wook Chung, Sang Gyoo Sim, Pil Joong Lee	Fast Implementation of Elliptic Curve Defined over GF(pm) on CalmRISC with MAC2424 Coprocessor.	CHES	2000	DBLP DOI BibTeX RDF
27	Sean W. Smith, Elaine R. Palmer, Steve H. Weingart	Using a High-Performance, Programmable Secure Coprocessor.	Financial Cryptography	1998	DBLP DOI BibTeX RDF
27	Alexandre F. Tenca, Milos D. Ercegovac	A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures.	FCCM	1998	DBLP DOI BibTeX RDF	long-precision, computer arithmetic, reconfigurable architecture
27	Jason Cong, John Peck	On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor.	FCCM	1997	DBLP DOI BibTeX RDF
27	Danny Crookes, T. John Brown, Y. Dong, Gareth McAleese, Philip J. Morrow, D. K. Roantree, Ivor T. A. Spence	A Self-Optimising Coprocessor Model for Portable Image Processing.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
27	Francisco Castillo, Jose A. García 0003, Juan Manuel Moreno, Joan Cabestany	A Coprocessor Card for Fast Neural Network Emulation.	IWANN	1995	DBLP DOI BibTeX RDF
27	Jurij Silc, Borut Robic	Efficient Run-Time Program Allocation on a Parallel Coprocessor.	Euro-Par	1995	DBLP DOI BibTeX RDF
27	Javier Moran Carrera, Eduardo Juárez Martínez, S. A. Fernandez, J. M. M. Chaus	Architecture of a FPGA-based coprocessor: the PAR-1.	FCCM	1995	DBLP DOI BibTeX RDF
27	David W. Matula	Design of a highly parallel IEEE standard floating point unit: the Cyrix 83D87 coprocessor.	SPDP	1990	DBLP DOI BibTeX RDF
27	Jiun-Ming Hsu, Prithviraj Banerjee	A message passing coprocessor for distributed memory multicomputers.	SC	1990	DBLP DOI BibTeX RDF
27	Christos J. Georgiou, S. L. Palmer, Philip L. Rosenfeld	An Experimental Coprocessor for Implementing Persistant Objects on an IBM 4381.	ASPLOS	1987	DBLP DOI BibTeX RDF
21	Alexander Klimm, Oliver Sander, Jürgen Becker 0001	A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs.	IPDPS	2009	DBLP DOI BibTeX RDF
21	Hendrik Tews, Bart Jacobs 0001	Performance Issues of Selective Disclosure and Blinded Issuing Protocols on Java Card.	WISTP	2009	DBLP DOI BibTeX RDF	selective disclosure, blinded issuing, performance, Java Card
21	Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez	Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.	CHES	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, FPGA, elliptic curve, hardware accelerator, Tate pairing, finite field arithmetic, ? T pairing
21	Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds	Bridge Floating-Point Fused Multiply-Add Design.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
21	Hao Che, Zhijun Wang 0001, Kai Zheng 0003, Bin Liu 0001	DRES: Dynamic Range Encoding Scheme for TCAM Coprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Composite structures, Storage/repositories, Network repositories/data mining/backup, Associative memories
21	Volker Hampel, Peter Sobe, Erik Maehle	Designing coprocessors for hybrid compute systems.	IPDPS	2008	DBLP DOI BibTeX RDF
21	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP architecture exploration for efficient IPSec encryption: A case study.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	computer-aided design, ADL, ASIP, IPSec
21	Yung-Tai Hsu, Yuan-Jin Wen, Sheng-De Wang	Embedded Hardware/Software Design and Cosimulation using User Mode Linux and SystemC.	ICPP Workshops	2007	DBLP DOI BibTeX RDF
21	Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A fast and generic hybrid simulation approach using C virtual machine.	CASES	2007	DBLP DOI BibTeX RDF	simulation, virtual machine, debugging
21	Miljan Vuletic, Laura Pozzi, Paolo Ienne	Virtual memory window for application-specific reconfigurable coprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
21	Rakesh Agrawal 0001, Dmitri Asonov, Murat Kantarcioglu, Yaping Li	Sovereign Joins.	ICDE	2006	DBLP DOI BibTeX RDF
21	María José Moure, María Dolores Valdés, Pablo Rodiz, Loreto Rodríguez-Pardo, José Fariña Rodríguez	An FPGA-Based System on Chip for the Measurement of QCM Sensors Resolution.	FPL	2006	DBLP DOI BibTeX RDF
21	Guido Bertoni, Luca Breveglieri, Matteo Venturi	ECC Hardware Coprocessors for 8-bit Systems and Power Consumption Considerations.	ITNG	2006	DBLP DOI BibTeX RDF
21	Heather Quinn, Debayan Bhaduri, Christof Teuscher, Paul S. Graham, Maya B. Gokhale	The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability.	FCCM	2006	DBLP DOI BibTeX RDF
21	Jianjun Guo, Kui Dai, Zhiying Wang 0003	A Heterogeneous Multi-core Processor Architecture for High Performance Computing.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	TTA, SoC, heterogeneous, multi-core
21	Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti 0001	FPGA based Agile Algorithm-On-Demand Co-Processor.	DATE	2005	DBLP DOI BibTeX RDF
21	Akihito Takahashi, Stanislav Sedukhin	Parallel Blocked Algorithm for Solving the Algebraic Path Problem on a Matrix Processor.	HPCC	2005	DBLP DOI BibTeX RDF
21	Wido Kruijtzer, Winfried Gehrke, Víctor Reyes, Ghiath Alkadi, Thomas Hinz, Jörn Jachalsky, Bruno Steux	The design of a smart imaging core for automotive and consumer applications: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	image processing, system level design
21	Luiza de Macedo Mourelle, Nadia Nedjah	Hardware for Modular Exponentiation Suitable for Smart Cards.	ICESS	2004	DBLP DOI BibTeX RDF
21	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.	SCOPES	2004	DBLP DOI BibTeX RDF
21	Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo	Improving Java Performance Using Dynamic Method Migration on FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
21	Xuejun Liang, Jack S. N. Jean	Mapping of generalized template matching onto reconfigurable computers.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
21	Raj Krishnamurthy, Karsten Schwan, Richard West, Marcel-Catalin Rosu	On Network CoProcessors for Scalable, Predictable Media Services.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	Cluster machines, quality of service, real-time systems, embedded systems, operating systems, data streaming, packet scheduling, multimedia services
21	Giovanni Danese, Ivo De Lotto, Francesco Leporati, M. Scaricabarozzi, Alvaro Spelgatti	An Accelerator for Double Precision Floating Point Operations.	PDP	2003	DBLP DOI BibTeX RDF
21	Rama Sangireddy, Huesung Kim, Arun K. Somani	Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures.	HiPC	2003	DBLP DOI BibTeX RDF
21	Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol	Robust Media Processing in a Flexible and Cost-Effective Network of Multi-Tasking Coprocessors.	ECRTS	2002	DBLP DOI BibTeX RDF
21	Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi	Tradeoff analysis of FPGA based elliptic curve cryptography.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
21	Philip Heng Wai Leong, Chiu-Wing Sham, W. C. Wong, H. Y. Wong, Wing Seung Yuen, Monk-Ping Leong	A bitstream reconfigurable FPGA implementation of the WSAT algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
21	David W. Kravitz, Kim-Ee Yeoh, Nicol So	Secure Open Systems for Protecting Privacy and Digital Services.	Digital Rights Management Workshop	2001	DBLP DOI BibTeX RDF
21	K. A. Jung, Y. S. Lee, H. S. Yang, W. S. Yang, J. H. Kim, S. H. Lee, B. H. Kang	An integrated H.263 video CODEC with protocol processor.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
21	Marcel-Catalin Rosu, Karsten Schwan	Support for Recoverable Memory in the Distributed Virtual Communication Machine.	IPDPS	2000	DBLP DOI BibTeX RDF	recoverable memory, virtual machine, extensibility, communication architecture
21	Jörg Hilgenstock, Klaus Herrmann 0002, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch	A Video Signal Processor for MIMD Multiprocessing.	DAC	1998	DBLP DOI BibTeX RDF
21	Kumar N. Ganapathy, Benjamin W. Wah, Chien-Wei Li	Designing a Scalable Processor Array for Recurrent Computations.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Access unit, affine dependencies, area index, clock-rate reduction, multimesh graph, uniform dependencies, scheduling, partitioning, memory bandwidth, processor array, dependence graph
21	Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri	Rapid Prototyping of Reconfigurable Coprocessors.	ASAP	1996	DBLP DOI BibTeX RDF	Prototyping, High-level Synthesis, JPEG, Coprocessors, Hardware-Software Co-design, Software Profiling
21	H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask	An SBus Monitor Board.	FPGA	1995	DBLP DOI BibTeX RDF
21	Gordon B. Agnew, Ronald C. Mullin, Scott A. Vanstone	On the Development of a Fast Elliptic Curve Cryptosystem.	EUROCRYPT	1992	DBLP DOI BibTeX RDF
21	Joan Daemen, René Govaerts, Joos Vandewalle	A Hardware Design Model for Cryptographic Algorithms.	ESORICS	1992	DBLP DOI BibTeX RDF	Hardware Cryptography, Pseudorandom Sequence Generators, Stream Ciphers, Block Ciphers, Cryptographic Hash Functions
21	George I. Davida, Frank B. Dancs	A Crypto-Engine.	CRYPTO	1987	DBLP DOI BibTeX RDF
18	Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla	A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms.	VLSI Design	2010	DBLP DOI BibTeX RDF	C2R, Hardware Coprocessor, Software Algorithms, High Level Synthesis, Clock-gating, Power Reduction
18	Klaus Kursawe, Dries Schellekens	Flexible muTPMs through disembedding.	AsiaCCS	2009	DBLP DOI BibTeX RDF	mobile trusted module, secure coprocessor, trusted computing, trusted platform module
18	Abdulhadi Shoufan, Sorin A. Huss, Oliver Kelm, Sebastian Schipp	A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures.	ReConFig	2008	DBLP DOI BibTeX RDF	Winternitz, Security, FPGA, Key Management, Coprocessor, Rekeying
18	Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001	ARISE Machines: Extending Processors with Hybrid Accelerators.	ARC	2008	DBLP DOI BibTeX RDF	reconfigurable instruction set processor, custom unit, FPGA, coprocessor
18	Chung-Ping Young, Chung-Chu Chia, Liang-Bi Chen, Ing-Jer Huang	NCPA: A Scheduling Algorithm for Multi-cipher and Multi-mode Reconfigurable Cryptosystem.	IIH-MSP	2008	DBLP DOI BibTeX RDF	multiple cipher, scheduling algorithm, Cryptosystem, operation mode, crypto-coprocessor
18	Masayuki Yoshino, Katsuyuki Okeya, Camille Vuillaume	Double-Size Bipartite Modular Multiplication.	ACISP	2007	DBLP DOI BibTeX RDF	bipartite modular multiplication, double-size technique, RSA, smartcard, crypto-coprocessor
18	Dong-Ho Lee, Jong-Soo Oh	Multi-segment GF(2m) multiplication and its application to elliptic curve cryptography.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	elliptic curve scalar multiplication, FPGA, elliptic curve cryptography (ECC), coprocessor, finite field multiplication
18	Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede	Efficient pipelining for modular multiplication architectures in prime fields.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	public key coprocessor, FPGA, cryptography, montgomery multiplication
18	Ying-Dar Lin, Kuo-Kun Tseng, Chen-Chou Hung, Yuan-Cheng Lai	Scalable Automaton Matching for High-Speed Deep Content Inspection.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF	String matching, Hashing, Finite automata, Coprocessor, Content filtering
18	Alexander Iliev, Sean W. Smith	Protecting Client Privacy with Trusted Computing at the Server.	IEEE Secur. Priv.	2005	DBLP DOI BibTeX RDF	Secure coprocessor, Oblivious RAM, network traffic archival, prototype, PKI, Private Information Retrieval
18	Ali Skaf, Alain Guyot	SAGA: the first general-purpose on-line arithmetic co-processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	general-purpose co-processor, online arithmetic coprocessor, VLSI realisation, BKM algorithm, complex logarithm function, complex exponential function, VLSI, arithmetic, coprocessors, CMOS digital integrated circuits, redundant number systems, CMOS IC, SAGA
18	Herman Lam, Chiang Lee, Stanley Y. W. Su	A Special Function Unit for Database Operations (SFU-DB): Design and Performance Evaluation.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	special function unit, SFU-DB, hardware sorting module, automatic retrieval memory, nonnumeric operations, host CPU, special processing unit, distribution-based sort algorithm, main memory size, fundamental sort algorithm, CMOS gate arrays, performance evaluation, performance evaluation, parallel algorithms, computational complexity, database management systems, sorting, execution time, coprocessor, special purpose computers, fabrication, worst case complexity, Turbo Pascal, parallel processing system, duplicates elimination, database operations, set intersection, set union, set difference, relational join
18	David R. Smith, Jing C. Lin	The Tree-Match Chip.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	subject stream scan, multiple chip cascading, tree-match chip, chip organization, one-bit-wide stacks, functional language processing, 40-pin standard frame, satellite computers, parallel algorithms, VLSI, circuit layout CAD, CMOS integrated circuits, CMOS technology, shift registers, coprocessor, content-addressed memory, tree-pattern-matching
18	Sudhir Ahuja, Nicholas Carriero, David Gelernter, Venkatesh Krishnaswamy	Matching Language and Hardware for Parallel Computation in the Linda Machine.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	Linda Machine, Linda parallel programming environment, logically shared associative memory, high-level shared-memory abstraction, nonshared-memory architecture, special-purpose communication network, Linda coprocessor, performance evaluation, parallel programming, parallel computer, protocols, protocols, programming environments, parallel machines, tuple space
16	Rathindra Nath Biswas, Anurup Saha, Swarup Kumar Mitra, Mrinal Kanti Naskar	Design and implementation of anchor coprocessor architecture for wireless node localization applications.	Peer Peer Netw. Appl.	2024	DBLP DOI BibTeX RDF