Search results for "low-jitter"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Karim M. Megawer, Ahmed Elkholy, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu	Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
16	Pietro Tosato, David Macii, Daniele Fontanelli, Davide Brunelli, David M. Laverty	A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units.	CoRR	2019	DBLP BibTeX RDF
16	Ibrahim Kaya, Jorge Bohórquez, Özcan Özdamar	A BCI Gaze Sensing Method Using Low Jitter Code Modulated VEP.	Sensors	2019	DBLP DOI BibTeX RDF
16	Long Wang, Xirong Que, Xiangyang Gong, Ye Tian 0008, Tongtong Wang, Xinyuan Wang 0006	A Scheduling Algorithm for Low Jitter in Ethernet-Based Fronthaul.	ISCC	2019	DBLP DOI BibTeX RDF
16	Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal	A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems.	IntelliSys (1)	2019	DBLP DOI BibTeX RDF
16	Stefan Reif, Luis Gerhorst, Kilian Bender, Timo Hönig	Towards Low-Jitter and Energy-Efficient Data Processing in Cyber-Physical Information Systems.	HICSS	2019	DBLP BibTeX RDF
16	Zaher Kakehbra, Morteza Mousazadeh, Abdollah Khoei, Ali Dadashi	A Fast-Lock, Low Jitter, High-Speed Half-Rate CDR Architecture with a Composite Phase Detector (CPD).	MIXDES	2019	DBLP DOI BibTeX RDF
16	Shravan S. Nagam, Peter R. Kinget	A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
16	Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu	Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
16	Shamim Sadrafshari, Razieh Eskandari, Khayrollah Hadidi, Abdollah Khoei	Low-jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
16	Jin Wu, Youzhi Zhang 0003, Rongqi Zhao, Kunpeng Zhang, Lixia Zheng, Weifeng Sun	Low-jitter DLL applied for two-segment TDC.	IET Circuits Devices Syst.	2018	DBLP DOI BibTeX RDF
16	Pietro Tosato, David Macii, Daniele Fontanelli, Davide Brunelli, David M. Laverty	A Software-based Low-Jitter Servo Clock for Inexpensive Phasor Measurement Units.	ISPCS	2018	DBLP DOI BibTeX RDF
16	Shravan S. Nagam, Peter R. Kinget	A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation.	CICC	2018	DBLP DOI BibTeX RDF
16	Xiang Gao	Tutorials: Low-Jitter PLLs for wireless transceivers.	ISSCC	2018	DBLP DOI BibTeX RDF
16	Naizao Zhong, Runxi Zhang, Chunqi Shi, Jinghong Chen	A Bandwidth-Tracking Self-Biased 5-to-2800 MHz Low-Jitter Clock Generator in 55nm CMOS.	APCCAS	2018	DBLP DOI BibTeX RDF
16	Helmut Fedder, Steffen Oesterwind, Markus Wick, Fabian Olbrich, Peter Michler, Thomas Veigel, Manfred Berroth, Michael Schlagmuller	Characterization of Electro-Optical Devices with Low Jitter Single Photon Detectors - Towards an Optical Sampling Oscilloscope Beyond 100 GHz.	ECOC	2018	DBLP DOI BibTeX RDF
16	Wei Fan, Zhelu Li, Jianxiong Xi, Lenian He, Kexu Sun, Ning Xie	A 1.2 Gbps failsafe low jitter LVDS transmitter-receiver applied in CMOS image sensor.	MOCAST	2018	DBLP DOI BibTeX RDF
16	Mario Mauerer, Arda Tuysuz, Johann W. Kolar	Low-Jitter GaN E-HEMT Gate Driver With High Common-Mode Voltage Transient Immunity.	IEEE Trans. Ind. Electron.	2017	DBLP DOI BibTeX RDF
16	Yuan Wang 0001, Yuequan Liu, Song Jia, Xing Zhang 0002	Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process.	Int. J. Circuit Theory Appl.	2017	DBLP DOI BibTeX RDF
16	Dong-Hyun Yoon, Yohan Hong, Jae-Hun Jung, Youngkwon Jo, Kwang-Hyun Baek	A low-jitter BMCDR for half-rate PON systems.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
16	Solomon Michael Serunjogi, Kai-Wei Lin, Mahmoud Rasras, Mihai Sanduleanu	Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
16	Shravan S. Nagam, Peter R. Kinget	A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation.	CICC	2017	DBLP DOI BibTeX RDF
16	Frank Herzel, Arzu Ergintav, Johannes Borngräber, Herman Jalli Ng, Dietmar Kissinger	Design of a low-jitter wideband frequency synthesizer for 802.11ad wireless OFDM systems using a frequency sixtupler.	ISCAS	2017	DBLP DOI BibTeX RDF
16	JiHoon Kim, Yong Moon	A study of low jitter phase locked loop for SPDIF.	ISOCC	2017	DBLP DOI BibTeX RDF
16	Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo 0003	A Radiation-Immune Low-Jitter High-Frequency PLL for SerDes.	NCCET	2017	DBLP DOI BibTeX RDF
16	Seojin Choi, Seyeon Yoo, Younghyun Lim, Jaehyouk Choi	A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
16	Mina Kim, Seojin Choi, Taeho Seong, Jaehyouk Choi	A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
16	Yung-Hsiang Ho, Chia-Yu Yao	A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
16	Shubin Liu, Wei Guo, Zhangming Zhu	An automatic mode low-jitter pulsewidth control loop with broadband operation frequency.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
16	Assia Hamouda, Otto Manck, Mohamed Lamine Hafiane, Nour-Eddine Bouguechal	An Enhanced Technique for Ultrasonic Flow Metering Featuring Very Low Jitter and Offset.	Sensors	2016	DBLP DOI BibTeX RDF
16	Gürkan Yilmaz, Catherine Dehollain	20-300 MHz frequency generator with -70 dBc reference spur for low jitter serial applications.	NORCAS	2016	DBLP DOI BibTeX RDF
16	Harishankar Sahu, Pallavi Paliwal, Vivek Yadav, Shalabh Gupta	A low-jitter digital-to-time converter with look-ahead multi-phase DDS.	LASCAS	2016	DBLP DOI BibTeX RDF
16	Xiaoying Deng, Yanyan Mo, Xin Lin, Mingcheng Zhu	Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCO.	SoCC	2016	DBLP DOI BibTeX RDF
16	Hengzhou Yuan, Yang Guo 0003, Yao Liu, Bin Liang, Qian-cheng Guo, Jia-wei Tan	A low-jitter self-biased phase-locked loop for SerDes.	ISOCC	2016	DBLP DOI BibTeX RDF
16	Bum-Hee Choi, Kyung-Sub Son, Jin-Ku Kang	A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's.	APCCAS	2016	DBLP DOI BibTeX RDF
16	Cunbo Lu, Liangtian Wan	A Low-Jitter Wireless Transmission Based on Buffer Management in Coding-Aware Routing.	Future Internet	2015	DBLP DOI BibTeX RDF
16	Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen	A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
16	Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001	Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2015	DBLP DOI BibTeX RDF
16	Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei	A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs.	J. Circuits Syst. Comput.	2015	DBLP DOI BibTeX RDF
16	Mohammad Gholami, Hamid Rahimpour, Gholamreza Ardeshir, Hossein Miar Naimi	A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers.	Int. J. Circuit Theory Appl.	2015	DBLP DOI BibTeX RDF
16	Minjie Liu, Yingzi Jiang, Siwan Dong, Zhangming Zhu, Yintang Yang	A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
16	Jinn-Shyan Wang, Chun-Yuan Cheng	An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
16	Xian Zhang, Hhua Liu, Lei Li	A low jitter phase-locked loop based on self-biased techniques.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
16	Okan Zafer Batur, Naci Pekcokguler, Günhan Dündar, Mutlu Koca	A high resolution and low jitter linear delay line for IR-UWB template pulse synchronization.	ECCTD	2015	DBLP DOI BibTeX RDF
16	Juan Núñez 0002, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda	An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs.	LASCAS	2015	DBLP DOI BibTeX RDF
16	Seok Min Jung, Janet Meiling Roveda	A low jitter digital phase-locked loop with a hybrid analog/digital PI control.	NEWCAS	2015	DBLP DOI BibTeX RDF
16	Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen	A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique.	ISCAS	2015	DBLP DOI BibTeX RDF
16	Yuequan Liu, Yuan Wang 0001, Song Jia, Xing Zhang 0002	180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance.	ISCAS	2015	DBLP DOI BibTeX RDF
16	Jun Guo, Peng Liu 0016, Weidong Wang, Jicheng Chen, Yingtao Jiang	A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector.	SoCC	2015	DBLP DOI BibTeX RDF
16	Seok Min Jung, Janet Meiling Roveda	A 320MHz-2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique.	SoCC	2015	DBLP DOI BibTeX RDF
16	Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong	Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
16	Chung-Yi Li, Chung-Len Lee, Ming-Hong Hu, Hwai-Pwu Chou	A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Jing Zhu 0006, Yunwu Zhang, Weifeng Sun, Yangbo Yi	Low-jitter, high-linearity current-controlled complementary metal oxide semiconductor relaxation oscillator with optimised floating capacitors.	IET Circuits Devices Syst.	2014	DBLP DOI BibTeX RDF
16	Young-Ju Kim 0001, Sang-Hye Chung, Lee-Sup Kim	A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
16	Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Jen-Ming Wu, Ching-Te Chiu, Shawn S. H. Hsu, Mau-Chung Frank Chang	A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
16	Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori	Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
16	Taek-Joon Ahn, Sang-Soon Im, Yong-Sung Ahn, Jin-Ku Kang	A low jitter clock and data recovery with a single edge sensing Bang-Bang PD.	IEICE Electron. Express	2014	DBLP DOI BibTeX RDF
16	Anil Chawda, Pallavi Paliwal, Priyank Laad, Shalabh Gupta	High resolution digital-to-time converter for low jitter digital PLLs.	ICECS	2014	DBLP DOI BibTeX RDF
16	Mohamed Hamouda, Georg Fischer 0001, Robert Weigel, Andreas Baenisch, Thomas Ussmueller	A 20-Gbps low jitter analog clock recovery circuit for ultra-wide band Radio systems.	ISCAS	2014	DBLP DOI BibTeX RDF
16	Yuan Fang, Jonas Bargon, Ashok Jaiswal, Klaus Hofmann	A low-jitter clock and data recovery for GDDR5 interface trainings.	ICICDT	2014	DBLP DOI BibTeX RDF
16	Christoph Baer, Thomas Musch, Timo Jaeschke, Nils Pohl	Contactless determination of gas concentration and pressure based on a low jitter mmWave FMCW radar.	SAS	2014	DBLP DOI BibTeX RDF
16	Hengzhou Yuan, Yang Guo 0003, Zhuo Ma	A 40nm/65nm process adaptive low jitter phase-locked loop.	ISIC	2014	DBLP DOI BibTeX RDF
16	Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang	Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
16	Gianluca Cena, Ivan Cibrario Bertolotti, Tingting Hu, Adriano Valenzano	Fixed-Length Payload Encoding for Low-Jitter Controller Area Network Communication.	IEEE Trans. Ind. Informatics	2013	DBLP DOI BibTeX RDF
16	Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001	A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
16	Reza Molavi, Hormoz Djahanshahi, Rod Zavari, Shahriar Mirabbasi	Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration.	J. Electr. Comput. Eng.	2013	DBLP DOI BibTeX RDF
16	Shubin Liu, Zhangming Zhu, Huaxi Gu, Yintang Yang	A low-jitter pulsewidth control loop with high supply noise rejection.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
16	Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang	A low jitter delay-locked-loop applied for DDR4.	DDECS	2013	DBLP DOI BibTeX RDF
16	Kan Yu, Mikael Gidlund, Johan Åkerberg, Mats Björkman	Low jitter scheduling for Industrial Wireless Sensor and Actuator Networks.	IECON	2013	DBLP DOI BibTeX RDF
16	Ayan Mandal, Kalyana C. Bollapalli, Nikhil Jayakumar, Sunil P. Khatri, Rabi N. Mahapatra	A low-jitter phase-locked resonant clock generation and distribution scheme.	ICCD	2013	DBLP DOI BibTeX RDF
16	Yun Chen, Chaojie Fan, Jianjun Zhou	Low jitter clock driver for high-performance pipeline ADC.	ASICON	2013	DBLP DOI BibTeX RDF
16	Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung	A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
16		A fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
16	Kamran Farzan, Mehrdad Ramezani, Angus McLaren, Roman Pahuta, Nadeesha Amarasinghe, David Cassan, Saman Sadr	A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology.	ESSCIRC	2012	DBLP DOI BibTeX RDF
16	Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001	A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops.	VLSIC	2012	DBLP DOI BibTeX RDF
16	Gianluca Cena, Ivan Cibrario Bertolotti, Tingting Hu, Adriano Valenzano	Performance evaluation and improvement of the CPU-CAN controller interface for low-jitter communication.	ETFA	2012	DBLP DOI BibTeX RDF
16	Manas Kumar Hati, Tarun Kanti Bhattacharyya	A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL.	VDAT	2012	DBLP DOI BibTeX RDF
16	Li Qiang Tao, Feng Qi Yu	Low-jitter slot assignment algorithm for deadline-aware packet transmission in wireless video surveillance sensor networks.	Int. J. Commun. Syst.	2011	DBLP DOI BibTeX RDF
16	Hsuan-Jung Hsu, Shi-Yu Huang	A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
16	Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki Kim	A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
16	Hsin-Chuan Chen	Design Approach of a Low-Jitter DDS-Like Frequency Synthesizer Using Mixed-Mode Signal Processing.	RVSP	2011	DBLP DOI BibTeX RDF
16	Shaolong Liu, Hui Wang, Yuhua Cheng	A wide lock-range, low jitter phase-locked loop for multi-standard SerDes application.	ASICON	2011	DBLP DOI BibTeX RDF
16	Wimol San-Um, Masayoshi Tachibana	A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration.	ISCAS	2010	DBLP DOI BibTeX RDF
16	Hossam Ali, Emad Hegazi	A low-jitter video clock recovery circuit.	ISCAS	2010	DBLP DOI BibTeX RDF
16	Wladek Olesinski, Hans Eberle	Simple two-priority, low-jitter scheduler.	ANCS	2010	DBLP DOI BibTeX RDF
16	Belal Helal, Chun-Ming Hsu, Kerwin Johnson, Michael H. Perrott	A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
16	Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim	A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
16	Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo	A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
16	Joonhee Lee, Sungjun Kim, Sehyung Jeon, Woojae Lee, SeongHwan Cho	A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
16	T. H. Szymanski	A low-jitter guaranteed-rate scheduling algorithm for packet-switched ip routers.	IEEE Trans. Commun.	2009	DBLP DOI BibTeX RDF
16	Salvatore Levantino, Marco Zanuso, Davide Tasca, Carlo Samori, Andrea L. Lacaita	An all-digital architecture for low-jitter regulated delay lines.	ICECS	2009	DBLP DOI BibTeX RDF
16	Takashi Kawamoto, Tomoaki Takahashi, Shigeyuki Suzuki, Takayuki Noto, Katsushi Asahina	Low-jitter fractional spread-spectrum clock generator using fast-settling dual charge-pump technique for Serial-ATA application.	ESSCIRC	2009	DBLP DOI BibTeX RDF
16	Ro-Min Weng, Yun-Chih Lu, Chun-Yu Liu	A Low Jitter Arbitrary-input Pulsewidth Control Loop with Wide Duty Cycle Adjustment.	ISCAS	2009	DBLP DOI BibTeX RDF
16	Jee Khoi Yin, Pak Kwong Chan	A Low-Jitter Polyphase-Filter-Based Frequency Multiplier With Phase Error Calibration.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
16	Xiang Gao 0002, Bram Nauta, Eric A. M. Klumperink	Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
16	Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu	A low jitter self-calibration PLL for 10Gbps SoC transmission links application.	ICECS	2008	DBLP DOI BibTeX RDF
16	Takashi Kawamoto, Masaru Kokubo	A low-jitter 1.5-GHz and 350-ppm spread-spectrum serial ATA PHY using reference clock with 400-ppm production-frequency tolerance.	ESSCIRC	2008	DBLP DOI BibTeX RDF
16	Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim	A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.	ESSCIRC	2008	DBLP DOI BibTeX RDF
16	Keng-Jan Hsiao, Tai-Cheng Lee	A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation.	ISSCC	2008	DBLP DOI BibTeX RDF
16	Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu	A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology.	ISCAS	2008	DBLP DOI BibTeX RDF