Search results for "metallization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Detlef Weber, F. Höhnsdorf, A. Hausmann, A. Klipp, Z. Stavreva, J. Herrmann, L. Bauch, M. Junack, H. Neef, M. Nichterwitz, S. Finsterbusch	Impact of substituting SiO2 ILD by low k materials into AlCu RIE metallization.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
23	David Dalleau, Kirsten Weide-Zaage	Three-Dimensional Voids Simulation in chip Metallization Structures: a Contribution to Reliability Evaluation.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
23	Shatil Haque, Guo-Quan Lu	Effects of device passivation materials on solderable metallization of IGBTs.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
23	Keith K. H. Wong, Suryanarayana Kaja, Patrick W. DeHaven	Metallization by plating for high-performance multichip modules.	IBM J. Res. Dev.	1998	DBLP DOI BibTeX RDF
23	Evan G. Colgan, Mitsuru Uda	On-chip metallization layers for reflective light valves.	IBM J. Res. Dev.	1998	DBLP DOI BibTeX RDF
23	Kang-Wook Lee 0003, Alfred Viehbeck	Wet-process surface modification of dielectric polymers: Adhesion enhancement and metallization.	IBM J. Res. Dev.	1994	DBLP DOI BibTeX RDF
23	William L. Guthrie, William J. Patrick, Ernest Levine, Harris C. Jones, Ebrahim A. Mehter, Thomas F. Houghton, George T. Chiu, Michael A. Fury	A four-level VLSI bipolar metallization design with chemical-mechanical planarization.	IBM J. Res. Dev.	1992	DBLP DOI BibTeX RDF
23	Tom J. Smy, R. Niall Tait, Michael J. Brett	Ballistic deposition simulation of via metallization using a quasi-three-dimensional model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
23	E. H. A. Crannernan	Multi-level metallization: Future prospects.	Eur. Trans. Telecommun.	1990	DBLP DOI BibTeX RDF
23	Joseph E. Hall, Dale E. Hocevar, Ping Yang 0001, Michael J. McGraw	SPIDER -- A CAD System for Modeling VLSI Metallization Patterns.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1987	DBLP DOI BibTeX RDF
23	Neil DalCero	Automatic batch processing in multilayer ceramic metallization.	DAC	1983	DBLP BibTeX RDF
18	Laurent Sauvage, Sylvain Guilley, Yves Mathieu	Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	EMA, security, FPGA, DPA, SCA, cartography
18	Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar	Complementary nano-electromechanical switches for ultra-low power embedded processors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	nems, cmos, switch, device, ultra-low power
18	Andrew B. Kahng, Kambiz Samadi	CMP Fill Synthesis: A Survey of Recent Studies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
18	SungJoon Lee, A. Pandey, DongSeop Kim, Ajeet Rohatgi, Gary S. May, Sang Jeen Hong, Seung Soo Han	Characterization and Optimization of the Contact Formation for High-Performance Silicon Solar Cells.	ISNN (3)	2007	DBLP DOI BibTeX RDF
18	Negin Manavizadeh, Rashid Safa Isini, Behzad Esfandyarpour, Ebrahim Asl Soleimani, Hassan Ghafoori Fard	Low Cost Electroplated Ni/Cu Ohmic Contacts for Multicrystalline Si Solar Cells using an Ultrasonic System.	CCECE	2006	DBLP DOI BibTeX RDF
18	Mohamed Lamine Tounsi, Rachida Touhami, Mustapha Chérif-Eddine Yagoub	Conception Des Coupleurs Coplanaires Multicouches En Bande Millimétrique Sur Des Substrats Anisotropes à Deux Niveaux De Métallisation.	CCECE	2006	DBLP DOI BibTeX RDF
18	R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh 0004	A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.	ISQED	2005	DBLP DOI BibTeX RDF
18	Syed M. Alam, Frank L. Wei, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel	Electromigration Reliability Comparison of Cu and Al Interconnects.	ISQED	2005	DBLP DOI BibTeX RDF
18	Eric F. Weglarz, Kewal K. Saluja, T. M. Mak	Testing of Hard Faults in Simultaneous Multithreaded Processors.	IOLTS	2004	DBLP DOI BibTeX RDF
18	Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda	A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification.	ISQED	2004	DBLP DOI BibTeX RDF
18	Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson	Design and implementation of the POWER5 microprocessor.	DAC	2004	DBLP DOI BibTeX RDF	POWER5, simultaneous multi-threading (SMT), clock gating, power reduction, microprocessor design, temperature sensor
18	Goeran Jerke, Jens Lienig, Jürgen Scheible	Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs.	DAC	2004	DBLP DOI BibTeX RDF	decompaction, layout decomposition, physical design, compaction, electromigration, interconnect reliability
18	Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie	Multi-objective optimization of interconnect geometry.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
18	David J. Walkey, Dritan Celo, Tom J. Smy	A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
18	Mohamed Lamine Tounsi, H. Halheit, Mustapha Chérif-Eddine Yagoub, Abdfelhamid Khodja	Analysis of shielded planar circuits by a mixed variational-spectral method.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama	A 1.3GHz fifth generation SPARC64 microprocessor.	DAC	2003	DBLP DOI BibTeX RDF	unix server, reliability, microprocessor, microarchitecture, SPARC, clock distribution
18	Dage Liu, John H. Reif, Thomas H. LaBean	DNA Nanotubes: Construction and Characterization of Filaments Composed of TX-tile Lattice.	DNA	2002	DBLP DOI BibTeX RDF
18	Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner	Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	SOI technology, logic design styles, circuit Design
18	J. W. McPherson	Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts.	ISQED	2001	DBLP DOI BibTeX RDF
18	Fabrice Caignet, S. D.-B. Dhia, Etienne Sicard	On the measurement of crosstalk in integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
18	Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor	Performance and Reliability Verification of C6201/C6701 Digital Signal Processors.	ICCD	1999	DBLP DOI BibTeX RDF
18	Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen	Three-dimensional capacitance computations for VLSI/ULSI interconnections.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
18	Albert Seidl, Helmut Klose, Milos Svoboda, Joachim Oberndorfer, Wolfgang Rösner	CAPCAL-a 3-D capacitance solver for support of CAD systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF