Search results for "multiple-valued"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
39	Claudio Moraga, Milena Stankovic, Radomir S. Stankovic, Suzana Stojkovic	On Bent and Hyper-bent Multiple-valued Functions.	J. Multiple Valued Log. Soft Comput.	2017	DBLP BibTeX RDF
39	Tamás Waldhauser	Maximal and Minimal Closed Classes in Multiple-valued Logic.	J. Multiple Valued Log. Soft Comput.	2016	DBLP BibTeX RDF
39	Bernd Steinbach, Christian Posthoff	Highly Complex 4-Colored Rectangle-free Grids - Solution Unsolved Multiple-Valued Problems.	J. Multiple Valued Log. Soft Comput.	2015	DBLP BibTeX RDF
39	David Y. Feinstein, Mitchell A. Thornton	Quantum Multiple-Valued Decision Diagrams Containing Skipped Variables.	J. Multiple Valued Log. Soft Comput.	2015	DBLP BibTeX RDF
39	Theodore W. Manikas, Mitchell A. Thornton, David Y. Feinstein	Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams.	J. Multiple Valued Log. Soft Comput.	2015	DBLP BibTeX RDF
39	Radomir S. Stankovic, Jaakko Astola	Contributions of Arto Salomaa to Multiple-Valued Logic.	J. Multiple Valued Log. Soft Comput.	2015	DBLP BibTeX RDF
39	Bernd Steinbach, Christian Posthoff	The Last Unsolved Four-Colored Rectangle-Free Grid: The Solution ofExtremely Complex Multiple-Valued Problems.	J. Multiple Valued Log. Soft Comput.	2015	DBLP BibTeX RDF
39	Kazuya Saito, Naofumi Homma, Takafumi Aoki	A Formal Approach to Designing Multiple-Valued Arithmetic Circuits.	J. Multiple Valued Log. Soft Comput.	2015	DBLP BibTeX RDF
39	Helena Astola, Stanislav Stankovic, Jaakko Astola	Introducing Fault-Tolerance to Multiple-Valued Logic with Error-Correcting Decision Diagrams.	J. Multiple Valued Log. Soft Comput.	2014	DBLP BibTeX RDF
39	Stanislav Stankovic, Milena Stankovic, Jaakko Astola	Representation of Multiple-Valued Functions with Flat Vilenkin-Chrestenson Spectra by Decision Diagrams.	J. Multiple Valued Log. Soft Comput.	2014	DBLP BibTeX RDF
39	Anna Bernasconi 0001, Valentina Ciriani	Autosymmetric and Dimension Reducible Multiple-Valued Functions.	J. Multiple Valued Log. Soft Comput.	2014	DBLP BibTeX RDF
39	Rohit P. Menon, Mitchell A. Thornton	Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.	J. Multiple Valued Log. Soft Comput.	2014	DBLP BibTeX RDF
39	Tsutomu Sasao	Multiple-Valued Index Generation Functions: Reduction of Variables by Linear Transformation.	J. Multiple Valued Log. Soft Comput.	2013	DBLP BibTeX RDF
39	Ori Lahav 0001	Studying Sequent Systems via Non-deterministic Multiple-Valued Matrices.	J. Multiple Valued Log. Soft Comput.	2013	DBLP BibTeX RDF
39	Jaakko Astola, Radomir S. Stankovic	Determination of Sparse Representations of Multiple-Valued Logic Functions by Using Covering Codes.	J. Multiple Valued Log. Soft Comput.	2012	DBLP BibTeX RDF
39	Elena Dubrova, Ming Liu, Maxim Teslenko	Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-based Bounded Model Checking.	J. Multiple Valued Log. Soft Comput.	2012	DBLP BibTeX RDF
39	Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu	Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique.	J. Multiple Valued Log. Soft Comput.	2012	DBLP BibTeX RDF
39	Radomir S. Stankovic, Jaakko Astola, Claudio Moraga	Design of Multiple-Valued Logic Networks with Regular Structure by Using Spectral Representations.	J. Multiple Valued Log. Soft Comput.	2012	DBLP BibTeX RDF
39	Francesc Esteva, Joan Gispert, Felip Manyà	Introduction to the Special Issue of the IEEE 40th International Symposium on Multiple-Valued Logic.	J. Multiple Valued Log. Soft Comput.	2012	DBLP BibTeX RDF
39	Anatolij Dvurecenskij, George Georgescu, Afrodita Iorgulescu, Sergiu Rudeanu	Foreword: Multiple-Valued Logic and Its Algebras.	J. Multiple Valued Log. Soft Comput.	2010	DBLP BibTeX RDF
39	Takaaki Mizuki, Hitoshi Tsubata, Takao Nishizeki	Minimizing AND-EXOR Expressions for Two-Variable Multiple-Valued Input Binary Output Functions.	J. Multiple Valued Log. Soft Comput.	2010	DBLP BibTeX RDF
39	Silvana Marinkovic, Dragic Bankovic	General Solutions of Equations in Multiple-Valued Logic?	J. Multiple Valued Log. Soft Comput.	2010	DBLP BibTeX RDF
39	Yasushi Yuminaka, Yasunori Takahashi	Time-Domain Pre-Emphasis Techniques for Multiple Valued Data Transmission.	J. Multiple Valued Log. Soft Comput.	2009	DBLP BibTeX RDF
39	Alexis De Vos, Yvan Van Rentergem	Multiple-Valued Reversible Logic Circuits.	J. Multiple Valued Log. Soft Comput.	2009	DBLP BibTeX RDF
39	Shangce Gao, Jianchen Zhang, Zheng Tang, Qi Ping Cao	A Chaotic Dynamic Local Search Method for Learning Multiple-Valued Logic Networks.	J. Multiple Valued Log. Soft Comput.	2009	DBLP BibTeX RDF
39	Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.	J. Multiple Valued Log. Soft Comput.	2009	DBLP BibTeX RDF
39	David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller	Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics.	J. Multiple Valued Log. Soft Comput.	2009	DBLP BibTeX RDF
39	Radomir S. Stankovic, Jaakko Astola	Interpretations of the Sampling Theorem in Multiple-Valued Logic.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
39	Nobuaki Okada, Michitaka Kameyama	Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
39	Krzysztof S. Berezowski, Sarma B. K. Vrudhula	Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
39	Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
39	Tasuku Ito, Michitaka Kameyama	Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
39	Dragan Jankovic, Radomir S. Stankovic, Claudio Moraga	Implementation Complexity of Algorithms for Optimization of Galois Field Expressions for Multiple-Valued Functions.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
39	David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat	Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
39	Yasushi Yuminaka, Kazuyoshi Yamamura	Equalization Techniques for Multiple-Valued Data Transmission and Their Application.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
39	Alioune Ngom, Dan A. Simovici, Ivan Stojmenovic	Evolutionary Strategy for Learning Multiple-Valued Logic Functions.	J. Multiple Valued Log. Soft Comput.	2006	DBLP BibTeX RDF
39	D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck	Synthesis of Quantum Multiple-Valued Circuits.	J. Multiple Valued Log. Soft Comput.	2006	DBLP BibTeX RDF
39	Pawel Kerntopf, Marek A. Perkowski, Mozammel H. A. Khan	On Universality of General Reversible Multiple-Valued Logic Gates.	J. Multiple Valued Log. Soft Comput.	2006	DBLP BibTeX RDF
39	Tomohiro Takahashi, Takahiro Hanyu	Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits.	J. Multiple Valued Log. Soft Comput.	2005	DBLP BibTeX RDF
39	Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis.	J. Multiple Valued Log. Soft Comput.	2005	DBLP BibTeX RDF
39	Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects.	J. Multiple Valued Log. Soft Comput.	2005	DBLP BibTeX RDF
39	Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama	Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic.	J. Multiple Valued Log. Soft Comput.	2005	DBLP BibTeX RDF
39	James J. Lu, Neil V. Murray, Erik Rosenthal	Deduction and Search Strategies for Regular Multiple-Valued Logics.	J. Multiple Valued Log. Soft Comput.	2005	DBLP BibTeX RDF
39	Radomir S. Stankovic, Milena Stankovic, Claudio Moraga	Haar Wavelet Transforms and Haar Spectral Transform Decision Diagrams for Switching and Multiple-Valued Functions.	J. Multiple Valued Log. Soft Comput.	2005	DBLP BibTeX RDF
39	Elena Dubrova, Harald Sack	Probabilistic Equivalence Checking of Multiple-Valued Functions.	J. Multiple Valued Log. Soft Comput.	2004	DBLP BibTeX RDF
39	Mark G. Karpovsky, Radomir S. Stankovic, Claudio Moraga	Spectral Techniques in Binary and Multiple-Valued Switching Theory: A Review of Results in the Decade 1991-2000.	J. Multiple Valued Log. Soft Comput.	2004	DBLP BibTeX RDF
39	Susanto Rahardja, Bogdan J. Falkowski	Fast Mixed Linearly Independent Arithmetic Logic Transforms for Multiple-Valued Functions.	J. Multiple Valued Log. Soft Comput.	2004	DBLP BibTeX RDF
39	Svetlana N. Yanushkevich, Vlad P. Shmerko, V. D. Malyugin, Piotr Dziurzanski, Anna M. Tomaszewska	Linearity of Word-Level Representations of Multiple-Valued Networks.	J. Multiple Valued Log. Soft Comput.	2004	DBLP BibTeX RDF
39	Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama	Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications.	J. Multiple Valued Log. Soft Comput.	2003	DBLP BibTeX RDF
39	Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama	Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization.	J. Multiple Valued Log. Soft Comput.	2003	DBLP BibTeX RDF
39	Andrew Adamatzky, Anthony G. Pipe	Editorial: Multiple-Valued Logic and Robotics.	J. Multiple Valued Log. Soft Comput.	2003	DBLP BibTeX RDF
39	Benet Devereux, Marsha Chechik	Edge-Shifted Decision Diagrams for Multiple-Valued Logic.	J. Multiple Valued Log. Soft Comput.	2003	DBLP BibTeX RDF
39	Pedro Acevedo Contla, Ivo G. Rosenberg, Dan A. Simovici, Ivan Stojmenovic	Boolean Completeness in Multiple-Valued Set Logic.	J. Multiple Valued Log. Soft Comput.	2003	DBLP BibTeX RDF
39	Elena Dubrova, Maxim Teslenko, Ming Liu	Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-Based Bounded Model Checking.	ISMVL	2010	DBLP DOI BibTeX RDF	multiple-valued network, SAT, bounded model checking, gene regulatory network, attractor
39	Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu	One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control.	ISMVL	2010	DBLP DOI BibTeX RDF	asynchronous transmission, current-mode, multiple-valued
39	Yuichi Baba, Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki	Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors.	ISMVL	2010	DBLP DOI BibTeX RDF	cryptographic processors, side-channel attacks, multiple-valued logic, RSA cryptosystem
39	Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi 0001	Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis.	ISMVL	2002	DBLP DOI BibTeX RDF	genetic algorithms, evolutionary computation, multiple-valued logic, arithmetic circuits
39	Alioune Ngom, Ivan Stojmenovic, Ratko Tosic	The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons.	ISMVL	2000	DBLP DOI BibTeX RDF	general position, partition, capacity, Separability, perceptrons, multiple-valued functions, multisets
39	Tsutomu Sasao	Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions.	ISMVL	1999	DBLP DOI BibTeX RDF	LUT-based FPGA, Multiple-valued logic function, Functional decomposition, Symmetric function
39	T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Programmable Logic Arrays with Universal Literals.	ISMVL	1997	DBLP DOI BibTeX RDF	universal literals, multiple-valued programmable logic, universal literal generators, operator structures, programmable logic arrays, programmable logic arrays
39	Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang	Decomposition of Multiple-Valued Relations .	ISMVL	1997	DBLP DOI BibTeX RDF	multiple-valued relations decomposition, cofactor pair compatibility, group compatibility, strongly unspecified data, program GUD-MV, machine learning, learning (artificial intelligence)
39	Reiner Hähnle	Commodious Axiomatization of Quantifiers in Multiple-Valued Logic.	ISMVL	1996	DBLP DOI BibTeX RDF	commodious axiomatization, distribution quantifiers, lattice-based quantifiers, skolemized signed formulas, Boolean set lattices, Boolean functions, filters, multivalued logic, multiple-valued logic, quantifiers
39	D. Michael Miller, Noriaki Muranaka	Multiple-Valued Decision Diagrams with Symmetric Variable Nodes.	ISMVL	1996	DBLP DOI BibTeX RDF	symmetry, Multiple-valued logic, decision diagrams
39	Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu	A Multiple-Valued Ferroelectric Content-Addressable Memory.	ISMVL	1996	DBLP DOI BibTeX RDF	ferroelectric, nonvolatile, memory, associative, CAM, content-addressable, multiple-valued
39	Boris A. Romov	Completeness Theory for Vector Partial Multiple-Valued Logic Functions.	ISMVL	1995	DBLP DOI BibTeX RDF	completeness theory, vector partial multiple-valued logic functions, completeness criterion, multiple-base invariant relations algebra, restricted quantifier free calculus, multivalued logic, Galois connection
39	Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi 0001	An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access.	ISMVL	2000	DBLP DOI BibTeX RDF
38	Nobuaki Okada, Michitaka Kameyama	Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits.	ISMVL	2007	DBLP DOI BibTeX RDF
38	Tsutomu Sasao, Jon T. Butler	Implementation of Multiple-Valued CAM Functions by LUT Cascades.	ISMVL	2006	DBLP DOI BibTeX RDF
38	Hafiz Md. Hasan Babu, Tsutomu Sasao	Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions.	ISMVL	1999	DBLP DOI BibTeX RDF
37	Tsutomu Sasao, Jon T. Butler	A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams.	ISMVL	1996	DBLP DOI BibTeX RDF	multiple-output switching functions, multi-terminal, multivalued logic, decision tables, computation time, switching functions, switching functions, multi-valued decision diagrams
37	Mitchell A. Thornton	Spectral Transforms of Mixed-radix MVL Functions.	ISMVL	2003	DBLP DOI BibTeX RDF
36	Marsha Chechik, Benet Devereux, Steve M. Easterbrook, Albert Y. C. Lai, Victor Petrovykh	Efficient Multiple-Valued Model-Checking Using Lattice Representations.	CONCUR	2001	DBLP DOI BibTeX RDF
35	Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi 0001	Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI.	ISMVL	2002	DBLP DOI BibTeX RDF	new paradigm computing, high-speed signaling, code-division multiple access, equalization, VLSI systems
34	Syuusuke Kuribara, Safia Abbas, Hajime Sawamura	Applying the Logic of Multiple-Valued Argumentation to Social Web: SNS and Wikipedia.	PRIMA	2008	DBLP DOI BibTeX RDF	Logic of Multiple-Valued Argumentation, Wikipedia, Argumentation, Social Web, SNS
34	Toshiko Wakaki, Takanori Mukai, Hiromitsu Miyashita, Hajime Sawamura, Kumiko Matsunaga, Taro Fukumoto, Katsumi Nitta	Automated argument system based on logic of multiple-valued argumentation.	AAMAS	2006	DBLP DOI BibTeX RDF	multiple-valued argumentation, multi-agent system, learning, knowledge acquisition
34	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.	PRDC	2000	DBLP DOI BibTeX RDF	dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
34	Svetlana N. Yanushkevich, Denis V. Popel, Vlad P. Shmerko, V. Cheushev, Radomir S. Stankovic	Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4).	ISMVL	2000	DBLP DOI BibTeX RDF	multiple-valued logic functions, information theory measures, decision trees, minimization
34	Renren Liu	Research on the Similarity among Precomplete Sets Preserving m-ary Relations in Partial K-Valued Logic.	ISMVL	1999	DBLP DOI BibTeX RDF	Partial multiple-valued logic, Sheffer functions, completeness
34	I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis	Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	voltage-mode latches, voltage-mode master-slave, true-single phase clocked-logic, Multiple-Valued Logic
34	Susanto Rahardja, Bogdan J. Falkowski	Family of Complex Hadamard Transforms: Relationship with Other Transforms and Complex Composite Spectra.	ISMVL	1997	DBLP DOI BibTeX RDF	complex Hadamard transforms, complex composite spectra, binary logic design, complex Hadamard matrices, convolution operation, complex convolution, Boolean functions, codings, Hadamard transforms, multiple-valued logic design
34	Sumiyasu Yamamoto, Shinsei Tazawa, Kazuhiko Ushio, Hideto Ikeda	Design of a Generalized Balanced Multiple-Valued File Organization Scheme of Order Two.	SIGMOD Conference	1978	DBLP DOI BibTeX RDF	directory file, multilist structure, multiple-valued records, redundancy, file organization, information storage and retrieval, bucket
34	Krzysztof S. Berezowski, Sarma B. K. Vrudhula	Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices.	ISMVL	2007	DBLP DOI BibTeX RDF
34	Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.	ISMVL	2007	DBLP DOI BibTeX RDF
34	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic.	ISMVL	2006	DBLP DOI BibTeX RDF
34	Haque Mohammad Munirul, Michitaka Kameyama	Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.	ISMVL	2006	DBLP DOI BibTeX RDF
34	Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu	Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders.	ISMVL	2005	DBLP DOI BibTeX RDF
34	Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama	Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic.	ISMVL	2005	DBLP DOI BibTeX RDF
34	Marek A. Perkowski, Tsutomu Sasao, Jong-Hwan Kim, Martin Lukac, Jeff Allen, Stefan Gebauer	Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem.	ISMVL	2005	DBLP DOI BibTeX RDF
34	Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari	Basic Multiple-Valued Functions Using Recharge CMOS Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
34	Svetlana N. Yanushkevich, Vlad P. Shmerko, L. Guy, D. C. Lu	Three Dimensional Multiple Valued Circuits Design Based on Single-Electron Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
34	Haque Mohammad Munirul, Michitaka Kameyama	Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
34	Yngvar Berg, Øivind Næss, Snorre Aunet, Renè Jensen, Mats Høvin	Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
34	Naofumi Takagi	Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.	ISMVL	2002	DBLP DOI BibTeX RDF	carry-save form, carry-propagation-free addition, multiplier recoding, computer arithmetic, signed-digit number representation, digit-recurrence algorithm
34	Harald Sack, Elena Dubrova, Christoph Meinel	Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions.	ISMVL	2000	DBLP DOI BibTeX RDF
34	K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic	Low-Energy Logic Circuit Techniques for Multiple-Valued Logic.	ISMVL	1996	DBLP DOI BibTeX RDF
34	Toshio Baba, Tetsuya Uemura	Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits .	ISMVL	1997	DBLP DOI BibTeX RDF
33	Aryan Saed, Majid Ahmadi, Graham A. Jullien	A Number System with Continuous Valued Digits and Modulo Arithmetic.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	continuous digits, modulo arithmetic, low-noise circuitry, Computer arithmetic, multiple-valued logic
33	Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González	Circuit Design using Resonant Tunneling Diodes.	VLSI Design	1998	DBLP DOI BibTeX RDF	Quantum device, Pipelining, Multiple-Valued Logic, Nanoelectronics, Resonant Tunneling Diode
33	Radomir S. Stankovic, Jaakko Astola	Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule.	ISMVL	2007	DBLP DOI BibTeX RDF
33	Daniel H.-Y. Teng, Ronald J. Bolton	Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique.	ISMVL	2005	DBLP DOI BibTeX RDF