Search results for "parasitics"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Lih-Yih Chiou, Shien-Chun Luo	Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
24	Alireza Khaligh	Realization of Parasitics in Stability of DC-DC Converters Loaded by Constant Power Loads in Advanced Multiconverter Automotive Systems.	IEEE Trans. Ind. Electron.	2008	DBLP DOI BibTeX RDF
24	Wenjian Yu, Xiren Wang, Zuochang Ye, Zeyi Wang	Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
24	I-Lun Tseng	Estimation of Analog Layout Parasitics with Parameterized Polygons		2008	RDF
24	Shuo Wang, Jacobus Daniel van Wyk, Fred C. Lee	Effects of Interactions Between Filter Parasitics and Power Interconnects on EMI Filter Performance.	IEEE Trans. Ind. Electron.	2007	DBLP DOI BibTeX RDF
24	Yassine Hariri, Claude Thibeault	Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
24	Ali Davoudi, Juri Jatskevich	Parasitics Realization in State-Space Average-Value Modeling of PWM DC-DC Converters Using an Equal Area Method.	IEEE Trans. Circuits Syst. I Regul. Pap.	2007	DBLP DOI BibTeX RDF
24	Yaser M. A. Khalifa, Badar K. Khan, Faisal Taha	Multi-objective optimization tool for a free structure analog circuits design using genetic algorithms and incorporating parasitics.	GECCO (Companion)	2007	DBLP DOI BibTeX RDF	genetic algorithms, optimization, analog circuits
24	Zuochang Ye, Zhiping Yu	Parasitics extraction involving 3-D conductors based on multi-layered Green's function.	ASP-DAC	2006	DBLP DOI BibTeX RDF
24	Guchuan Zhu, Julien Penet, Lahcen Saydy	Robust control of an electrostatically actuated MEMS in the presence of parasitics and parametric uncertainties.	ACC	2006	DBLP DOI BibTeX RDF
24	D. H. S. Maithripala, Balasaheb D. Kawade, Jordan M. Berg, Wijesuriya P. Dayawansa	Passivity-Based Control of Electrostatic MEMS in the Presence of Parasitics.	CDC	2006	DBLP DOI BibTeX RDF
24	Frank Felgenhauer, M. Begoin, Wolfgang Mathis	Q-parasitics and their influence to the behaviour of nanoscaled CMOS circuits.	ECCTD	2005	DBLP DOI BibTeX RDF
24	Gabriella Trucco, Giorgio Boselli, Valentino Liberali	A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
24	M. S. B. Sowariraj, Theo Smedes, Cora Salm, Ton J. Mouthaan, Fred G. Kuper	Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels -An explanation and die protection strategy.	Microelectron. Reliab.	2003	DBLP DOI BibTeX RDF
24	Thomas P. Warwick	Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements.	ITC	2003	DBLP DOI BibTeX RDF
24	Veit Dominik Kunz	CMOS compatible vertical surround gate mosfets with reduced parasitics.		2003	RDF
24	Andrea Pacelli	A local circuit topology for inductive parasitics.	ICCAD	2002	DBLP DOI BibTeX RDF
24	Peter Feldmann, Sharad Kapur, David E. Long	Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics.	DATE	1999	DBLP DOI BibTeX RDF
24	Edward W. Y. Liu, Henry C. Chang, Alberto L. Sangiovanni-Vincentelli	Analog System Verification in the Presence of Parasitics Using Behavioral Simulation.	DAC	1993	DBLP DOI BibTeX RDF
24	David L. Standley, John L. Wyatt Jr.	Stability theorem for lateral inhibition networks that is robust in the presence of circuit parasitics.	ICNN	1988	DBLP DOI BibTeX RDF
24	David Overhauser, Ibrahim N. Hajj	A tabular macromodeling approach to fast timing simulation including parasitics.	ICCAD	1988	DBLP DOI BibTeX RDF
24	John L. Wyatt Jr., David L. Standley	A Method for the Design of Stable Lateral Inhibition Networks that is Robust in the Presence of Circuit Parasitics.	NIPS	1987	DBLP BibTeX RDF
24	Shun-Lin Su	Extraction of MOS VLSI Circuit Models Including Critical Interconnect Parasitics		1987	RDF
24	Petros A. Ioannou, C. Richard Johnson Jr.	Reduced-order performance of parallel and series-parallel identifiers with weakly observable parasitics.	Autom.	1983	DBLP DOI BibTeX RDF
24	Kar-Keung D. Young, Petar V. Kokotovic	Analysis of feedback-loop interactions with actuator and sensor parasitics.	Autom.	1982	DBLP DOI BibTeX RDF
12	Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS logic devices, reliability, Markov process, monte carlo method, poisson distribution, laplace transform
12	Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang	Performance-driven analog placement considering boundary constraint.	DAC	2010	DBLP DOI BibTeX RDF	analog placement, boundary constraint, symmetry
12	Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li 0001	Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation.	DAC	2010	DBLP DOI BibTeX RDF	low-dropout regulator, on-chip voltage regulation, power delivery network, power efficiency
12	Yong Zhang 0049, Peng Li 0001, Garng M. Huang	Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis.	DAC	2010	DBLP DOI BibTeX RDF	separatrix, SRAM, dynamic stability
12	Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli	Graphene based transistors: physics, status and future perspectives.	ISPD	2009	DBLP DOI BibTeX RDF	cnfet, gnr-fet., graphene, carbon nanotubes
12	Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng	Efficient power network analysis with complete inductive modeling.	ISQED	2009	DBLP DOI BibTeX RDF
12	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Almitra Pradhan, Ranga Vemuri	Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
12	Rafael Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández 0001	An Integrated Layout-Synthesis Approach for Analog ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
12	Renato Rimolo-Donadio, Christian Schuster, Xiaoxiong Gu, Young Hoon Kwark, Mark B. Ritter	Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects.	DATE	2008	DBLP DOI BibTeX RDF
12	Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel	A capacitance solver for incremental variation-aware extraction.	ICCAD	2008	DBLP DOI BibTeX RDF
12	Ranko Sredojevic, Vladimir Stojanovic	Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example.	ICCAD	2008	DBLP DOI BibTeX RDF
12	Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alexandre Yakovlev, Gordon Russell 0002	The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk.	SLIP	2008	DBLP DOI BibTeX RDF	cross-talk, interconnect, variability, Bit Error Rate(BER)
12	Hariharan Sankaran, Srinivas Katkoori	Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis.	DELTA	2008	DBLP DOI BibTeX RDF	Simulated Annealing, HLS, Encoding, Crosstalk, Binding, Reordering
12	Ruxandra-Liana Costea, Corneliu A. Marinov	Time Evaluation for WTA Hopfield Type Circuits Affected by Cross-Coupling Capacitances.	ICONIP (2)	2008	DBLP DOI BibTeX RDF
12	Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong	Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
12	Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain	Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's.	DATE	2007	DBLP DOI BibTeX RDF
12	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
12	Asha Balijepalli, Saurabh Sinha, Yu Cao	Compact modeling of carbon nanotube transistor for early stage process-design exploration.	ISLPED	2007	DBLP DOI BibTeX RDF	optimum delay, schottky-barrier, surface potential, modeling, process variability, CNT
12	Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim	Placement and routing of RF embedded passive designs in LCP substrate.	ICCD	2007	DBLP DOI BibTeX RDF
12	Andreas G. Katsiamis, Henry M. D. Ip, Emmanuel M. Drakakis	A Practical CMOS Companding Sinh Lossy Integrator.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Massimo Alioto, Gaetano Palumbo	High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Hamid Nejati, Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud	Modeling and Design of Ultrawideband Low Noise Amplifiers with Generalized Impedance Matching Networks.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Jere A. M. Järvinen, Mikko Saukoski, Kari Halonen	A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Chanseok Hwang, Peng Rong, Massoud Pedram	Sleep transistor distribution in row-based MTCMOS designs.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage minimization, placement, MTCMOS
12	Subramanian Rajagopalan, Shabbir H. Batterywala	A 3-dimensional FEM Based Resistance Extraction.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou 0001	Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Huiying Yang, Ranga Vemuri	Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Mark M. Budnik, Kaushik Roy 0001	A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Brock J. LaMeres, Sunil P. Khatri	Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission.	DATE	2006	DBLP DOI BibTeX RDF
12	Mark M. Budnik, Kaushik Roy 0001	Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network.	DATE	2006	DBLP DOI BibTeX RDF
12	Daniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali	Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs.	SBCCI	2006	DBLP DOI BibTeX RDF	crosstalk, mixed-signal ICs
12	Shweta Shah, Nazanin Mansouri, Adrián Núñez-Aldana	Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
12	Ali Davoudi, Juri Jatskevich	State-space averaging of switched-inductor-cell for PWM dc-dc converters considering conduction losses in both operational modes.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Bo-Shih Huang, Ming-Dou Ker	New matching methodology of low-noise amplifier with ESD protection.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Cameron T. Charles, David J. Allstot	A 2-GHz integrated CMOS reflective-type phase shifter with 675° control range.	ISCAS	2006	DBLP DOI BibTeX RDF
12	R. Jancke, P. Schwarz	Supporting analog synthesis by abstracting circuit behavior using a modeling methodology.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Massimo Alioto, Gaetano Palumbo	Nanometer MCML gates: models and design considerations.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Shu-Hui Tu, J. Neil Ross, Chun-Ming Chang	Analytical synthesis of current-mode even-Nth-order single-ended-input OTA and equal-capacitor elliptic filter structure with the minimum components.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Tino Heijmen, Damien Giot, Philippe Roche	Factors That Impact the Critical Charge of Memory Elements.	IOLTS	2006	DBLP DOI BibTeX RDF
12	Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud	Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	narrow-band, low noise amplifier, noise figure
12	Jindrich Zejda, Li Ding 0002	TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks.	ISQED	2006	DBLP DOI BibTeX RDF
12	Benjamin Sheahan, John W. Fattaruso, Jennifer Wong, Karlheinz Muth, Boris Murmann	4.25 Gb/s laser driver: design challenges and EDA tool limitations.	DAC	2006	DBLP DOI BibTeX RDF	electrical to optical interface, laser diode, laser driver
12	Bikram Baidya, Tamal Mukherjee	Layout verification for mixed-domain integrated MEMS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Miodrag Vujkovic, David Wadkins, Carl Sechen	Efficient Post-layout Power-Delay Curve Generation.	PATMOS	2005	DBLP DOI BibTeX RDF
12	Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra	Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits.	DATE	2005	DBLP DOI BibTeX RDF
12	Rong Jiang 0002, Charlie Chung-Ping Chen	Comprehensive frequency dependent interconnect extraction and evaluation methodology.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity
12	Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang 0001, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De	Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.	ISLPED	2005	DBLP DOI BibTeX RDF	Vt mismatch, Vt variation, random dopant variation, threshold voltage variation, transistor mismatch, transistor threshold voltage mismatch, process variation, CMOS, integrated circuits, variation, transistors, threshold voltage, mismatch, body bias, Vt
12	Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara	Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines.	ICCD	2005	DBLP DOI BibTeX RDF
12	David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler	Indirect programming of floating-gate transistors.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
12	Hui Zhang 0057, Preethi Karthik, Hua Tang, Alex Doboli	An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
12	Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada	Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
12	Mohammad Hekmat, Shahriar Mirabbasi, Majid Hashemi	Ground bounce calculation due to simultaneous switching in deep sub-micron integrated circuits.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
12	Amitava Bhaduri, Ranga Vemuri	Moment-driven coupling-aware routing methodology.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	coupling-aware, routing, moments
12	Andres Teene, Bob Davis, Ruggero Castagnetti, Jeff Brown, S. Ramesh 0004	Impact of Interconnect Process Variations on Memory Performance and Design.	ISQED	2005	DBLP DOI BibTeX RDF
12	Sani R. Nassif, Zhuo Li 0001	A More Effective CEFF.	ISQED	2005	DBLP DOI BibTeX RDF
12	Ghanshyam Nayak, Clyde Washburn, P. R. Mukund	System in a Package Design of a RF Front End System Using Application Specific Reduced Order Models.	VLSI Design	2005	DBLP DOI BibTeX RDF
12	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel	ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips.	VLSI Design	2005	DBLP DOI BibTeX RDF
12	Huiyun Li, A. Theodore Markettos, Simon W. Moore	Security Evaluation Against Electromagnetic Analysis at Design Time.	CHES	2005	DBLP DOI BibTeX RDF	EM side-channel analysis, design time security evaluation, smart card
12	Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira	A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
12	Jiri Haze, Radimir Vrba	ADC Position-Sense Interface.	ECBS	2004	DBLP DOI BibTeX RDF
12	Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis	An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain.	DATE	2004	DBLP DOI BibTeX RDF
12	Robert A. Mullen	RF design methodologies bridging system-IC-module design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
12	Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik	HiSIM: hierarchical interconnect-centric circuit simulator.	ICCAD	2004	DBLP DOI BibTeX RDF
12	Mohamed Elgebaly, Manoj Sachdev	Efficient adaptive voltage scaling system through on-chip critical path emulation.	ISLPED	2004	DBLP DOI BibTeX RDF	low-power, CMOS, adaptive voltage scaling
12	Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma	XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs.	ICCD	2004	DBLP DOI BibTeX RDF
12	Davide Pandini, Cristiano Forzan, Livio Baldi	Design Methodologies and Architecture Solutions for High-Performance Interconnects.	ICCD	2004	DBLP DOI BibTeX RDF
12	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel	Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model.	DFT	2004	DBLP DOI BibTeX RDF
12	Ji Luo 0003, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang 0001, Kuan-Jung Chung, Anthony L. Wilson	A High Performance Radiation-Hard Field Programmable Analog Array .	ISQED	2004	DBLP DOI BibTeX RDF
12	Sherif Hammouda, Mohamed Dessouky, Mohamed Tawfik, Wael M. Badawy	A Fully Automated Approach for Analog Circuit Reuse.	IWSOC	2004	DBLP DOI BibTeX RDF
12	Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley	A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.	DAC	2004	DBLP DOI BibTeX RDF	modeling, synthesis, layout, sizing, parasitic, radio frequency
12	Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Maximizing throughput over parallel wire structures in the deep submicrometer regime.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Payam Heydari, Massoud Pedram	Ground bounce in digital VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
12	Jérôme Lescot, François J. R. Clément	Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF