Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
24 | Lih-Yih Chiou, Shien-Chun Luo |
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 17(11), pp. 1659-1663, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Alireza Khaligh |
Realization of Parasitics in Stability of DC-DC Converters Loaded by Constant Power Loads in Advanced Multiconverter Automotive Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 55(6), pp. 2295-2305, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Wenjian Yu, Xiren Wang, Zuochang Ye, Zeyi Wang |
Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8), pp. 1508-1513, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | I-Lun Tseng |
Estimation of Analog Layout Parasitics with Parameterized Polygons ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2008 |
RDF |
|
24 | Shuo Wang, Jacobus Daniel van Wyk, Fred C. Lee |
Effects of Interactions Between Filter Parasitics and Power Interconnects on EMI Filter Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 54(6), pp. 3344-3352, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Yassine Hariri, Claude Thibeault |
Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 1(6), pp. 694-705, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Ali Davoudi, Juri Jatskevich |
Parasitics Realization in State-Space Average-Value Modeling of PWM DC-DC Converters Using an Equal Area Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(9), pp. 1960-1967, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Yaser M. A. Khalifa, Badar K. Khan, Faisal Taha |
Multi-objective optimization tool for a free structure analog circuits design using genetic algorithms and incorporating parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (Companion) ![In: Genetic and Evolutionary Computation Conference, GECCO 2007, Proceedings, London, England, UK, July 7-11, 2007, Companion Material, pp. 2527-2534, 2007, ACM, 978-1-59593-698-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
genetic algorithms, optimization, analog circuits |
24 | Zuochang Ye, Zhiping Yu |
Parasitics extraction involving 3-D conductors based on multi-layered Green's function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 689-693, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Guchuan Zhu, Julien Penet, Lahcen Saydy |
Robust control of an electrostatically actuated MEMS in the presence of parasitics and parametric uncertainties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACC ![In: American Control Conference, ACC 2006, Minneapolis, MN, USA, 14-16 June, 2006, 2006, IEEE, 1-4244-0209-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | D. H. S. Maithripala, Balasaheb D. Kawade, Jordan M. Berg, Wijesuriya P. Dayawansa |
Passivity-Based Control of Electrostatic MEMS in the Presence of Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDC ![In: 45th IEEE Conference on Decision and Control, CDC 2006, San Diego, CA, USA, December 13-15, 2006, pp. 615-620, 2006, IEEE, 1-4244-0171-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Frank Felgenhauer, M. Begoin, Wolfgang Mathis |
Q-parasitics and their influence to the behaviour of nanoscaled CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: Proceedings of the 2005 European Conference on Circuit Theory and Design, ECCTD 2005, Cork, Ireland, August 29th - September 1st 2005, pp. 229-232, 2005, IEEE, 0-7803-9066-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Gabriella Trucco, Giorgio Boselli, Valentino Liberali |
A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 138-147, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | M. S. B. Sowariraj, Theo Smedes, Cora Salm, Ton J. Mouthaan, Fred G. Kuper |
Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels -An explanation and die protection strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 43(9-11), pp. 1569-1575, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Thomas P. Warwick |
Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 537-544, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Veit Dominik Kunz |
CMOS compatible vertical surround gate mosfets with reduced parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2003 |
RDF |
|
24 | Andrea Pacelli |
A local circuit topology for inductive parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 208-214, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Peter Feldmann, Sharad Kapur, David E. Long |
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 418-417, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Edward W. Y. Liu, Henry C. Chang, Alberto L. Sangiovanni-Vincentelli |
Analog System Verification in the Presence of Parasitics Using Behavioral Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 159-163, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
24 | David L. Standley, John L. Wyatt Jr. |
Stability theorem for lateral inhibition networks that is robust in the presence of circuit parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNN ![In: Proceedings of International Conference on Neural Networks (ICNN'88), San Diego, CA, USA, July 24-27, 1988, pp. 27-36, 1988, IEEE. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | David Overhauser, Ibrahim N. Hajj |
A tabular macromodeling approach to fast timing simulation including parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1988 IEEE International Conference on Computer-Aided Design, ICCAD 1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical Papers, pp. 70-73, 1988, IEEE Computer Society, 0-8186-0869-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | John L. Wyatt Jr., David L. Standley |
A Method for the Design of Stable Lateral Inhibition Networks that is Robust in the Presence of Circuit Parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NIPS ![In: Neural Information Processing Systems, Denver, Colorado, USA, 1987, pp. 860-868, 1987, American Institue of Physics, 0-88318-569-5. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP BibTeX RDF |
|
24 | Shun-Lin Su |
Extraction of MOS VLSI Circuit Models Including Critical Interconnect Parasitics ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1987 |
RDF |
|
24 | Petros A. Ioannou, C. Richard Johnson Jr. |
Reduced-order performance of parallel and series-parallel identifiers with weakly observable parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autom. ![In: Autom. 19(1), pp. 75-80, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
|
24 | Kar-Keung D. Young, Petar V. Kokotovic |
Analysis of feedback-loop interactions with actuator and sensor parasitics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Autom. ![In: Autom. 18(5), pp. 577-582, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
12 | Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky |
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 281-286, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CMOS logic devices, reliability, Markov process, monte carlo method, poisson distribution, laplace transform |
12 | Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang |
Performance-driven analog placement considering boundary constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 292-297, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog placement, boundary constraint, symmetry |
12 | Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li 0001 |
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 831-836, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
low-dropout regulator, on-chip voltage regulation, power delivery network, power efficiency |
12 | Yong Zhang 0049, Peng Li 0001, Garng M. Huang |
Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 567-572, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
separatrix, SRAM, dynamic stability |
12 | Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli |
Graphene based transistors: physics, status and future perspectives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 65-66, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cnfet, gnr-fet., graphene, carbon nanotubes |
12 | Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng |
Efficient power network analysis with complete inductive modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 770-775, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan |
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 307-312, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Almitra Pradhan, Ranga Vemuri |
Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 131-136, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Rafael Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández 0001 |
An Integrated Layout-Synthesis Approach for Analog ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), pp. 1179-1189, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Renato Rimolo-Donadio, Christian Schuster, Xiaoxiong Gu, Young Hoon Kwark, Mark B. Ritter |
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 252-255, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel |
A capacitance solver for incremental variation-aware extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 662-669, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Ranko Sredojevic, Vladimir Stojanovic |
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 314-321, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alexandre Yakovlev, Gordon Russell 0002 |
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 65-72, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cross-talk, interconnect, variability, Bit Error Rate(BER) |
12 | Hariharan Sankaran, Srinivas Katkoori |
Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 454-457, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Simulated Annealing, HLS, Encoding, Crosstalk, Binding, Reordering |
12 | Ruxandra-Liana Costea, Corneliu A. Marinov |
Time Evaluation for WTA Hopfield Type Circuits Affected by Cross-Coupling Capacitances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (2) ![In: Advances in Neuro-Information Processing, 15th International Conference, ICONIP 2008, Auckland, New Zealand, November 25-28, 2008, Revised Selected Papers, Part II, pp. 885-892, 2008, Springer, 978-3-642-03039-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 845-857, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain |
Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1520-1525, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram |
Sizing and placement of charge recycling transistors in MTCMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 791-796, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Asha Balijepalli, Saurabh Sinha, Yu Cao |
Compact modeling of carbon nanotube transistor for early stage process-design exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 2-7, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
optimum delay, schottky-barrier, surface potential, modeling, process variability, CNT |
12 | Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim |
Placement and routing of RF embedded passive designs in LCP substrate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 273-279, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Andreas G. Katsiamis, Henry M. D. Ip, Emmanuel M. Drakakis |
A Practical CMOS Companding Sinh Lossy Integrator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3303-3306, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Massimo Alioto, Gaetano Palumbo |
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2998-3001, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Hamid Nejati, Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud |
Modeling and Design of Ultrawideband Low Noise Amplifiers with Generalized Impedance Matching Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2622-2625, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Jere A. M. Järvinen, Mikko Saukoski, Kari Halonen |
A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1713-1716, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Chanseok Hwang, Peng Rong, Massoud Pedram |
Sleep transistor distribution in row-based MTCMOS designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 235-240, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
leakage minimization, placement, MTCMOS |
12 | Subramanian Rajagopalan, Shabbir H. Batterywala |
A 3-dimensional FEM Based Resistance Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 565-570, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou 0001 |
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 875-880, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Huiying Yang, Ranga Vemuri |
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 201-206, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Mark M. Budnik, Kaushik Roy 0001 |
A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(12), pp. 1336-1346, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Brock J. LaMeres, Sunil P. Khatri |
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 522-527, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Mark M. Budnik, Kaushik Roy 0001 |
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1116-1121, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Daniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali |
Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 226-231, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
crosstalk, mixed-signal ICs |
12 | Shweta Shah, Nazanin Mansouri, Adrián Núñez-Aldana |
Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONIELECOMP ![In: 16th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2006), 27 February 2005 - 1 March 2006, Cholula, Puebla, Mexico, pp. 38, 2006, IEEE Computer Society, 0-7695-2505-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Ali Davoudi, Juri Jatskevich |
State-space averaging of switched-inductor-cell for PWM dc-dc converters considering conduction losses in both operational modes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Bo-Shih Huang, Ming-Dou Ker |
New matching methodology of low-noise amplifier with ESD protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Cameron T. Charles, David J. Allstot |
A 2-GHz integrated CMOS reflective-type phase shifter with 675° control range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | R. Jancke, P. Schwarz |
Supporting analog synthesis by abstracting circuit behavior using a modeling methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Massimo Alioto, Gaetano Palumbo |
Nanometer MCML gates: models and design considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Shu-Hui Tu, J. Neil Ross, Chun-Ming Chang |
Analytical synthesis of current-mode even-Nth-order single-ended-input OTA and equal-capacitor elliptic filter structure with the minimum components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Tino Heijmen, Damien Giot, Philippe Roche |
Factors That Impact the Critical Charge of Memory Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 57-62, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud |
Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 187-191, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
narrow-band, low noise amplifier, noise figure |
12 | Jindrich Zejda, Li Ding 0002 |
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 147-152, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Benjamin Sheahan, John W. Fattaruso, Jennifer Wong, Karlheinz Muth, Boris Murmann |
4.25 Gb/s laser driver: design challenges and EDA tool limitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 863-866, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
electrical to optical interface, laser diode, laser driver |
12 | Bikram Baidya, Tamal Mukherjee |
Layout verification for mixed-domain integrated MEMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), pp. 563-577, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Miodrag Vujkovic, David Wadkins, Carl Sechen |
Efficient Post-layout Power-Delay Curve Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 393-403, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra |
Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1064-1069, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Rong Jiang 0002, Charlie Chung-Ping Chen |
Comprehensive frequency dependent interconnect extraction and evaluation methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1070-1073, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel |
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 22-27, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity |
12 | Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang 0001, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De |
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 26-29, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Vt mismatch, Vt variation, random dopant variation, threshold voltage variation, transistor mismatch, transistor threshold voltage mismatch, process variation, CMOS, integrated circuits, variation, transistors, threshold voltage, mismatch, body bias, Vt |
12 | Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara |
Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 243-248, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler |
Indirect programming of floating-gate transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2172-2175, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Hui Zhang 0057, Preethi Karthik, Hua Tang, Alex Doboli |
An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5629-5632, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada |
Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5561-5564, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Mohammad Hekmat, Shahriar Mirabbasi, Majid Hashemi |
Ground bounce calculation due to simultaneous switching in deep sub-micron integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5617-5620, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Amitava Bhaduri, Ranga Vemuri |
Moment-driven coupling-aware routing methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 390-395, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
coupling-aware, routing, moments |
12 | Andres Teene, Bob Davis, Ruggero Castagnetti, Jeff Brown, S. Ramesh 0004 |
Impact of Interconnect Process Variations on Memory Performance and Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 694-699, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Sani R. Nassif, Zhuo Li 0001 |
A More Effective CEFF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 648-653, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Ghanshyam Nayak, Clyde Washburn, P. R. Mukund |
System in a Package Design of a RF Front End System Using Application Specific Reduced Order Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 878-881, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel |
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 354-359, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
12 | Huiyun Li, A. Theodore Markettos, Simon W. Moore |
Security Evaluation Against Electromagnetic Analysis at Design Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 280-292, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
EM side-channel analysis, design time security evaluation, smart card |
12 | Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira |
A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2), pp. 293-301, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Jiri Haze, Radimir Vrba |
ADC Position-Sense Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 11th IEEE International Conference on the Engineering of Computer-Based Systems (ECBS 2004), 24-27 May 2004, Brno, Czech Republic, pp. 429-434, 2004, IEEE Computer Society, 0-7695-2125-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis |
An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 39-45, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Robert A. Mullen |
RF design methodologies bridging system-IC-module design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 491-498, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik |
HiSIM: hierarchical interconnect-centric circuit simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 489-496, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Mohamed Elgebaly, Manoj Sachdev |
Efficient adaptive voltage scaling system through on-chip critical path emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 375-380, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low-power, CMOS, adaptive voltage scaling |
12 | Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma |
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 208-215, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Davide Pandini, Cristiano Forzan, Livio Baldi |
Design Methodologies and Architecture Solutions for High-Performance Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 152-159, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel |
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 174-182, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Ji Luo 0003, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang 0001, Kuan-Jung Chung, Anthony L. Wilson |
A High Performance Radiation-Hard Field Programmable Analog Array . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 522-527, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Sherif Hammouda, Mohamed Dessouky, Mohamed Tawfik, Wael M. Badawy |
A Fully Automated Approach for Analog Circuit Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 237-240, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley |
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 155-158, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
modeling, synthesis, layout, sizing, parasitic, radio frequency |
12 | Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen |
Maximizing throughput over parallel wire structures in the deep submicrometer regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(2), pp. 224-243, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Payam Heydari, Massoud Pedram |
Ground bounce in digital VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(2), pp. 180-193, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Jérôme Lescot, François J. R. Clément |
Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 101-110, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|